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CN113990744A - Single-side inclined plane grid silicon carbide MOSFET device with deep L-shaped base region and preparation method thereof - Google Patents

Single-side inclined plane grid silicon carbide MOSFET device with deep L-shaped base region and preparation method thereof Download PDF

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CN113990744A
CN113990744A CN202111322446.2A CN202111322446A CN113990744A CN 113990744 A CN113990744 A CN 113990744A CN 202111322446 A CN202111322446 A CN 202111322446A CN 113990744 A CN113990744 A CN 113990744A
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silicon carbide
ohmic contact
gate
base region
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董志华
刘辉
刘国华
程知群
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Hangzhou University Of Electronic Science And Technology Fuyang Institute Of Electronic Information Co ltd
Hangzhou Dianzi University
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Hangzhou Dianzi University
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Abstract

本发明公开了带深L形基区的单侧斜面栅碳化硅MOSFET器件及其制备方法，其中主要步骤为S80，为得到栅槽，对碳化硅进行第一次刻蚀，一次刻蚀所用掩膜包含一种低刻蚀选择比和一种较高刻蚀选择比的两种掩膜，分别用于形成栅槽下半部分的斜面和垂直面结构；S90，为得到栅槽，对碳化硅进行第二次刻蚀，刻蚀掩膜为刻蚀选择比较高的掩膜，用于形成两侧都为垂直面的槽；S100，高温干氧氧化形成栅介质。本发明保证栅氧化层的可靠性，在器件反向阻断时，栅氧化层的电场强度能降低到很低，并且施加保护结构后也不影响器件的正向导通性能，保证导通电阻不会增加，电流输出能力不会降低。

Figure 202111322446

The invention discloses a single-side slope gate silicon carbide MOSFET device with a deep L-shaped base region and a preparation method thereof. The main step is S80. The film includes two masks with a low etching selectivity ratio and a high etching selectivity ratio, which are respectively used to form the inclined plane and vertical plane structure of the lower half of the gate trench; S90, in order to obtain the gate trench, the silicon carbide is The second etching is performed, and the etching mask is a relatively high mask for etching, which is used to form a groove with vertical planes on both sides; S100, high temperature dry oxygen oxidation forms a gate dielectric. The invention ensures the reliability of the gate oxide layer. When the device is reversely blocked, the electric field strength of the gate oxide layer can be reduced to a very low level, and the forward conduction performance of the device is not affected after the protection structure is applied, so that the on-resistance is not affected. will increase and the current output capability will not decrease.

Figure 202111322446

Description

Single-side inclined plane grid silicon carbide MOSFET device with deep L-shaped base region and preparation method thereof
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a single-side inclined plane gate silicon carbide MOSFET device with a deep L-shaped base region and a preparation method thereof.
Background
Silicon carbide (SiC) is one of the third generation wide bandgap semiconductors, which has many superior and unique electrical, mechanical and chemical properties, including: the material has the advantages of large forbidden band width, high electron and hole mobility, extremely high hardness, high wear resistance, high quality factor Q, high thermal conductivity, high chemical corrosion resistance and the like, so that the material has wide application prospect in the fields of high-power, high-temperature and high-frequency power electronics.
The SiC UMOSFET structure is characterized in that a U-shaped groove gate exists, a channel is vertical to the surface of the device, and JFET (junction field effect transistor) resistance inside the device is eliminated powerfully. Under the same conditions, the on-resistance of the UMOS structure device is significantly reduced. In addition, the channel region and the source region of the UMOS structure can be formed by epitaxial growth, so that the adverse effect caused by an ion implantation method can be avoided, the silicon carbide UMOS structure is more advantageous, and smaller on-resistance can be obtained.
The silicon carbide UMOSFET structure also has a very important problem of itself, that is, in the blocking state of the device, the electric field intensity of the oxide layer at the bottom of the UMOS groove is very high, about 2.5 times of the electric field intensity of the peak value of the PN junction, while the electric field at the bottom corner of the groove is more concentrated due to the two-dimensional effect, and the electric field intensity is higher, so that the gate oxide layer of the silicon carbide UMOSFET device at the corner of the groove gate is more likely to break down first, thereby causing the reliability reduction of the device.
The following 4 typical solutions exist in the prior art:
1. the P-type electric field shielding structure is placed and attached to the bottom of the groove, and the P-type shielding layer can well protect the gate dielectric when reverse blocking is carried out, so that the electric field intensity at the corner of the gate groove is not too large, and the failure of a device is caused. However, when the device is in forward conduction, a new JFET area is formed, so that the conduction channel of current is narrowed, the on-resistance is increased, and the conduction capability of the current is reduced.
2. The P-type base region on one side is extended downwards and surrounds one side of the gate structure and part of the gate bottom, the structure can ensure the gate oxide reliability of the device, but half of the channel is sacrificed at the same time, so that the current output capability of the device is reduced too much.
3. A low-on-resistance silicon carbide MOSFET device containing a built-in floating space region and a preparation method thereof. The 3P + floating shielding layers are additionally arranged in the drift region at a certain distance below the gate structure, so that the defect that the silicon carbide MOSFET structure with the second conduction type gate oxide protection region has larger on-resistance is overcome, and meanwhile, a new electric field peak is introduced into the second conduction type floating region, so that the breakdown voltage of the device is increased.
4. The traditional vertical gate structure is changed into a V-shaped gate structure, namely, an inclined crystal plane is used for replacing a vertical plane. The semiconductor device can suppress channel resistance of a trench gate type semiconductor device and realize further reduction in on-resistance.
Disclosure of Invention
Therefore, a technical scheme is needed to be provided, which can ensure the reliability of the gate oxide layer, reduce the electric field intensity of the gate oxide layer to be very low when the device is reversely blocked, and also have no influence on the forward conduction performance of the device after a protection structure is applied, ensure that the on-resistance is not increased, and keep the current output capability at a higher level.
In order to achieve the aim, the invention provides a preparation method of a single-side inclined plane grid silicon carbide MOSFET device with a deep L-shaped base region, which comprises the following steps: the method comprises the following steps:
s10, epitaxially growing an N-drift layer on the silicon carbide N + substrate;
s20, forming a P + shielding layer on the N-drift layer through ion implantation;
s30, then epitaxially growing an N-drift layer;
s40, forming an N-type current spreading layer on the N-drift layer through ion implantation;
s50, forming a P-type base region on the N-drift region through ion implantation;
s60, forming an N + ohmic contact region on the N-drift region through ion implantation;
s70, forming a P + ohmic contact region on the N-drift region through ion implantation;
s80, for obtaining the gate slot, etching the silicon carbide for the first time, wherein the mask used for the first etching comprises two masks with a low etching selection ratio and a higher etching selection ratio, and the two masks are respectively used for forming the inclined plane and the vertical plane structure of the lower half part of the gate slot, wherein the mask with the low etching selection ratio means that the etching selection ratio of the silicon carbide to the mask is 0.2:1 to 1:1 mask; the mask with higher etching selection ratio refers to a mask with the etching selection ratio of silicon carbide to the mask being more than 2: 1;
s90, in order to obtain a gate groove, performing second etching on the silicon carbide, wherein the etching mask is a mask with higher etching selection ratio and is used for forming a groove with two sides being vertical surfaces, and the mask with higher etching selection ratio is a mask with etching selection ratio of the silicon carbide to the mask being more than 2: 1;
s100, performing high-temperature dry oxygen oxidation to form a gate dielectric, wherein the high temperature is 1100-1500 ℃;
s110, filling the gate groove with high-doped polysilicon, wherein the high-doped polysilicon is doped with boron ions or phosphorus ions in a doping range of 1 × 1019cm-3To x 1020cm-3To (c) to (d);
and S120, preparing and forming a grid on the upper surface of the polycrystalline silicon, forming a first source electrode above the first P + ohmic contact region and the first N + ohmic contact region, forming a second source electrode above the second P + ohmic contact region and the second N + ohmic contact region, and preparing and forming a drain electrode on the lower surface of the substrate layer.
Preferably, in the step S10, an N-drift layer is epitaxially grown on the silicon carbide N + substrate, wherein the N-drift layer is doped with nitrogen and phosphorus, and the doping concentration is 5 × 1015cm-3To 8X 1015cm-3In the meantime.
Preference is given toAnd S20, forming a P + shielding layer on the N-drift layer by ion implantation, wherein the P + shielding layer is doped with aluminum and boron at a doping concentration of 1 × 1019cm-3To 2X 1019cm-3The thickness of the doped region is 0.2 to 0.5 μm.
Preferably, S30, and then epitaxially growing an N-drift layer, specifically, epitaxially growing an N-drift layer with the same doping concentration as that of the N-drift region above the above structure, wherein the thickness of the N-drift layer is 3.5 to 4.5 μm, and the doping manner is the same as that of the lower N-drift layer in S10.
Preferably, in S40, an N-type current spreading layer is formed on the N-drift layer by ion implantation, specifically, an N-type current spreading region is formed by ion implantation of nitrogen or phosphorus, and the doping concentration is 1 × 1017cm-3To 2X 1017cm-3The thickness of the doped region is between 0.15 and 0.25 μm.
Preferably, in S50, the P-type base region is formed on the N-drift region by ion implantation, and is a second L-type base region is formed by ion implantation of aluminum or boron, and the doping concentration is 1 × 1017cm-3To 1X 1018cm-3(ii) a Then forming a first P-type base region by aluminum or boron ion implantation with a doping concentration of 1 × 1017cm-3To 2X 1017cm-3The thickness of the doped region is between 0.5 and 1 μm.
Preferably, in S60, an N + ohmic contact region is formed on the N-drift region by ion implantation, specifically, a first N + ohmic contact region and a second N + ohmic contact region are formed by ion implantation of nitrogen or phosphorus, and the doping concentration is 1 × 1019cm-3To 1X 1020cm-3The thickness of the doped region is between 0.2 and 0.25 μm.
Preferably, in S70, a P + ohmic contact region is formed on the N-drift region by ion implantation, specifically, a first P + ohmic contact region and a second P + ohmic contact region are formed by ion implantation of aluminum or boron, and the doping concentration is 1 × 1019cm-3To 1X 1020cm-3The thickness of the doped region is between 0.2 and 0.25 μm.
Based on the purpose, the invention also provides a single-side inclined plane gate silicon carbide MOSFET device with the deep L-shaped base region, and the preparation method comprises the steps of sequentially forming drain metal, a silicon carbide N + substrate above the drain metal, an N-drift region on the N + substrate, a P + shielding layer in an N-drift layer, a gate structure above the N-drift layer, a first P-type base region on the left side of the gate structure above the N-drift layer, a second P-type base region on the right side of the gate structure above the N-drift layer, a first P + ohmic contact region on the left side above the first P-type base region, a first N + ohmic contact region on the right side above the first P-type base region, an N-type current expansion layer below the first P-type base region, a second N + ohmic contact region on the left side above the second P-type base region, and a second P + ohmic contact region on the right side above the second P-type base region from bottom to top; a first source metal is arranged above the first P + ohmic contact region and the first N + ohmic contact region; a second source metal is arranged above the second P + ohmic contact region and the second N + ohmic contact region; the gate structure comprises polysilicon, a gate dielectric surrounding the bottom and the side wall of the polysilicon, and gate metal arranged above the polysilicon.
Preferably, the bottom of the grid structure is one side of an inclined plane, and the included angle between the inclined plane and the horizontal plane is 30-60 degrees; the distance between the top of the P + shielding layer and the bottommost part of the grid structure is 0.5-2 mu m.
The beneficial effects of the invention at least comprise:
1. the existing protective structure for the gate oxide medium is either a P + shielding layer or a deep L-shaped P-type base region. According to the invention, through the combined structure of the P + shielding layer and the deep L-shaped P-type base region, the gate oxide medium can be protected to the greatest extent when the device is reversely blocked, the electric field intensity at the gate oxide medium is ensured to be far lower than 3MV/cm, and the long-term reliability of the device is improved;
2. the two sides of the existing grid structure are mostly vertical surfaces, and the groove angle is of a right-angle structure, so that the electric field intensity of the groove angle is easily overlarge. The bottom of one side of the gate structure is of an inclined plane structure, so that the phenomenon of electric field concentration on the gate oxide medium is reduced to a certain extent, and when the device is conducted in the forward direction, the electric field intensity between the P + shielding layer and the special inclined plane structure at the bottom of the gate structure is larger, so that the drift speed of electrons in the device is increased, and the current density is increased. Therefore, when the gate oxide medium is protected, the special structure can well ensure that the on-resistance cannot be increased, and the current conducting capacity is kept at a higher level.
Drawings
In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:
fig. 1 is a cross-sectional view of the overall structure of a single-sided bevel-gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 2 is a device structure diagram after S10 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 3 is a device structure diagram after S20 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 4 is a device structure diagram after S30 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 5 is a device structure diagram after S51 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 6 is a device structure diagram after S40 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 7 is a device structure diagram after S52 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 8 is a device structure diagram after S60 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 9 is a device structure diagram after S70 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 10 is a device structure diagram after S80 of a method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 11 is a device structure diagram after S90 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 12 is a device structure diagram after S100 of a method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 13 is a device structure diagram after S110 of the method for manufacturing a single-sided bevel gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention;
fig. 14 is a device structure diagram after S120 of the method for manufacturing a single-side bevel-gate silicon carbide MOSFET device with a deep L-shaped base region according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The preparation method of the single-side inclined plane grid silicon carbide MOSFET device with the deep L-shaped base region comprises the following steps:
s10, epitaxially growing an N-drift layer with a certain thickness on the N + substrate, wherein the drift layer is doped with nitrogen and phosphorus and the doping concentration is 5 multiplied by 1015cm-3To 8X 1015cm-3In the meantime.
S20, forming a P + shielding layer inside the N-drift layer by aluminum ion implantation, wherein the P + shielding layer is doped with aluminum and boron, and the doping concentration is 1 × 1019cm-3To 2X 1019cm-3The thickness of the doped region is 0.2 to 0.5 μm.
And S30, growing an N-drift layer with the same doping concentration as the N-drift region above the structure in an epitaxial mode above the N-drift layer, wherein the thickness of the N-drift layer is 3.5-4.5 mu m, and the doping mode is the same as that of the lower N-drift layer.
S51, forming a second L-shaped P-type base region above the N-drift layer by means of aluminum or boron ion implantation with the doping concentration of 1 × 1017cm-3To 1X 1018cm-3。
S40, forming an N-type current spreading layer by nitrogen or phosphorus ion implantation with a doping concentration of 1 × 10 above the N-drift layer17cm-3To 2X 1017cm-3The thickness of the doped region is 0.15To 0.25 μm.
S52, forming a first P-type base region above the N-drift layer by means of aluminum or boron ion implantation with the doping concentration of 1 × 1017cm-3To 2X 1017cm-3The thickness of the doped region is between 0.5 and 1 μm.
S60, forming a first N + ohmic contact region and a second N + ohmic contact region above the N-drift layer by nitrogen or phosphorus ion implantation with a doping concentration of 1 × 1019cm-3To 1X 1020cm-3The thickness of the doped region is between 0.2 and 0.25 μm.
S70, forming a first P + ohmic contact region and a second P + ohmic contact region above the N-drift layer by implanting aluminum or boron ions with a doping concentration of 1 × 1019cm-3To 1X 1020cm-3The thickness of the doped region is between 0.2 and 0.25 μm.
S80, etching the silicon carbide for the first time to form a gate groove with a side inclined plane structure and a side vertical structure, wherein the mask with a low etching selection ratio refers to a mask with the etching selection ratio of the silicon carbide to the mask being 0.2:1 to 1:1, for example: photoresist, a mask with a higher etching selectivity ratio refers to a mask with a silicon carbide to mask etching selectivity ratio of more than 2:1, for example: silica, alumina, nickel, copper, chromium, and the like; in the specific embodiment, two masks are used in one etching, the mask with a low etching selectivity is photoresist, the mask with a high etching selectivity is silicon dioxide or aluminum oxide, the mask with a low etching selectivity can be used for forming an inclined plane due to the fact that the mask with a low etching selectivity is subjected to lateral etching seriously, the hard mask with a high etching selectivity has a small lateral etching effect and can be used for forming a vertical plane, and the etching depth is 1.5-2 microns.
S90, performing second etching on the silicon carbide to form the upper half part of the gate groove with the two sides of the gate groove in a vertical structure, wherein the mask with the higher etching selection ratio is a mask with the etching selection ratio of the silicon carbide to the mask being more than 2:1, such as: silica, alumina, nickel, copper, chromium, and the like; in a specific embodiment, the mask with higher etching selectivity is silicon dioxide or aluminum oxide, and the etching depth is 1-1.5 μm.
And S100, carrying out dry oxygen oxidation at the temperature of 1100-1500 ℃ to form gate dielectric silicon dioxide, and forming silicon dioxide with the thickness of 45-55 nm on the vertical surfaces on two sides of the gate structure.
S110, depositing polysilicon in the etched gate groove, and doping P type, wherein the doped ions are boron ions or phosphorus ions, and the doping range is 1 × 1019cm-3To x 1020cm-3To (c) to (d); and then high-temperature goods returning activation is carried out, wherein the high temperature range is between 1000 ℃ and 1200 ℃.
And S120, preparing and forming a grid on the upper surface of the polycrystalline silicon, wherein the metal is Al. And forming a first source electrode above the first P + ohmic contact region and the first N + ohmic contact region, wherein the metal is Ni/Al, Ni/Ti, Al/Ti/Ni and the like. And forming a second source electrode above the second P + ohmic contact region and the second N + ohmic contact region, wherein the metal is Ni/Al, Ni/Ti, Al/Ti/Ni and the like. And preparing and forming a drain electrode on the lower surface of the substrate layer, wherein the used metal is Ni, Ni/Ti/Ag and the like, and the temperature for carrying out high-temperature annealing on the grown metal is between 750 ℃ and 1050 ℃.
The device cross-sectional view obtained by the preparation method of the single-side inclined plane gate silicon carbide MOSFET device with the deep L-shaped base region is shown in figure 1, and comprises drain metal 12 from bottom to top in sequence; a silicon carbide N + substrate 11 over the drain metal 12; an N-drift region 10 on an N + substrate 11; a P + shield layer 9 in the N-drift layer; a gate structure above the N-drift layer 10, a first P-type base region 5 on the left side of the gate structure above the N-drift layer 10, a second P-type base region 51 on the right side of the gate structure above the N-drift layer 10, a first P + ohmic contact region 3 on the left side above the first P-type base region 5, a first N + ohmic contact region 4 on the right side above the first P-type base region 5, an N-type current spreading layer 6 below the first P-type base region 5, a second N + ohmic contact region 41 on the left side above the second P-type base region 51, and a second P + ohmic contact region 31 on the right side above the second P-type base region 51; a first source metal 2 is arranged above the first P + ohmic contact region 3 and the first N + ohmic contact region 4; a second source metal 21 is arranged above the second P + ohmic contact region 31 and the second N + ohmic contact region 41; the gate structure comprises polycrystalline silicon 7, a gate dielectric 8 surrounding the bottom and the side wall of the polycrystalline silicon 7 and gate metal 1 arranged above the polycrystalline silicon 6; wherein alpha represents the included angle between the inclined plane part at the bottom of the grid structure and the surface of the device, and the included angle ranges from 30 degrees to 60 degrees; h represents the distance from the top of the P + shielding layer to the bottom of the gate structure, and is in the range of 0.5 to 2 μm. .
Referring to fig. 2, which is a structural diagram of the device after S10, S10, an N-drift layer 10 with a certain thickness is epitaxially grown on an N + substrate 11, the drift layer is doped with nitrogen and phosphorus, and the doping concentration is 5 × 1015cm-3To 8X 1015cm-3In the meantime.
Referring to fig. 3, which is a structural diagram of the device after S20, S20, a P + shielding layer 9 is formed inside the N-drift layer 10 by means of aluminum ion implantation, wherein the P + shielding layer 9 is doped with aluminum and boron, and the doping concentration is 1 × 1019cm-3To 2X 1019cm-3The thickness of the doped region is 0.2 to 0.5 μm.
Referring to fig. 4, which is a structure diagram of the device after S30, S30 grows an N-drift layer 10 with the same doping concentration as that of the N-drift region 10 above the N-drift layer 10 by epitaxy, and the thickness of the N-drift layer 10 is 3.5 to 4.5 μm, and the doping manner is the same as that of the underlying N-drift layer 10.
Referring to fig. 5, which is a structural diagram of the device after S51, S51, an L-shaped second P-type base region 51 is formed above the N-drift layer 10 by ion implantation of aluminum or boron, with a doping concentration of 1 × 1017cm-3To 1X 1018cm-3。
Referring to fig. 6, which is a structural view of the device after S40, S40, an N-type current spreading layer 6 is formed by implanting nitrogen or phosphorus ions above the N-drift layer 10, with a doping concentration of 1 × 1017cm-3To 2X 1017cm-3The thickness of the doped region is between 0.15 and 0.25 μm.
Referring to fig. 7, which is a structural diagram of the device after S52, S52, a first P-type base region 5 is formed by implanting aluminum or boron ions above the N-drift layer 10, with a doping concentration of 1 × 1017cm-3To 2X 1017cm-3The thickness of the doped region is between 0.5 and 1 μm.
Referring to FIG. 8, which is a structural diagram of the device after S60, S60, in the N-drift layer10, forming a first N + ohmic contact region 4 and a second N + ohmic contact region 41 by implanting nitrogen or phosphorus ions with a doping concentration of 1 × 1019cm-3To 1X 1020cm-3The thickness of the doped region is between 0.2 and 0.25 μm.
Referring to fig. 9, which is a structural view of the device after S70, S70, a first P + ohmic contact region 3 and a second P + ohmic contact region 31 are formed by implanting al or b ions above the N-drift layer 10, with a doping concentration of 1 × 1019cm-3To 1X 1020cm-3The thickness of the doped region is between 0.2 and 0.25 μm.
Referring to fig. 10, which is a structure diagram of the device after S80, S80 performs a first etching on the silicon carbide to form a gate trench having a side-slope structure and a side-vertical structure, where the mask with a low etching selectivity refers to a mask with an etching selectivity of the silicon carbide to the mask being 0.2:1 to 1:1, for example: photoresist, a mask with a higher etching selectivity ratio refers to a mask with a silicon carbide to mask etching selectivity ratio of more than 2:1, for example: silica, alumina, nickel, copper, chromium, and the like; in the specific embodiment, two masks are used in one etching, the mask with a low etching selectivity is photoresist, and the mask with a high etching selectivity is silicon dioxide or aluminum oxide, as shown in fig. 11, the mask with a low etching selectivity can be used for forming an inclined plane due to the fact that the mask with a low etching selectivity is subjected to relatively serious lateral etching, the hard mask with a high etching selectivity has a relatively small lateral etching effect and can be used for forming a vertical plane, and the etching depth is 1.5-2 μm.
Referring to fig. 11, which is a structure diagram of the device after S90, S90 performs a second etching on the silicon carbide to form an upper half portion of the gate trench with a vertical structure on both sides, where the mask with a higher etching selectivity ratio refers to a mask with an etching selectivity ratio of silicon carbide to the mask being greater than 2:1, for example: silica, alumina, nickel, copper, chromium, and the like; in a specific embodiment, the mask with higher etching selectivity is silicon dioxide or aluminum oxide, and the etching depth is 1-1.5 μm.
Referring to fig. 12, which is a structural diagram of the device after S100, dry oxidation is performed at an oxidation temperature of 1100 ℃ to 1500 ℃ to form gate dielectric silicon dioxide, and silicon dioxide with a thickness of 45 nm to 55nm is formed on two side vertical surfaces of the gate structure.
Referring to fig. 13, which is a structural diagram of the device after S110, polysilicon deposition is performed in the etched gate trench, and P-type doping is performed, where the doped ions are boron ions or phosphorus ions, and the doping range is 1 × 1019cm-3To x 1020cm-3To (c) to (d); and then high-temperature goods returning activation is carried out, wherein the high temperature range is between 1000 ℃ and 1200 ℃.
Referring to fig. 14, which is a structure diagram of the device after S120, in S120, a gate metal 1 is prepared and formed on the upper surface of the polysilicon 7, and the used metal is Al. A first source metal 2 is formed over the first P + ohmic contact region 3 and the first N + ohmic contact region 4 using Ni/Al, Ni/Ti, Al/Ti/Ni, etc. A second source metal 21 is formed over the second P + ohmic contact region 31 and the second N + ohmic contact region 41 using Ni/Al, Ni/Ti, Al/Ti/Ni, etc. And preparing and forming drain electrode metal 12 on the lower surface of the substrate layer, wherein the used metal is Ni, Ni/Ti/Ag and the like, and the temperature for carrying out high-temperature annealing on the grown metal is between 750 ℃ and 1050 ℃.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims (10)

1. A preparation method of a single-side inclined plane grid silicon carbide MOSFET device with a deep L-shaped base region is characterized by comprising the following steps:
s10, epitaxially growing an N-drift layer on the silicon carbide N + substrate;
s20, forming a P + shielding layer on the N-drift layer through ion implantation;
s30, then epitaxially growing an N-drift layer;
s40, forming an N-type current spreading layer on the N-drift layer through ion implantation;
s50, forming a P-type base region on the N-drift region through ion implantation;
s60, forming an N + ohmic contact region on the N-drift region through ion implantation;
s70, forming a P + ohmic contact region on the N-drift region through ion implantation;
s80, for obtaining the gate slot, etching the silicon carbide for the first time, wherein the mask used for the first etching comprises two masks with a low etching selection ratio and a higher etching selection ratio, and the two masks are respectively used for forming the inclined plane and the vertical plane structure of the lower half part of the gate slot, wherein the mask with the low etching selection ratio means that the etching selection ratio of the silicon carbide to the mask is 0.2:1 to 1:1 mask; the mask with higher etching selection ratio refers to a mask with the etching selection ratio of silicon carbide to the mask being more than 2: 1;
s90, in order to obtain a gate groove, performing second etching on the silicon carbide, wherein the etching mask is a mask with higher etching selection ratio and is used for forming a groove with two sides being vertical surfaces, and the mask with higher etching selection ratio is a mask with etching selection ratio of the silicon carbide to the mask being more than 2: 1;
s100, performing high-temperature dry oxygen oxidation to form a gate dielectric, wherein the high temperature is 1100-1500 ℃;
s110, filling the gate groove with high-doped polysilicon, wherein the high-doped polysilicon is doped with boron ions or phosphorus ions in a doping range of 1 × 1019cm-3To x 1020cm-3To (c) to (d);
and S120, preparing and forming a grid on the upper surface of the polycrystalline silicon, forming a first source electrode above the first P + ohmic contact region and the first N + ohmic contact region, forming a second source electrode above the second P + ohmic contact region and the second N + ohmic contact region, and preparing and forming a drain electrode on the lower surface of the substrate layer.
2. The method for fabricating the single-sided bevel-gate silicon carbide MOSFET device with the deep L-shaped base region as claimed in claim 1, wherein S10, an N-drift layer is epitaxially grown on a silicon carbide N + substrate, wherein the N-drift layer is doped with nitrogen and phosphorus and has a doping concentration of 5 x 1015cm-3To 8X 1015cm-3In the meantime.
3. The method for manufacturing the single-sided inclined plane grid silicon carbide MOSFET device with the deep L-shaped base region as claimed in claim 1, wherein S20, a P + shielding layer is formed on the N-drift layer by ion implantation, wherein the P + shielding layer is doped with aluminum and boron, and the doping concentration is 1 x 1019cm-3To 2X 1019cm-3The thickness of the doped region is 0.2 to 0.5 μm.
4. The method for manufacturing the single-sided bevel gate silicon carbide MOSFET device with the deep L-shaped base region as claimed in claim 2, wherein the step S30 is followed by epitaxially growing an N-drift layer, specifically, an N-drift layer with the same doping concentration as that of the N-drift region is epitaxially grown on the structure, and the thickness of the N-drift layer is 3.5 to 4.5 μm, and the doping method is the same as that of the N-drift layer of the lower layer in the step S10.
5. The method for manufacturing the single-sided bevel gate silicon carbide MOSFET device with the deep L-shaped base region as claimed in claim 1, wherein in step S40, an N-type current spreading layer is formed on the N-drift layer by ion implantation, specifically, an N-type current spreading region is formed by nitrogen or phosphorus ion implantation, and the doping concentration is 1 x 1017cm-3To 2X 1017cm-3The thickness of the doped region is between 0.15 and 0.25 μm.
6. The method for manufacturing the single-sided inclined plane grid silicon carbide MOSFET device with the deep L-shaped base region as claimed in claim 1, wherein in step S50, a P-type base region is formed on the N-drift region by ion implantation, and an L-type second P-type base region is formed by ion implantation of aluminum or boron, wherein the doping concentration is 1 x 1017cm-3To 1X 1018cm-3(ii) a Then forming a first P-type base region by aluminum or boron ion implantation with a doping concentration of 1 × 1017cm-3To 2X 1017cm-3The thickness of the doped region is between 0.5 and 1 μm.
7. According to claim 1The preparation method of the single-side inclined plane grid silicon carbide MOSFET device with the deep L-shaped base region is characterized in that S60, an N + ohmic contact region is formed on the N-drift region through ion implantation, specifically, a first N + ohmic contact region and a second N + ohmic contact region are formed through nitrogen or phosphorus ion implantation, and the doping concentration is 1 x 1019cm-3To 1X 1020cm-3The thickness of the doped region is between 0.2 and 0.25 μm.
8. The method for manufacturing the single-sided bevel gate silicon carbide MOSFET device with the deep L-shaped base region as claimed in claim 1, wherein S70 is implemented by ion implantation on the N-drift region to form a P + ohmic contact region, specifically, a first P + ohmic contact region and a second P + ohmic contact region are formed by ion implantation of aluminum or boron, and the doping concentration is 1 x 1019cm-3To 1X 1020cm-3The thickness of the doped region is between 0.2 and 0.25 μm.
9. A single-side bevel gate silicon carbide MOSFET device with a deep L-shaped base region prepared by the preparation method of any one of claims 1 to 8, the device is characterized by comprising a drain metal, a silicon carbide N + substrate above the drain metal, an N-drift region on the N + substrate, a P + shielding layer in the N-drift layer, a gate structure above the N-drift layer, a first P-type base region on the left side of the gate structure above the N-drift layer, a second P-type base region on the right side of the gate structure above the N-drift layer, a first P + ohmic contact region on the left side above the first P-type base region, a first N + ohmic contact region on the right side above the first P-type base region, an N-type current expansion layer below the first P-type base region, a second N + ohmic contact region on the left side above the second P-type base region and a second P + ohmic contact region on the right side above the second P-type base region from bottom to top in sequence; a first source metal is arranged above the first P + ohmic contact region and the first N + ohmic contact region; a second source metal is arranged above the second P + ohmic contact region and the second N + ohmic contact region; the gate structure comprises polysilicon, a gate dielectric surrounding the bottom and the side wall of the polysilicon, and gate metal arranged above the polysilicon.
10. The single-sided bevel gate silicon carbide MOSFET device with the deep L-shaped base region as claimed in claim 1, wherein the bevel of the beveled side of the bottom of the gate structure forms an angle of 30 ° -60 ° with the horizontal; the distance between the top of the P + shielding layer and the bottommost part of the grid structure is 0.5-2 mu m.
CN202111322446.2A 2021-11-09 2021-11-09 Single-side inclined plane grid silicon carbide MOSFET device with deep L-shaped base region and preparation method thereof Pending CN113990744A (en)

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