[go: up one dir, main page]

CN113972623A - DC Surge Suppression Circuit Based on NMOS Tube - Google Patents

DC Surge Suppression Circuit Based on NMOS Tube Download PDF

Info

Publication number
CN113972623A
CN113972623A CN202111153544.8A CN202111153544A CN113972623A CN 113972623 A CN113972623 A CN 113972623A CN 202111153544 A CN202111153544 A CN 202111153544A CN 113972623 A CN113972623 A CN 113972623A
Authority
CN
China
Prior art keywords
voltage
capacitor
diode
resistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111153544.8A
Other languages
Chinese (zh)
Inventor
许文进
谭诚
殷赫
周蔚琦
薛雅心
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Electric Control Research Institute China South Industries Group Co ltd
Original Assignee
Shanghai Electric Control Research Institute China South Industries Group Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Electric Control Research Institute China South Industries Group Co ltd filed Critical Shanghai Electric Control Research Institute China South Industries Group Co ltd
Priority to CN202111153544.8A priority Critical patent/CN113972623A/en
Publication of CN113972623A publication Critical patent/CN113972623A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/005—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection avoiding undesired transient conditions
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
    • H02H3/202—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage for DC systems
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
    • H02H3/22—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage of short duration, e.g. lightning
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Landscapes

  • Dc-Dc Converters (AREA)

Abstract

The invention provides a direct current surge suppression circuit based on an NMOS (N-channel metal oxide semiconductor) tube, which comprises: the peak pulse suppression circuit comprises a peak pulse suppression circuit, a voltage stabilizing circuit, a bootstrap booster circuit, a control module and an electronic switch; the spike pulse suppression circuit is connected with the output end Vin of the power supply to suppress the voltage of the plus or minus 250V spike pulse; the voltage stabilizing circuit is connected with the bootstrap booster circuit to provide power supply voltage for a 555 timer of the bootstrap booster circuit; the bootstrap booster circuit is connected with the electronic switch to ensure that an NMOS (N-channel metal oxide semiconductor) tube of the electronic switch can be normally conducted under normal voltage; the control module is connected with the electronic switch to control the connection and disconnection of the NMOS tube of the electronic switch. Compared with PMOS, the surge suppression circuit based on NMOS has strong reliability, the circuit has more selectivity for bearing high-voltage NMOS above 250V, the price of PMOS is generally higher, the price of NMOS tube adopted by the invention is low, and the manufacturing cost is reduced.

Description

Direct current surge suppression circuit based on NMOS pipe
Technical Field
The invention relates to the field of surge voltage suppression, in particular to a direct current surge suppression circuit based on an NMOS (N-channel metal oxide semiconductor) tube.
Background
For some electrical equipment in specific environment and application, the power supply of the electrical equipment is often accompanied by surge voltage impact, particularly for military vehicles, a surge suppression module is required to be added at the input front end of a power module of the electrical equipment so as to protect subsequent circuits, and the surge voltage of 40V/50ms and 100V/50ms and the peak pulse voltage of +/-250V, which are specified in the standard of GJB298-87 military vehicle 28V direct current electrical system characteristic, are mainly suppressed within a normal working voltage range, so that the surge voltage suppression and peak pulse voltage suppression functions of the military vehicle are realized, and the electrical equipment is prevented from being damaged due to the failure of the power module caused by abnormal operation or misoperation of a 28V electrical system of the military vehicle.
The existing surge suppression circuit is mostly used for suppressing surge voltage by using a TVS transient diode or a piezoresistor in civil aspects, but the reliability is poor. In a surge suppression power module disclosed in patent CN 206542180U, a PMOS is mainly used as a control switch, and although the circuit structure of the surge suppression power module based on the PMOS is relatively simple, the PMOS on the market is generally high in price and poor in reliability, and few PMOS can bear a high voltage of more than 250V. At present, most imported surge suppression chips LT4363 are adopted for military use, and the price of the domestic surge suppression chips is generally higher. Therefore, a domestic direct current surge suppression circuit with low cost and strong reliability is needed.
In chinese patent publication No. CN110676828A, a dc surge suppressing circuit is disclosed, which comprises an electronic switch module, a limiting circuit module, an input end sampling circuit module, a control circuit module of the electronic switch module, an output end sampling circuit module, and a control circuit module of the limiting circuit module, the electronic switch module is connected with the amplitude limiting circuit module in parallel to form a double-channel circuit which is connected between the direct-current voltage input end and the output end in series, the electronic switch module performs sampling and control through the input end sampling circuit module and the control circuit module, the amplitude limiting circuit module performs sampling and control through the output end sampling circuit module and the control circuit module, the problems that the suppression voltage of the existing direct current surge voltage suppression circuit is higher than the normal voltage, and the sizes of the on-resistance of the switch and the amplitude limiting device are inconsistent with the modulation voltage range can be effectively solved.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a direct current surge suppression circuit based on an NMOS (N-channel metal oxide semiconductor) tube.
According to the invention, the DC surge suppression circuit based on the NMOS tube comprises: the peak pulse suppression circuit comprises a peak pulse suppression circuit, a voltage stabilizing circuit, a bootstrap booster circuit, a control module and an electronic switch;
the spike pulse suppression circuit is connected with the output end Vin of the power supply to suppress the voltage of the plus or minus 250V spike pulse;
the voltage stabilizing circuit is connected with the bootstrap booster circuit to provide power supply voltage for a 555 timer of the bootstrap booster circuit;
the bootstrap booster circuit is connected with the electronic switch to ensure that an NMOS (N-channel metal oxide semiconductor) tube of the electronic switch can be normally conducted under normal voltage;
the control module is connected with the electronic switch to control the connection and disconnection of the NMOS tube of the electronic switch.
Preferably, the spike suppression circuit includes a transient diode TVS1 and a bypass capacitor CP1, the bypass capacitor CP1 is connected in parallel with the transient diode TVS1, one end of the bypass capacitor CP1 and one end of the transient diode TVS1 are connected to the output terminal Vin of the power supply, and the other end of the transient diode TVS1 and the other end of the bypass capacitor CP1 are both grounded.
Preferably, the voltage stabilizing circuit comprises a current limiting resistor R1, a voltage stabilizing diode D1 and a charging capacitor C1;
one end of the current-limiting resistor R1 is connected with the output end of the spike suppression circuit, the other end of the current-limiting resistor R1 is connected with one end of the charging capacitor C1 and the cathode of the voltage stabilizing diode D1, and the other end of the charging capacitor C1 and the anode of the voltage stabilizing diode D1 are both connected with the ground.
Preferably, the bootstrap boost circuit includes an oscillation circuit, a voltage doubling module, and a filter capacitor C8; the oscillation circuit is connected with the output of the voltage stabilizing circuit, the output of the oscillation circuit is connected with the voltage doubling module, the output of the voltage doubling module is connected with one end of the filter capacitor C8, and the other end of the filter capacitor C8 is grounded.
Preferably, the oscillating circuit comprises a 555 timer, a resistor R2, a resistor R3, a charging capacitor C6 and a filter capacitor C7;
the resistor R2, the resistor R3 and the charging capacitor C6 are sequentially connected in series, one end of the resistor R2 is connected with the other end of the resistor R1, and the other end of the charging capacitor C6 is grounded;
the GND pin of the 555 timer is grounded, the TRI pin and the THR pin of the 555 timer are connected and connected with one end of a charging capacitor C6, the RES pin and the VDD pin of the 555 timer are connected and connected with the other end of a resistor R1, the CON pin of the 555 timer is connected with one end of a filter capacitor C7, the other end of the filter capacitor C7 is grounded, the DIS pin of the 555 timer is connected with the other end of a resistor R2, and the OUT pin of the 555 timer is connected with the voltage doubling module.
Preferably, the oscillation frequency and the duty ratio of the oscillation circuit are determined by a resistor R2, a resistor R3, and a charging capacitor C6, and the oscillation frequency of the oscillation circuit is: 1.44/((R))2+2R3)·C6The duty ratio of the oscillation circuit is: d ═ R1+R2)/(R1+2R2)。
Preferably, the voltage-doubling module comprises a voltage-doubling capacitor C2, a voltage-doubling capacitor C3, a voltage-doubling capacitor C4, a voltage-doubling capacitor C5, a diode D4, a diode D5, a diode D6 and a diode D7;
the voltage-multiplying capacitor C2, the voltage-multiplying capacitor C3, the diode D4 and the diode D5 form a first-stage voltage-multiplying circuit, and the voltage-multiplying capacitor C4, the voltage-multiplying capacitor C5, the diode D6 and the diode D7 form a second-stage voltage-multiplying circuit;
one end of the voltage-multiplying capacitor C2 is connected with an OUT pin of the 555 timer, the other end of the voltage-multiplying capacitor C2 is respectively connected with the cathode of a diode D4 and the anode of a diode D5, the anode of the diode D4 is respectively connected with the other end of a resistor R1 and one end of a voltage-multiplying capacitor C3, and the cathode of the diode D5 is connected with the other end of the voltage-multiplying capacitor C3;
one end of the voltage-multiplying capacitor C4 is connected with an OUT pin of the 555 timer, the other end of the voltage-multiplying capacitor C4 is respectively connected with the cathode of the diode D6 and the cathode of the diode D7, the anode of the diode D6 is respectively connected with the other end of the voltage-multiplying capacitor C3 and one end of the voltage-multiplying capacitor C5, and the anode of the diode D7 is respectively connected with the other end of the voltage-multiplying capacitor C5 and one end of the filter capacitor C8.
Preferably, the control module comprises a voltage dividing resistor R7, a voltage dividing resistor R8, an operational amplifier U2, a zener diode D2, a zener diode D3, a zener diode D9, a current limiting resistor R4, a current limiting resistor R5 and an NMOS transistor Q1;
one end of the voltage dividing resistor R7 is connected with one end of a resistor R1, the other end of the voltage dividing resistor R7 is connected with one end of a voltage dividing resistor R8, the other end of the voltage dividing resistor R8 is grounded, one ends of the current limiting resistor R4 and the current limiting resistor R5 are connected and then connected with the output end Vin of the power supply, the other end of the current limiting resistor R4 is connected with the positive power end of the operational amplifier U2 and the negative electrode of the zener diode D2, the other end of the current limiting resistor R5 is connected with the inverting input end of the operational amplifier U2 and the negative electrode of the zener diode D3, the positive electrodes of the zener diode D2 and the zener diode D3 are connected and then grounded, the non-inverting input end of the operational amplifier U2 is connected with the other end of the voltage dividing resistor R7, the output end of the operational amplifier U2 is connected with one end of a resistor R9, and the other end of the resistor R9 is connected with the negative electrode of the zener diode D9, the zener diode D632, the negative electrode of the zener diode D, The grid of the NMOS tube Q1 is connected, the anode of the voltage stabilizing diode D9 is connected with the source of the NMOS tube Q1 and grounded, and the drain of the NMOS tube Q1 is connected with the electronic switch.
Preferably, the electronic switch includes an NMOS transistor Q2 and a zener diode D8, a drain of the NMOS transistor Q2 is connected to one end of a resistor R1, a gate of the NMOS transistor Q2 is connected to one end of a resistor R6, a cathode of the zener diode D8 and a drain of the NMOS transistor Q1, the other end of the resistor R6 is connected to one end of a filter capacitor C8, a source of the NMOS transistor Q2 is connected to an anode of the zener diode D8 to form an output Vout terminal, and the output Vout terminal is connected to the electric device.
Preferably, the withstand voltage value of the NMOS transistor Q2 is 300V.
Compared with the prior art, the invention has the following beneficial effects:
1. the NMOS-based surge suppression circuit has high reliability compared with PMOS, and the circuit has more selectivity for bearing high-voltage NMOS above 250V.
2. Compared with the common high price of PMOS in the current market, the NMOS transistor adopted by the invention has low price, and the manufacturing cost is reduced.
3. All devices required by the invention are provided with corresponding manufacturers at home, and autonomous control and localization can be realized so as to overcome the problem of foreign chip neck clamping.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of the electrical system of the present invention;
fig. 2 is a circuit diagram of an electrical system surge voltage suppression circuit of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
The invention introduces a direct current surge suppression circuit based on an NMOS (N-channel metal oxide semiconductor) tube, which is shown in figure 1 and comprises the following components: the peak pulse suppression circuit comprises a peak pulse suppression circuit, a voltage stabilizing circuit, a bootstrap booster circuit, a control module and an electronic switch; the spike pulse suppression circuit is connected with the output end Vin of the power supply to suppress the plus or minus 250V spike pulse voltage; the voltage stabilizing circuit is connected with the bootstrap booster circuit to provide power supply voltage for a 555 timer of the bootstrap booster circuit; the bootstrap booster circuit is connected with the electronic switch to ensure that an NMOS tube of the electronic switch can be normally conducted under normal voltage; the control module is connected with the electronic switch to control the connection and disconnection of the NMOS tube of the electronic switch.
Referring to fig. 2, the spike suppression circuit includes a transient diode TVS1 and a bypass capacitor CP1, the bypass capacitor CP1 is connected in parallel with the transient diode TVS1, one end of the bypass capacitor CP1 and one end of the transient diode TVS1 are connected to the output terminal Vin of the power supply, and the other end of the transient diode TVS1 and the other end of the bypass capacitor CP1 are both grounded.
The voltage stabilizing circuit comprises a current limiting resistor R1, a voltage stabilizing diode D1 and a charging capacitor C1; one end of a current-limiting resistor R1 is connected with the output end of the spike pulse suppression circuit, the other end of the current-limiting resistor R1 is connected with one end of a charging capacitor C1 and the cathode of a voltage stabilizing diode D1, and the current-limiting resistor R1 mainly plays a role in protecting the voltage stabilizing diode D1. The voltage stabilizing diode D1 is a 12V/2W voltage stabilizing diode which mainly stabilizes the voltage output by the spike suppression circuit to 12V to supply power to the voltage doubling circuit and provide reference voltage. The charging capacitor C1 is mainly used for supplying power to the voltage doubling circuit when the system is just powered on to ensure the stability of the power supply. The other end of the charging capacitor C1 and the anode of the zener diode D1 are both connected to ground.
The bootstrap booster circuit comprises an oscillating circuit, a voltage doubling module and a filter capacitor C8; the oscillating circuit is connected with the output of the voltage stabilizing circuit, the output of the oscillating circuit is connected with the voltage doubling module, the output of the voltage doubling module is connected with one end of the filter capacitor C8, and the other end of the filter capacitor C8 is grounded.
The oscillating circuit comprises a 555 timer, a resistor R2, a resistor R3, a charging capacitor C6 and a filter capacitor C7; the resistor R2, the resistor R3 and the charging capacitor C6 are sequentially connected in series, one end of the resistor R2 is connected with the other end of the resistor R1, and the other end of the charging capacitor C6 is grounded. The GND pin ground connection of 555 timer, the TRI pin of 555 timer, the THR pin links to each other and is connected with charging capacitor C6's one end, the RES pin of 555 timer, the VDD pin links to each other and is connected with the other end of resistance R1, the CON pin of 555 timer is connected with filter capacitor C7's one end, filter capacitor C7's other end ground connection, the DIS pin of 555 timer is connected with the other end of resistance R2, the OUT pin and the voltage doubling module of 555 timer are connected.
The oscillation frequency and the duty ratio of the oscillation circuit are determined by the resistor R2, the resistor R3, and the charging capacitor C6, and the oscillation frequency of the oscillation circuit: 1.44/((R))2+2R3)·C6Duty ratio of the oscillation circuit: d ═ R2+R3)/(R2+2R3)。
The voltage-multiplying module comprises a voltage-multiplying capacitor C2, a voltage-multiplying capacitor C3, a voltage-multiplying capacitor C4, a voltage-multiplying capacitor C5, a diode D4, a diode D5, a diode D6 and a diode D7. The voltage-multiplying capacitor C2, the voltage-multiplying capacitor C3, the diode D4 and the diode D5 form a first-stage voltage-multiplying circuit, and the voltage-multiplying capacitor C4, the voltage-multiplying capacitor C5, the diode D6 and the diode D7 form a second-stage voltage-multiplying circuit;
one end of a voltage-multiplying capacitor C2 is connected with an OUT pin of the 555 timer, the other end of the voltage-multiplying capacitor C2 is respectively connected with the cathode of a diode D4 and the anode of a diode D5, the anode of the diode D4 is respectively connected with the other end of a resistor R1 and one end of a voltage-multiplying capacitor C3, and the cathode of a diode D5 is connected with the other end of the voltage-multiplying capacitor C3;
one end of a voltage-multiplying capacitor C4 is connected with an OUT pin of the 555 timer, the other end of the voltage-multiplying capacitor C4 is respectively connected with the cathode of a diode D6 and the cathode of a diode D7, the anode of the diode D6 is respectively connected with the other end of a voltage-multiplying capacitor C3 and one end of a voltage-multiplying capacitor C5, and the anode of the diode D7 is respectively connected with the other end of the voltage-multiplying capacitor C5 and one end of a filter capacitor C8.
The principle of the first-stage voltage doubling circuit is that when the pin 3 of the oscillator 555 timer outputs low level, the voltage stabilizing circuit outputs 12V voltage to charge the capacitor C2 through the diode D4, so that the voltage at two ends of the capacitor C2 is 12V; when the 3 pin of the oscillator 555 timer outputs high level, the voltage across the capacitor C2 is again increased to 24V across the C2. Due to the unidirectional conductivity of the diode, the capacitor C2 charges the capacitor C3 through the diode D5 so that the output voltage becomes a double voltage of 24V.
The same second stage voltage doubling circuit is connected in series with the first stage voltage doubling circuit, so that the whole voltage doubling module is changed into a 36V voltage output by the voltage doubling circuit.
The control module comprises a voltage division resistor R7, a voltage division resistor R8, an operational amplifier U2, a voltage stabilizing diode D2, a voltage stabilizing diode D3, a voltage stabilizing diode D9, a current limiting resistor R4, a current limiting resistor R5 and an NMOS tube Q1;
one end of a voltage dividing resistor R7 is connected with one end of a resistor R1, the other end of a voltage dividing resistor R7 is connected with one end of a voltage dividing resistor R8, the other end of the voltage dividing resistor R8 is grounded, one ends of a current limiting resistor R4 and a current limiting resistor R5 are connected and then connected with the output end Vin of a power supply, the other end of a current limiting resistor R4 is respectively connected with the positive power supply end of an operational amplifier U2 and the negative electrode of a 12V/2W voltage stabilizing diode D2, the other end of a current limiting resistor R5 is respectively connected with the inverting input end of the operational amplifier U2 and the negative electrode of a 3V/0.5W voltage stabilizing diode D3, the positive electrode of the voltage stabilizing diode D2 and the positive electrode of the voltage stabilizing diode D3 are connected and then grounded, the non-inverting input end of the operational amplifier U2 is connected with the other end of the voltage dividing resistor R7, the output end of the operational amplifier U2 is connected with one end of a resistor R9, the other end of a resistor R9 is respectively connected with the negative electrode of the voltage stabilizing diode D9, the negative electrode of the voltage stabilizing diode D9 and the negative electrode of the voltage stabilizing diode D9, The grid of the NMOS tube Q1 is connected, the anode of the voltage stabilizing diode D9 is connected with the source of the NMOS tube Q1 and grounded, and the drain of the NMOS tube Q1 is connected with the electronic switch. The 12V/2W Zener diode D2 provides 12V power to the operational amplifier U2, and the 3V/0.5W Zener diode D3 provides 3V reference voltage to the operational amplifier U2. The resistances of the divider resistors R7 and R8 are 10K and 1K, respectively.
The electronic switch comprises an NMOS tube Q2 and a 10V/0.5W voltage stabilizing diode D8, the drain electrode of the NMOS tube Q2 is connected with one end of a resistor R1, the grid electrode of the NMOS tube Q2 is respectively connected with one end of a resistor R6, the negative electrode of a voltage stabilizing diode D8 and the drain electrode of the NMOS tube Q1, the other end of the resistor R6 is connected with one end of a filter capacitor C8, the source electrode of the NMOS tube Q2 is connected with the positive electrode of the voltage stabilizing diode D8 to form an output Vout end, and the output Vout end is connected with electric equipment. The withstand voltage of the NMOS transistor Q2 is 300V.
The principle of DC surge suppression based on the NMOS tube is as follows:
1. when the output voltage Vin of the power supply is 28V, the voltage divided by the voltage dividing resistor R8 is about 2.5V, the voltage of the non-inverting input terminal of the operational amplifier U2 is 2.5V, and the comparison level of the inverting input terminal of the operational amplifier U2 is 3V under the steady voltage of the voltage regulator D2, so that the output of the output terminal of the operational amplifier U2 is low, the NMOS transistor Q1 is turned off, the NMOS transistor Q2 is kept on under the action of the voltage boost circuit, and the output of Vout is 28V.
2. When the power supply generates a peak pulse voltage of +/-250V, the transient energy is larger, and the TVS tube of the peak pulse suppression circuit is used for suppressing and absorbing the energy.
3. When surge voltage of 40V/50ms or 100V/50ms occurs to the power supply, the voltage divided by the voltage dividing resistor R8 is greater than the comparison level 3V of the inverting input end of the operational amplifier U2, the output end of the operational amplifier U2 at the moment is high level 12V, the NMOS tube Q1 is conducted at the moment, the grid of the NMOS tube Q2 is pulled down to be grounded, the NMOS tube Q2 is turned off at the moment, and the subsequent Vout is output to be 0V, so that the subsequent circuit is protected.
Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (10)

1.一种基于NMOS管的直流浪涌抑制电路，其特征在于，包括：尖峰脉冲抑制电路、稳压电路、自举升压电路、控制模块和电子开关；1. a direct current surge suppression circuit based on NMOS tube, is characterized in that, comprises: spike suppression circuit, voltage stabilizer circuit, bootstrap boost circuit, control module and electronic switch; 所述尖峰脉冲抑制电路和供电电源的输出端Vin相连用来抑制±250V尖峰脉冲电压；The spike suppression circuit is connected to the output terminal Vin of the power supply for suppressing the ±250V spike voltage; 所述稳压电路和自举升压电路相连为自举升压电路的555定时器提供电源电压；The voltage regulator circuit is connected with the bootstrap booster circuit to provide power supply voltage for the 555 timer of the bootstrap booster circuit; 所述自举升压电路和电子开关相连以保证正常电压时电子开关的NMOS管能正常导通；The bootstrap boost circuit is connected with the electronic switch to ensure that the NMOS tube of the electronic switch can be normally turned on when the voltage is normal; 所述控制模块和电子开关相连来控制电子开关的NMOS管的导通和截止。The control module is connected with the electronic switch to control the on and off of the NMOS transistor of the electronic switch. 2.根据权利要求1所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述尖峰脉冲抑制电路包括瞬态二极管TVS1和旁路电容CP1，所述旁路电容CP1和瞬态二极管TVS1并联，旁路电容CP1的一端和瞬态二极管TVS1的一端与供电电源的输出端Vin相连，所述瞬态二极管TVS1的另一端和旁路电容CP1的另一端都接地。2. The NMOS transistor-based DC surge suppression circuit according to claim 1, wherein the spike suppression circuit comprises a transient diode TVS1 and a bypass capacitor CP1, and the bypass capacitor CP1 and the transient diode TVS1 is connected in parallel, one end of the bypass capacitor CP1 and one end of the transient diode TVS1 are connected to the output terminal Vin of the power supply, and the other end of the transient diode TVS1 and the other end of the bypass capacitor CP1 are both grounded. 3.根据权利要求1所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述稳压电路包括限流电阻R1、稳压二极管D1和充电电容C1；3. The NMOS tube-based DC surge suppression circuit according to claim 1, wherein the voltage regulator circuit comprises a current limiting resistor R1, a voltage regulator diode D1 and a charging capacitor C1; 所述限流电阻R1的一端与尖峰脉冲抑制电路输出端相连，所述限流电阻R1另一端和充电电容C1的一端、稳压二极管D1的负极相连，所述充电电容C1的另一端和稳压二极管D1的正极均与地相连。One end of the current limiting resistor R1 is connected to the output end of the spike suppression circuit, the other end of the current limiting resistor R1 is connected to one end of the charging capacitor C1 and the negative electrode of the zener diode D1, and the other end of the charging capacitor C1 is connected to the stabilizer. The anodes of the voltage diodes D1 are all connected to the ground. 4.根据权利要求1所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述自举升压电路包括振荡电路、倍压模块以及滤波电容C8；所述振荡电路与稳压电路的输出连接，所述振荡电路的输出与倍压模块连接，所述倍压模块的输出与滤波电容C8的一端连接，所述滤波电容C8的另一端接地。4. The NMOS transistor-based DC surge suppression circuit according to claim 1, wherein the bootstrap boost circuit comprises an oscillation circuit, a voltage multiplier module and a filter capacitor C8; the oscillation circuit and the voltage regulator circuit The output of the oscillating circuit is connected to the voltage doubling module, the output of the voltage doubling module is connected to one end of the filter capacitor C8, and the other end of the filter capacitor C8 is grounded. 5.根据权利要求4所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述振荡电路包括555定时器、电阻R2、电阻R3、充电电容C6以及滤波电容C7；5. The NMOS tube-based DC surge suppression circuit according to claim 4, wherein the oscillation circuit comprises a 555 timer, a resistor R2, a resistor R3, a charging capacitor C6 and a filter capacitor C7; 所述电阻R2、电阻R3和充电电容C6依次串联，所述电阻R2的一端与电阻R1的另一端连接，所述充电电容C6的另一端接地；The resistor R2, the resistor R3 and the charging capacitor C6 are connected in series in sequence, one end of the resistor R2 is connected to the other end of the resistor R1, and the other end of the charging capacitor C6 is grounded; 所述555定时器的GND引脚接地，555定时器的TRI引脚、THR引脚相连并与充电电容C6的一端连接，555定时器的RES引脚、VDD引脚相连并与电阻R1的另一端连接，555定时器的CON引脚与滤波电容C7的一端连接，所述滤波电容C7的另一端接地，555定时器的DIS引脚与电阻R2的另一端连接，所述555定时器的OUT引脚与倍压模块连接。The GND pin of the 555 timer is grounded, the TRI pin and THR pin of the 555 timer are connected to one end of the charging capacitor C6, and the RES pin and VDD pin of the 555 timer are connected to the other end of the resistor R1. One end is connected, the CON pin of the 555 timer is connected to one end of the filter capacitor C7, the other end of the filter capacitor C7 is grounded, the DIS pin of the 555 timer is connected to the other end of the resistor R2, the OUT of the 555 timer The pins are connected with the voltage doubler module. 6.根据权利要求5所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述振荡电路的振荡频率和占空比由电阻R2、电阻R3以及充电电容C6决定，所述振荡电路的振荡频率：f＝1.44/((R2+2R3)·C6，所述振荡电路的占空比：D＝(R2+R3)/(R2+2R3)。6. The NMOS transistor-based DC surge suppression circuit according to claim 5, wherein the oscillation frequency and duty cycle of the oscillation circuit are determined by the resistor R2, the resistor R3 and the charging capacitor C6, and the oscillation circuit The oscillation frequency of : f=1.44/((R 2 +2R 3 )·C 6 , the duty cycle of the oscillation circuit: D=(R 2 +R 3 )/(R 2 +2R 3 ). 7.根据权利要求4所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述倍压模块包括倍压电容C2、倍压电容C3、倍压电容C4、倍压电容C5以及二极管D4、二极管D5、二极管D6、二极管D7；7. The NMOS tube-based DC surge suppression circuit according to claim 4, wherein the voltage doubling module comprises a voltage doubling capacitor C2, a voltage doubling capacitor C3, a voltage doubling capacitor C4, a voltage doubling capacitor C5 and a diode D4, diode D5, diode D6, diode D7; 所述倍压电容C2、倍压电容C3、二极管D4、二极管D5构成第一级二倍压电路，所述倍压电容C4、倍压电容C5、二极管D6、二极管D7构成第二级二倍压电路；The voltage-doubling capacitor C2, the voltage-doubling capacitor C3, the diode D4, and the diode D5 constitute a first-stage double-voltage circuit, and the voltage-doubling capacitor C4, the voltage-doubling capacitor C5, the diode D6, and the diode D7 constitute a second-stage double-voltage circuit. circuit; 所述倍压电容C2的一端与555定时器的OUT引脚连接，所述倍压电容C2的另一端分别与二极管D4负极、二极管D5的正极连接，所述二极管D4的正极分别与电阻R1的另一端、倍压电容C3的一端连接，所述二极管D5的负极与倍压电容C3的另一端连接；One end of the voltage doubling capacitor C2 is connected to the OUT pin of the 555 timer, and the other end of the voltage doubling capacitor C2 is respectively connected to the cathode of the diode D4 and the anode of the diode D5, and the anode of the diode D4 is respectively connected to the resistor R1. The other end is connected to one end of the voltage doubling capacitor C3, and the cathode of the diode D5 is connected to the other end of the voltage doubling capacitor C3; 所述倍压电容C4的一端与555定时器的OUT引脚连接，所述倍压电容C4的另一端分别与二极管D6的负极、二极管D7的负极连接，所述二极管D6的正极分别与倍压电容C3的另一端、倍压电容C5的一端连接，所述二极管D7的正极分别与倍压电容C5的另一端、滤波电容C8的一端连接。One end of the voltage doubling capacitor C4 is connected to the OUT pin of the 555 timer, and the other end of the voltage doubling capacitor C4 is respectively connected to the cathode of the diode D6 and the cathode of the diode D7, and the anode of the diode D6 is respectively connected to the voltage doubler. The other end of the capacitor C3 and one end of the voltage doubling capacitor C5 are connected, and the anodes of the diode D7 are respectively connected to the other end of the voltage doubling capacitor C5 and one end of the filter capacitor C8. 8.根据权利要求1所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述控制模块包括分压电阻R7、分压电阻R8、运算放大器U2、稳压二极管D2、稳压二极管D3、稳压二极管D9、限流电阻R4、限流电阻R5和NMOS管Q1；8. The NMOS tube-based DC surge suppression circuit according to claim 1, wherein the control module comprises a voltage dividing resistor R7, a voltage dividing resistor R8, an operational amplifier U2, a Zener diode D2, a Zener diode D3, Zener diode D9, current limiting resistor R4, current limiting resistor R5 and NMOS transistor Q1; 所述分压电阻R7的一端与电阻R1的一端连接，所述分压电阻R7的另一端与分压电阻R8的一端连接，所述分压电阻R8的另一端接地，所述限流电阻R4和限流电阻R5的一端连接后与供电电源的输出端Vin连接，所述限流电阻R4的另一端分别连接运算放大器U2的正电源端、稳压二极管D2的负极连接，所述限流电阻R5的另一端分别与运算放大器U2的反相输入端、稳压二极管D3的负极连接，所述稳压二极管D2正极和稳压二极管D3的正极连接后接地，所述运算放大器U2的正相输入端与分压电阻R7的另一端连接，所述运算放大器U2的输出端与电阻R9的一端连接，所述电阻R9的另一端分别与稳压二极管D9的负极、NMOS管Q1的栅极连接，所述稳压二极管D9的正极与NMOS管Q1的源极连接并接地，所述NMOS管Q1的漏极与电子开关连接。One end of the voltage dividing resistor R7 is connected to one end of the resistor R1, the other end of the voltage dividing resistor R7 is connected to one end of the voltage dividing resistor R8, the other end of the voltage dividing resistor R8 is grounded, and the current limiting resistor R4 One end of the current limiting resistor R5 is connected to the output terminal Vin of the power supply, and the other end of the current limiting resistor R4 is respectively connected to the positive power supply terminal of the operational amplifier U2 and the negative electrode of the zener diode D2. The other end of R5 is respectively connected to the inverting input terminal of the operational amplifier U2 and the negative pole of the Zener diode D3, the positive pole of the Zener diode D2 is connected to the positive pole of the Zener diode D3 and then grounded, and the non-inverting input of the operational amplifier U2 The terminal is connected to the other end of the voltage dividing resistor R7, the output terminal of the operational amplifier U2 is connected to one end of the resistor R9, and the other end of the resistor R9 is respectively connected to the negative electrode of the Zener diode D9 and the gate of the NMOS transistor Q1, The anode of the Zener diode D9 is connected to the source of the NMOS transistor Q1 and grounded, and the drain of the NMOS transistor Q1 is connected to the electronic switch. 9.根据权利要求1所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述电子开关包括NMOS管Q2和稳压二极管D8，所述NMOS管Q2的漏极连接电阻R1的一端，所述NMOS管Q2的栅极分别连接电阻R6的一端、稳压二极管D8的负极和NMOS管Q1的漏极连接，所述电阻R6的另一端连接滤波电容C8的一端，所述NMOS管Q2的源极与稳压二极管D8的正极连接并构成输出Vout端，所述输出Vout端连接用电设备。9. The NMOS transistor-based DC surge suppression circuit according to claim 1, wherein the electronic switch comprises an NMOS transistor Q2 and a Zener diode D8, and the drain of the NMOS transistor Q2 is connected to one end of a resistor R1 , the gate of the NMOS transistor Q2 is connected to one end of the resistor R6, the negative electrode of the Zener diode D8 is connected to the drain of the NMOS transistor Q1, the other end of the resistor R6 is connected to one end of the filter capacitor C8, the NMOS transistor Q2 The source of the zener diode D8 is connected to the anode of the zener diode D8 to form an output Vout terminal, and the output Vout terminal is connected to the electrical equipment. 10.根据权利要求9所述的基于NMOS管的直流浪涌抑制电路，其特征在于：所述NMOS管Q2的耐压值为300V。10 . The DC surge suppression circuit based on an NMOS transistor according to claim 9 , wherein the withstand voltage value of the NMOS transistor Q2 is 300V. 11 .
CN202111153544.8A 2021-09-29 2021-09-29 DC Surge Suppression Circuit Based on NMOS Tube Pending CN113972623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111153544.8A CN113972623A (en) 2021-09-29 2021-09-29 DC Surge Suppression Circuit Based on NMOS Tube

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111153544.8A CN113972623A (en) 2021-09-29 2021-09-29 DC Surge Suppression Circuit Based on NMOS Tube

Publications (1)

Publication Number Publication Date
CN113972623A true CN113972623A (en) 2022-01-25

Family

ID=79587160

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111153544.8A Pending CN113972623A (en) 2021-09-29 2021-09-29 DC Surge Suppression Circuit Based on NMOS Tube

Country Status (1)

Country Link
CN (1) CN113972623A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120090448A (en) * 2025-05-06 2025-06-03 四川九洲电器集团有限责任公司 A bootstrap boost circuit for achieving surge voltage suppression

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070115022A1 (en) * 1992-02-21 2007-05-24 Elster Electricity, Llc Power supply having voltage blocking clamp
CN101499654A (en) * 2008-10-23 2009-08-05 天水华天微电子股份有限公司 Instant voltage peak and instant voltage surge suppressor
CN201717779U (en) * 2010-04-28 2011-01-19 石家庄国耀电子科技有限公司 Direct-current power supply input end protector of airborne apparatus
CN205178499U (en) * 2015-12-16 2016-04-20 西安森派电子技术有限公司 Direct current excessive pressure surge suppressor
CN205901586U (en) * 2016-08-17 2017-01-18 中国航空无线电电子研究所 Voltage pre -stabilizing circuit with prevent joining conversely function
CN206412760U (en) * 2017-01-25 2017-08-15 无锡天和电子有限公司 A kind of anti-reverse voltage surge, spike and ripple protection circuit
CN208094183U (en) * 2018-03-01 2018-11-13 中国航空无线电电子研究所 Pre- regulator circuit with Surge suppression
CN112993953A (en) * 2021-02-26 2021-06-18 西安微电子技术研究所 High-voltage surge suppression circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070115022A1 (en) * 1992-02-21 2007-05-24 Elster Electricity, Llc Power supply having voltage blocking clamp
CN101499654A (en) * 2008-10-23 2009-08-05 天水华天微电子股份有限公司 Instant voltage peak and instant voltage surge suppressor
CN201717779U (en) * 2010-04-28 2011-01-19 石家庄国耀电子科技有限公司 Direct-current power supply input end protector of airborne apparatus
CN205178499U (en) * 2015-12-16 2016-04-20 西安森派电子技术有限公司 Direct current excessive pressure surge suppressor
CN205901586U (en) * 2016-08-17 2017-01-18 中国航空无线电电子研究所 Voltage pre -stabilizing circuit with prevent joining conversely function
CN206412760U (en) * 2017-01-25 2017-08-15 无锡天和电子有限公司 A kind of anti-reverse voltage surge, spike and ripple protection circuit
CN208094183U (en) * 2018-03-01 2018-11-13 中国航空无线电电子研究所 Pre- regulator circuit with Surge suppression
CN112993953A (en) * 2021-02-26 2021-06-18 西安微电子技术研究所 High-voltage surge suppression circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120090448A (en) * 2025-05-06 2025-06-03 四川九洲电器集团有限责任公司 A bootstrap boost circuit for achieving surge voltage suppression

Similar Documents

Publication Publication Date Title
CN102013802B (en) BOOST circuit with short circuit protection function
CN107027334A (en) Inrush Current Prevention Circuit
CN112383293B (en) Control circuit and chip of intelligent low-side power switch
CN1674438A (en) Circuit for positive power source inputting load electrifying slow starting
CN106058836A (en) Large-current surge suppressor
CN104102318A (en) Power source circuit
CN113972623A (en) DC Surge Suppression Circuit Based on NMOS Tube
CN114465473B (en) Switching power supply circuit with digital surge current suppression function and electronic equipment
CN205004952U (en) Direct current soft start circuit
CN108631565B (en) Two-stage switch power supply
CN104104066B (en) Voltage stabilization control circuit for battery reverse connection protection
CN107959324A (en) Spacecraft power supply system stored energy battery discharge on-off circuit
US20210391715A1 (en) Polarity reversal protection circuit
CN108963999B (en) Surge current suppressor
CN114629481B (en) A high-side drive circuit, drive method, power supply and vehicle
CN111614073B (en) A low-cost power supply reverse connection protection circuit
CN212210492U (en) A low-cost power reverse polarity protection circuit
CN217406170U (en) Drive protection circuit of switch valve and switch valve
CN113241813B (en) Intelligent load identification circuit, method and photovoltaic power generation system
CN106300303A (en) Dash current protection circuit
CN111725787B (en) BOOST direct current short-circuit protection circuit that steps up
CN115882708A (en) Boost-buck power converter supporting power-down delay and conversion method
CN116979819A (en) Power supply circuit of synchronous rectifier, power supply device and power supply equipment
CN214707671U (en) Control circuit and chip of intelligent low-side power switch
CN211352550U (en) A starting load capacity enhancement auxiliary circuit and power supply

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20220125

RJ01 Rejection of invention patent application after publication