CN113921466B - TP (Transmission protocol) reducing RC loading method - Google Patents

Abstract

The present invention discloses a method for reducing TP RC loading, comprising the following steps: S1: a GE layer, i.e., a gate, is made on a glass substrate, a GI layer is made on the basis of the GE layer, a SE layer is made on the basis of the GI layer, and an ES layer is made on the SE layer; S2: an SD layer is then made on the ES layer, and the SD layer and the SE layer are connected to form a complete TFT structure by etching a through hole in the ES layer, and another SD layer is made on the ES layer as a TP wiring; S3: a PV layer is made on the SD layer, an OC layer is made on the PV layer, the drain is connected to the PIXEL ITO, a CH layer is made on the PIXEL ITO, and a VCOM ITO layer is made on the CH layer. The present invention provides a method for reducing TP RC loading, wherein an electrode film layer is added between the GI layer and the ES layer, the Scan signal and the TP signal are shielded, so that the capacitive coupling effect of the TP signal on the Scan signal is greatly reduced, thereby achieving the purpose of optimizing the horizontal stripes of the touch screen. The capacitive coupling of the Scan signal to the TP signal is effectively reduced.

Description

A method for reducing TP RC loading

Technical Field

The invention belongs to the technical field of touch screens, and in particular relates to a method for reducing TP RC loading.

Background Art

In recent years, the touch screen display market has entered a period of product diversification, ranging from small-sized mobile phones to medium and large-sized NBs, tablets, car-mounted products and even IT products.

Touch technology is mainly divided into two types: out-cell and in-cell. For mobile phones, tablets and NB products, in-cell products are gradually replacing out-cell products due to cost, weight and thickness considerations.

At present, in-cell products are gradually moving towards medium and large sizes. As the panel size becomes larger, the TP Block (touch screen horizontal stripes) of in-cell products will become more serious under the flicker screen. Therefore, we propose a method to reduce TP RC loading to solve the problems mentioned in the above background technology.

Summary of the invention

The object of the present invention is to provide a TP reduction RC loading method to solve the problems raised in the above background technology.

To achieve the above object, the present invention provides the following technical solution: a method for reducing TP RC loading, comprising the following steps:

S1: A GE layer, i.e., a gate, is formed on a glass substrate. A GI layer, i.e., a first insulating layer, is formed on the basis of the GE layer. A SE layer, i.e., a semiconductor layer, is formed on the basis of the GI layer. An ES layer, i.e., a second insulating layer, is formed on the SE layer to protect the SE layer.

S2: Then, an SD layer is fabricated on the ES layer as the source and drain of the TFT switch, and the SD layer and the SE layer are connected by etching through holes in the ES layer to form a complete TFT structure. At the same time, another SD layer is fabricated on the ES layer as a TP wiring.

S3: A PV layer, i.e., the third insulating layer, is fabricated above the SD layer. An OC layer, i.e., the fourth insulating layer, is fabricated above the PV layer. The drain electrode is connected to the PIXEL ITO by etching through holes in the OC layer and the PV layer, so that the signal of the SD source electrode can be transmitted to the drain electrode and then to the PIXEL ITO through the SE layer when the gate voltage is high. A CH layer, i.e., the fifth insulating layer, is fabricated above the PIXEL ITO. A VCOM ITO layer is fabricated above the CH layer.

There is a coupling phenomenon between the TP wiring and the gate. An ITO layer is made on the GI layer so that the ITO layer is placed between the gate and the TP wiring to prevent the gate from being affected by the TP wiring, thereby eliminating the horizontal stripes on the touch screen caused by the coupling of the gate wiring with the TP wiring.

The thickness of the glass substrate is 0.3-0.5 mm.

In cell, touch panel, TP Block.

The present invention is suitable for unbound in-cell touch screen panels.

Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention provides a method for reducing TP RC loading. The present invention mainly adds a mask and an electrode film layer (i.e., ITO layer) between the GI layer and the ES layer to shield the Scan signal and the TP signal, so that the capacitive coupling effect of the Scan signal on the TP signal is greatly reduced, thereby achieving the purpose of optimizing the TP Block. Effectively reduce the capacitive coupling of the Scan signal to the TP signal. The ITO layer is placed between the Scan and TP as a shield, thereby reducing the capacitive coupling effect of the Scan on the TP, thereby achieving the purpose of optimizing the TP Block.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a pixel arrangement structure design in the prior art;

FIG2 is a schematic diagram of a conventional two-pixel arrangement structure design;

FIG3 is a schematic diagram of the TP capacitive coupling effect before and after improvement;

FIG4 is a schematic diagram of a pixel arrangement structure design of the present invention;

FIG5 is a schematic cross-sectional view of a pixel unit according to a prior art;

FIG. 6 is a schematic cross-sectional view of a pixel unit according to the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the known technology, taking the TOP COM 9PEP architecture as an example, the TP Lines are all overlapped with the Data Lines (as shown in Figure 1), but due to the increase in size and resolution, the coupling effect of Data on TP capacitance is bound to increase, so the TP Line will not overlap with the Data Line (as shown in Figure 2) as a design, and because the TP Line and the Data Line do not overlap, the TP Line can use the same film layer metal2 as the Data Line to increase the distance between the TP Line and the COM layer, thereby reducing the capacitance between the TP Line and the COM layer (the original overlapping TP Line needs to use metal3, which is close to the COM layer), but the overlap between the TP Line and the Scan Line still exists. Therefore, the TP Block mainly comes from the coupling effect of the TP routing on the Scan signal (as shown in Figure 3). The larger the size and the higher the resolution, the more serious the TP Block problem will be. This patent uses a new design to optimize the TP Block problem.

The present invention provides a method for reducing TP RC loading as shown in FIG3 , FIG4 and FIG6 , comprising the following steps:

S1: A GE layer, i.e., a gate, is formed on a glass substrate. A GI layer, i.e., a first insulating layer, is formed on the basis of the GE layer. A SE layer, i.e., a semiconductor layer, is formed on the basis of the GI layer. An ES layer, i.e., a second insulating layer, is formed on the SE layer to protect the SE layer.

S2: Then, an SD layer is fabricated on the ES layer as the source and drain of the TFT switch, and the SD layer and the SE layer are connected by etching through holes in the ES layer to form a complete TFT structure. At the same time, another SD layer is fabricated on the ES layer as a TP wiring.

S3: A PV layer, i.e., the third insulating layer, is fabricated above the SD layer. An OC layer, i.e., the fourth insulating layer, is fabricated above the PV layer. The drain electrode is connected to the PIXEL ITO by etching through holes in the OC layer and the PV layer, so that the signal of the SD source electrode can be transmitted to the drain electrode and then to the PIXEL ITO through the SE layer when the gate voltage is high. A CH layer, i.e., the fifth insulating layer, is fabricated above the PIXEL ITO. A VCOM ITO layer is fabricated above the CH layer.

There is a coupling phenomenon between the TP wiring and the gate. An ITO layer is made on the GI layer so that the ITO layer is placed between the gate and the TP wiring to prevent the gate from being affected by the TP wiring, thereby eliminating the horizontal stripes on the touch screen caused by the coupling of the gate wiring with the TP wiring.

The thickness of the glass substrate is 0.3-0.5 mm.

In summary, compared with the known technology, there is no shielding pattern between TP and Scan. In order to reduce the capacitive coupling of Scan to TP, the present invention uses an electrode film layer (the present invention takes Pixel signal as an example) between TP and Scan line for shielding (as shown in Figure 4). From the cross-sectional view, it can be understood that the known technology Gate does not have any signal between TP as a shield (as shown in Figure 5). The present invention technology adds a mask process to make an electrode film layer ITO placed between Scan and TP as a shield (as shown in Figure 6), thereby reducing the capacitive coupling effect of Scan on TP, thereby achieving the purpose of TP Block optimization.

Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (2)

1. A method for reducing TP RC loading, i.e., a method for reducing the resistance and capacitance load of a touch screen, characterized in that it comprises the following steps: S1: A GE layer, i.e., a gate, is formed on a glass substrate. A GI layer, i.e., a first insulating layer, is formed on the basis of the GE layer. A SE layer, i.e., a semiconductor layer, is formed on the basis of the GI layer. An ES layer, i.e., a second insulating layer, is formed on the SE layer to protect the SE layer. S2: Then, an SD layer is fabricated on the ES layer as the source and drain of the TFT switch, and the SD layer and the SE layer are connected by etching through holes in the ES layer to form a complete TFT structure. At the same time, another SD layer is fabricated on the ES layer as a TP wiring. S3: a PV layer, i.e., the third insulating layer, is formed on the SD layer; an OC layer, i.e., the fourth insulating layer, is formed on the PV layer; the drain electrode is connected to the pixel electrode by etching through holes in the OC layer and the PV layer; a CH layer, i.e., the fifth insulating layer, is formed on the pixel electrode; and a common electrode through hole is formed on the CH layer; The coupling phenomenon between the TP wiring and the gate is solved by making an ITO layer on the GI layer so that the ITO layer is placed between the gate and the TP wiring to prevent the gate from being affected by the TP wiring, thereby eliminating the horizontal stripes on the touch screen caused by the coupling of the gate wiring with the TP wiring. The drain is connected to the pixel electrode, so that the signal of the SD source can be transmitted to the drain through the SE layer and then to the pixel electrode when the gate voltage is high. 2. A TP RC loading reduction method according to claim 1, characterized in that the thickness of the glass substrate is 0.3-0.5 mm.