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CN113903393A - A method to improve the reliability of NOR FLASH - Google Patents

A method to improve the reliability of NOR FLASH Download PDF

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Publication number
CN113903393A
CN113903393A CN202110953010.7A CN202110953010A CN113903393A CN 113903393 A CN113903393 A CN 113903393A CN 202110953010 A CN202110953010 A CN 202110953010A CN 113903393 A CN113903393 A CN 113903393A
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page
address mapping
update
information
physical area
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李建波
王延斌
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Beijing CEC Huada Electronic Design Co Ltd
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Beijing CEC Huada Electronic Design Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

本发明提供一种提升NOR FLASH可靠性的方法，应用于芯片安全存储领域。该方法包括5个阶段：阶段1，更新擦除次数统计页；阶段2，更新ECC错误统计页；阶段3，更新地址映射信息页；阶段4，初始化地址映射表；阶段5，逻辑地址访问物理区。针对NOR FLASH可靠性问题，引入物理状态统计区包含擦除次数统计页和ECC错误统计页，擦除次数影响可靠性，而ECC错误表示发生失效，通过以上信息可以有效地评价NOR FLASH可靠性水平。同时加入冗余物理区，通过地址映射表替换失效的原始物理区。本发明提出的方法不仅可以评价NOR FLASH可靠性水平，同时提升NOR FLASH可靠性。

Figure 202110953010

The invention provides a method for improving the reliability of NOR FLASH, which is applied to the field of chip security storage. The method includes 5 stages: stage 1, update the erasure count statistics page; stage 2, update the ECC error statistics page; stage 3, update the address mapping information page; stage 4, initialize the address mapping table; stage 5, logical address access physical Area. Aiming at the reliability problem of NOR FLASH, the physical state statistics area is introduced to include the number of erasure statistics page and the page of ECC error statistics. The number of erasures affects reliability, and the ECC error indicates failure. The above information can effectively evaluate the reliability level of NOR FLASH. . At the same time, a redundant physical area is added, and the failed original physical area is replaced by the address mapping table. The method proposed by the present invention can not only evaluate the reliability level of NOR FLASH, but also improve the reliability of NOR FLASH.

Figure 202110953010

Description

Method for improving NOR FLASH reliability
Technical Field
The invention relates to the technical field of chip secure storage, in particular to a method for improving NOR FLASH reliability.
Background
With the continuous development of the integrated circuit industry in China, the application field of NOR FLASH is more and more extensive, and higher challenges are provided for the reliability of NORFLASH. In the use process of the traditional NOR FLASH chip, the reliability problem is caused by some reasons (such as chip aging, environmental temperature and humidity change, erasing times exceeding the upper limit and the like), so that the chip works abnormally.
When failure analysis is carried out on a NOR FLASH chip with reliability problems, only failed units can be identified, but the reasons for the results cannot be analyzed, and the chip cannot be recovered to work normally. Therefore, there is a need for a suitable method to preserve the state affecting the reliability of NOR FLASH for evaluating the reliability level, while a method to replace failed cells to restore the chip to normal operation is needed.
Disclosure of Invention
The invention provides a method for improving the reliability of NOR FLASH, which is used for evaluating the reliability level of the NOR FLASH and improving the reliability of the NOR FLASH at the same time.
The invention provides a method for improving NOR FLASH reliability, which is characterized in that the method specifically comprises a physical area, a physical state statistical area, an address mapping area and an address mapping table, and the method comprises the following 5 stages:
stage 1, updating an erasing frequency statistical page;
stage 2, updating an ECC error statistic page;
stage 3, updating the address mapping information page;
step 4, initializing an address mapping table;
stage 5, the logical address accesses the physical area;
in the stage 1, updating the erasing times counting Page is that after the current Page in the physical area is erased, the hardware reads the information of the erasing times counting Page corresponding to the current Page, and then updates the information of the erasing times counting Page corresponding to the current Page, wherein the specific updating is writing operation, the specific reading information is the erased times of the current Page, and the specific updating information is the erased times of the current Page plus one.
And the step 2 of updating the ECC error counting Page is that after the current Page of the physical area has an ECC error, the information of the ECC error counting Page corresponding to the current Page is read, and then the information of the ECC error counting Page corresponding to the current Page is updated, wherein the specific updating is writing operation, the specific reading information is the number of times of the current Page having the ECC error, and the specific updating information is the number of times of the current Page having the ECC error plus one.
And 3, updating the address mapping information page in a stage of reading the information of the physical state statistical area, judging whether the erasing times is larger than the maximum value, if so, updating the address mapping information page, otherwise, judging whether ECC errors occur, if so, updating the address mapping information page, otherwise, carrying out no operation, specifically updating the address mapping information page to be write operation, wherein the specific maximum value is the intrinsic life of NOR FLASH, the content of the specific address mapping information page is 1 or 0, and the specific address mapping information page is defaulted to be 1, and the specific no operation means that the write operation is not carried out.
And the step 4 of initializing the address mapping table is to read the address mapping information page and update the address mapping table after the chip is powered on, and specifically, the address mapping table is initialized to latch the content of the read address mapping information page into a register, and the address mapping table selects a redundant physical area or an original physical area according to the value of the register.
And in the stage 5, when the logical address accesses the physical area, the logical address is firstly latched and then converted into the physical address, whether the redundant physical area is started or not is judged according to the address mapping table, if so, the redundant physical area is started, otherwise, the original physical area is kept unchanged, the specific conversion into the physical address belongs to the memory space management, the physical address is already fixed during chip design, and after the specific initialization address mapping table is completed, the physical address corresponds to the redundant physical area or the original physical area and is a fixed value.
Drawings
FIG. 1 is a system diagram of a method for improving NOR FLASH reliability;
FIG. 2 is a flowchart of an update erase count page;
FIG. 3 is a flowchart of updating an ECC error statistics page;
FIG. 4 is a flowchart of updating an address mapping information page;
FIG. 5 is a flow chart of initializing an address mapping table;
FIG. 6 is a flow chart of logical address access to a physical area;
Detailed Description
The method for improving the reliability of the NOR FLASH comprises 3 parts, as shown in figure 1, the part 1 is that the current Page erasing times and ECC error state information of a NOR FLASH physical area (108) are acquired and stored to an erasing times counting Page (1011) and an ECC error counting Page (1012) corresponding to a physical state counting area (101), and the information is used for evaluating the reliability level of the current Page; the 2 nd part is that a user program (103) obtains the current Page erasing times and ECC error state information through a physical state statistical module (102), and updates an address mapping information Page (1051) of an address mapping area (105) through an address mapping management module (104), and the part is a key decision link and decides whether to replace an original physical area or not according to the reliability level of the current Page; part 3 is the replacement of the redundant physical area with the original physical area by initializing the address mapping table (107) by reading the contents of the address mapping information page (1051). The implementation will be described in detail from 5 stages below.
The phase 1 update erase count statistics page is shown in fig. 2, specifically:
in step 201, the current Page erase of the physical area is completed.
Step 202, reading the statistical Page information of the corresponding erasing times of the current Page.
And step 203, updating the statistical Page information of the corresponding erasing times of the current Page.
The step 201 that the current Page erase of the physical area is completed means that the user executes a Page erase instruction, and the chip completes the Page erase operation.
Reading the statistics Page information of the erasing times corresponding to the current Page in step 202 means that the chip automatically reads the statistics Page information of the erasing times corresponding to the current Page, the specific erasing times statistics Page is a fixed Page of a physical area corresponding to a fixed address in the Page, and the specific reading information is the erased times of the current Page.
The step 203 of updating the information of the statistical Page of the erasing times corresponding to the current Page means that a write operation is performed on the statistical Page of the erasing times corresponding to the current Page, and the specific content of the write operation is that the erased times of the current Page read in the step 202 are increased by one.
Phase 2 update ECC error statistics page as shown in fig. 3, specifically:
in step 301, the current Page of the physical area is ECC-error.
Step 302, reading the ECC error statistical Page information corresponding to the current Page.
Step 303, updating the ECC error statistical Page information corresponding to the current Page.
The current Page ECC error of the physical area in step 301 refers to an ECC error occurring when a user reads the content of the current Page.
Step 302, reading the ECC error statistics Page information corresponding to the current Page means that the chip automatically reads the ECC error statistics Page information corresponding to the current Page, and the specific read information is the number of times of ECC errors occurring in the current Page, where the specific fixed address in the ECC error statistics Page corresponds to the fixed Page in the physical area.
Updating the information of the ECC error statistic Page corresponding to the current Page in step 303 means performing a write operation on the ECC error statistic Page corresponding to the current Page, where the specific content of the write operation is to add one to the number of ECC errors occurring when the current Page is read in step 302.
Stage 3 updating address mapping information page as shown in fig. 4, specifically:
step 401, reading the physical status statistics area information, where the information includes the number of times of erasure and the number of times of ECC errors.
Step 402, judging whether the erasing times is larger than the maximum value, if so, executing step 403, otherwise, executing step 404, wherein the specific maximum value is the intrinsic life of the NOR FLASH.
Step 403, updating the address mapping information page, where the specific update is a write operation, and the content of the write operation is 0. The specific content of the address mapping information page is 1 or 0, and defaults to 1.
Step 404, determining whether the number of ECC errors is greater than 1, if so, executing step 403, otherwise, executing step 405.
Step 405, no operation, i.e. no write operation, ends this phase.
Stage 4 initializing address mapping table as shown in fig. 5, specifically:
step 501, the chip power-on completion means that the chip completes simulation trimming, chip configuration and safety monitoring, and can execute a user program.
In step 502, reading the address mapping information page refers to latching the content of the read address mapping information page into a register.
In step 503, updating the address mapping table means selecting a redundant physical area or an original physical area according to the register value latched in step 502, where the latched register value corresponds to the original physical area if it is 1, and corresponds to the redundant physical area if it is 0.
Stage 5 logical address access physical area as shown in fig. 6, specifically:
in step 601, latching the logical address refers to latching the address accessed by the user into the register.
The translation to a physical address, step 602, refers to translating a logical address to a physical address according to a memory space management scheme.
Step 603, judging whether to start a redundant physical area, if so, executing step 604, otherwise, executing step 605, wherein the specific judgment is based on the content of the address mapping table of the stage 4, if so, selecting the original physical area, if so, selecting the redundant physical area, and after the specific stage 4 is completed, the content of the address mapping table is a fixed value, namely the redundant physical area or the original physical area corresponding to the current Page is a fixed value.
In step 604, the redundant physical area refers to that the corresponding content of the current Page of the address mapping table is 0, and the redundant physical area is selected.
Step 605, selecting the original physical area, where the content of the address mapping table corresponding to the current Page is 1.

Claims (6)

1.一种提升NOR FLASH可靠性的方法,其特征在于，所述方法具体包括物理区、物理状态统计区、地址映射区、地址映射表，实现所述方法包括以下5个步骤：1. a method for improving NOR FLASH reliability, is characterized in that, described method specifically comprises physical district, physical state statistics district, address mapping district, address mapping table, realizes described method comprises following 5 steps: 步骤1，更新擦除次数统计页；Step 1, update the erasure count statistics page; 步骤2，更新ECC错误统计页；Step 2, update the ECC error statistics page; 步骤3，更新地址映射信息页；Step 3, update the address mapping information page; 步骤4，初始化地址映射表；Step 4, initialize the address mapping table; 步骤5，逻辑地址访问物理区。Step 5, the logical address accesses the physical area. 2.如权利要求1所述的方法，其特征在于，所述的更新擦除次数统计页是在物理区当前Page擦除完成后，读取当前Page对应擦除次数统计页信息，再更新当前Page对应擦除次数统计页信息。2. method as claimed in claim 1, is characterized in that, described update erasing times statistical page is after the current Page erasure of physical area is completed, read current Page corresponding erasing times statistical page information, then update current page Page corresponds to the erasure count statistics page information. 3.如权利要求1所述的方法，其特征在于，所述的更新ECC错误统计页是在物理区当前Page ECC错误后，读取当前Page对应ECC错误统计页信息，再更新当前Page对应ECC错误统计页信息。3. The method of claim 1, wherein the updating of the ECC error statistics page is to read the ECC error statistics page information corresponding to the current Page after the current Page ECC error in the physical area, and then update the current Page corresponding to the ECC Error statistics page information. 4.如权利要求1所述的方法，其特征在于，所述的更新地址映射信息页是读取物理状态统计区信息，再判断擦除次数是否大于最大值，如果是则更新地址映射信息页，否则判断是否发生ECC错误，如果是则更新地址映射信息页，否则无操作。4. method as claimed in claim 1 is characterized in that, described update address mapping information page is to read physical state statistics area information, then judge whether erasure times is greater than maximum value, if so then update address mapping information page , otherwise judge whether an ECC error occurs, if so, update the address mapping information page, otherwise no operation. 5.如权利要求1所述的方法，其特征在于，所述的初始化地址映射表是在芯片上电完成后，读取地址映射信息页，再更新地址映射表。5. The method of claim 1, wherein the initializing the address mapping table is to read the address mapping information page after the chip is powered on, and then update the address mapping table. 6.如权利要求1所述的方法，其特征在于，所述的逻辑地址访问物理区首先锁存逻辑地址，再转换为物理地址，根据地址映射表，判断是否启动冗余物理区，如果是则启动冗余物理区，否则保持原始物理区不变。6. method as claimed in claim 1 is characterized in that, described logical address accesses physical area at first latching logical address, is converted into physical address again, according to address mapping table, judges whether to start redundant physical area, if it is Then start the redundant physical area, otherwise keep the original physical area unchanged.
CN202110953010.7A 2021-08-19 2021-08-19 A method to improve the reliability of NOR FLASH Pending CN113903393A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1701308A (en) * 2002-10-28 2005-11-23 桑迪士克股份有限公司 Maintaining erase counts in non-volatile storage systems
KR20090131086A (en) * 2008-06-17 2009-12-28 삼성전자주식회사 Memory system performing asymmetric mapping operation and address mapping method thereof
CN102298543A (en) * 2011-09-15 2011-12-28 成都市华为赛门铁克科技有限公司 Memory management method and memory management device
CN102622306A (en) * 2012-02-21 2012-08-01 中颖电子股份有限公司 Bad block management method for storage device
CN105786722A (en) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 NVM erasing and writing control method and system based on heterogeneous hybrid memory
CN109165115A (en) * 2018-06-26 2019-01-08 北京中电华大电子设计有限责任公司 A method of enhancing FLASH memory reliability

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1701308A (en) * 2002-10-28 2005-11-23 桑迪士克股份有限公司 Maintaining erase counts in non-volatile storage systems
KR20090131086A (en) * 2008-06-17 2009-12-28 삼성전자주식회사 Memory system performing asymmetric mapping operation and address mapping method thereof
CN102298543A (en) * 2011-09-15 2011-12-28 成都市华为赛门铁克科技有限公司 Memory management method and memory management device
CN102622306A (en) * 2012-02-21 2012-08-01 中颖电子股份有限公司 Bad block management method for storage device
CN105786722A (en) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 NVM erasing and writing control method and system based on heterogeneous hybrid memory
CN109165115A (en) * 2018-06-26 2019-01-08 北京中电华大电子设计有限责任公司 A method of enhancing FLASH memory reliability

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