CN113900006B - Chip fault testing device, system and method - Google Patents
Chip fault testing device, system and method Download PDFInfo
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- CN113900006B CN113900006B CN202110990088.6A CN202110990088A CN113900006B CN 113900006 B CN113900006 B CN 113900006B CN 202110990088 A CN202110990088 A CN 202110990088A CN 113900006 B CN113900006 B CN 113900006B
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- 238000012360 testing method Methods 0.000 title claims abstract description 152
- 238000000034 method Methods 0.000 title abstract description 7
- 238000005070 sampling Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000008054 signal transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000004088 simulation Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
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Abstract
The invention discloses a chip fault testing device, a system and a method, wherein the device comprises a testing board card, an ADC chip testing seat for installing a tested ADC chip and a DAC chip testing seat for installing the tested DAC chip are arranged on the testing board card, and a signal input port and a signal output port are also arranged, and the signal input port is connected with the tested ADC chip and the tested DAC chip and the signal output port in sequence to form a testing channel. The invention can simplify the test flow and rapidly verify whether the tested ADC chip and the tested DAC chip have faults or not without the participation of the FPGA in fault test.
Description
Technical Field
The present invention relates to the field of chip fault testing, and in particular, to a chip fault testing device, system and method.
Background
For the chip materials of the ADC (analog-to-digital converter) and the DAC (digital-to-analog converter), the degree of quality of the chip cannot be judged by simply observing the appearance, the quality and performance index of the chip can be judged only after the design of the board is finished, so that the dislocation delay between the purchasing period and the verification period of the chip is caused, the time spent in the process from the design of the board to the verification of the welding test of the board can exceed the quality guarantee period of the commodity, and the project scheduling is greatly delayed, so that the test equipment corresponding to the design of the chip is necessary.
As shown in fig. 1, a conventional ADC chip test apparatus includes a test board and an FPGA, the test board being provided with an analog input port, a digital output port, a clock port, and a configuration port. After the ADC chip is configured, the standard signal source is driven by the on-board clock to generate a single carrier wave converted digital signal, the single carrier wave converted digital signal is output to the FPGA, the FPGA latches and grabs data, and the data is subjected to FFT spectrum analysis to check whether the performance index of the ADC chip accords with the expectation.
As shown in fig. 2, a conventional DAC chip test apparatus includes a test board provided with an analog output port, a digital input port, a clock port, and a configuration port, and an FPGA. After the DAC chip completes configuration, under the drive of a homologous clock, the DDS (signal generator) generates a standard digital signal, the standard digital signal is transmitted to the DAC chip through the FPGA to latch data, the data is converted into an analog signal after analog-to-digital conversion, and the analog signal is output to the frequency spectrograph, so that whether the related performance indexes of SNR and SFDR meet expectations is checked.
Therefore, the existing ADC chip test equipment and DAC chip test equipment both need the participation of the FPGA, take a great deal of time to modify and compile the hardware language special for the FPGA, and have low test efficiency.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems existing in the prior art, the invention provides a chip fault testing device, a chip fault testing system and a chip fault testing method, which can simplify the testing process and rapidly verify whether the tested ADC chip and the tested DAC chip have faults or not without participation of an FPGA in fault testing.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
The chip fault testing device comprises a testing board card, wherein an ADC chip testing seat for installing an ADC chip to be tested and a DAC chip testing seat for installing a DAC chip to be tested are arranged on the testing board card, and a signal input port and a signal output port are also arranged on the testing board card, and the signal input port is connected with the DAC chip to be tested and the signal output port sequentially through the ADC chip to be tested and the DAC chip to be tested to form a testing channel.
Further, be equipped with first connector, second connector and be used for the cable that links to each other first connector and second connector on the test board card, the ADC chip of being tested loops through first connector and second connector and is connected by the DAC chip of being tested, first connector output side is equipped with first terminal, second connector input side is equipped with the second terminal, the pin one-to-one of first terminal and the ADC chip output of being tested, the pin one-to-one of second terminal and the DAC chip input of being tested, and first terminal, second terminal and cable one-to-one respectively, and every first terminal passes through the cable and can dismantle with the second terminal of correspondence and be connected.
Further, the first terminal and the second terminal are jacks respectively, plugs are arranged at two ends of the cable respectively, and the plugs are inserted into the corresponding jacks.
Further, the cable is an equal-length cable.
Furthermore, the test board is also provided with a clock port, and the clock port is connected with the clock end of the tested ADC chip and the clock end of the tested DAC chip.
Furthermore, the test board is also provided with a configuration port, and the configuration port is connected with the configuration end of the tested ADC chip and the configuration end of the tested DAC chip through an SPI or I2C bus.
Further, the device also comprises a frequency spectrograph, wherein the input end of the frequency spectrograph is connected with the signal output port.
Further, the device also comprises a logic analyzer, wherein the input end of the logic analyzer is connected with the output end of the tested ADC chip.
The invention also provides a chip fault test system, which comprises an upper computer and a chip fault test device, wherein the chip fault test device is any one of the chip fault test devices, and the upper computer is connected with the configuration ends of the tested ADC chip and the tested DAC chip.
The invention also provides a chip fault test method which is applied to any one of the chip fault test devices and is characterized by comprising the following steps:
S1) installing a tested ADC chip on an ADC chip test seat, and installing the tested DAC chip on the DAC chip test seat;
S2) according to the pin definition of the output end of the tested ADC chip and the pin definition of the input end of the tested DAC chip, respectively configuring a first terminal corresponding to the output side of the first connector and a second terminal corresponding to the input side of the second connector, and connecting the corresponding first terminal and the corresponding second terminal through a cable;
s3) inputting the corresponding clock signals into the clock port according to the tested ADC chip and the sampling rate and the playback rate supported by the tested DAC chip;
s4) connecting the upper computer with a configuration port, and configuring the tested ADC chip, the sampling rate and the working mode of the tested DAC chip;
S5) an external signal source inputs a standard test signal to the signal input port, the output signal of the signal output port is checked through a spectrometer, if the waveform of the output signal meets the requirement and the performance indexes of the tested ADC chip and the tested DAC chip meet the expectations, the tested ADC chip and the tested DAC chip have no faults, the test is ended and the test is exited, otherwise, the step S6) is executed;
S6) disconnecting the cable from the second terminal, connecting the cable with a logic analyzer, configuring the output increment number or the fixed number of the tested ADC chip through the upper computer, judging whether the connectivity problem or the time sequence problem exists through the logic analyzer, if so, testing the ADC chip, and otherwise, testing the DAC chip.
Compared with the prior art, the invention has the advantages that:
1. In the chip fault testing device, the signal input port, the tested ADC chip, the tested DAC chip and the signal output port are sequentially connected to form the test channel on the test board for loop test, and as the ADC and the DAC are devices with two functions being equal to each other, whether the difference between the input signal and the output signal of the test board meets the requirement or not can be determined, whether faults exist in each pair of the tested ADC chip and the tested DAC chip or not can be determined, each pair of the ADC chip and the DAC chip with faults can be removed in time, meanwhile, the FPGA is not required to participate in fault test, on one hand, the equipment cost is reduced, and on the other hand, the time for compiling FPGA hardware language is saved.
2. In the chip fault testing device, the ADC chip testing seat and the DAC chip testing seat are arranged on the testing board card, so that fault verification can be rapidly carried out on each pair of tested ADC chips and tested DAC chips under the condition of no welding.
3. In the chip fault testing device, the first connector and the second connector are arranged on the testing board card, the first terminal at the output side of the first connector, the pin at the output end of the tested ADC chip, the pin at the input end of the tested DAC chip and the second terminal at the input side of the second connector are in one-to-one correspondence respectively, and each first terminal is detachably connected with the corresponding second terminal through the cable, so that the corresponding first terminal and the corresponding second terminal can be timely adjusted and reconnected under the condition that the definition of the pin is changed for the tested ADC chip and the tested DAC chip, and the applicability of fault testing for the ADC chips with different models is improved.
Drawings
Fig. 1 is a schematic diagram of the connection relationship and operation of the conventional ADC chip test apparatus.
Fig. 2 is a schematic diagram of the connection relationship and operation of the conventional DAC chip test apparatus.
Fig. 3 is a connection relationship and an operation schematic diagram of a chip failure test system according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of operation when determining a specific fault object in an embodiment of the present invention.
Detailed Description
The invention is further described below in connection with the drawings and the specific preferred embodiments, but the scope of protection of the invention is not limited thereby.
For a typical ADC chip, it includes an input terminal for receiving an analog signal, an output terminal for outputting a digital signal, and further includes a power supply terminal, a ground terminal, a clock terminal, and a configuration terminal; correspondingly, for a typical DAC chip, the device comprises an input terminal for receiving a digital signal, an output terminal for outputting an analog signal, and a power supply terminal, a ground terminal, a clock terminal and a configuration terminal, so that in theory, the ADC chip and the DAC chip are two devices with equivalent functions, the analog signal sequentially passes through the ADC chip and the DAC chip without faults, and the output signal should still be an analog signal, so that loop test can be performed for one test group comprising the ADC chip and the DAC chip without participation of the FPGA to determine whether each test group has faults. The ADC chip is selected as the first stage to conveniently adjust the external signal source to modify the parameters of the signal to be tested, thereby facilitating the automatic test
Based on the above-mentioned thought, as shown in fig. 3, the invention provides a chip fault testing device, which comprises a testing board card, wherein the testing board card is provided with an ADC chip testing seat for installing an ADC chip to be tested and a DAC chip testing seat for installing the DAC chip to be tested, and is also provided with a signal input port and a signal output port, and the signal input port is connected with the ADC chip to be tested and the DAC chip to be tested and the signal output port in sequence to form a testing channel. Through the structure, the tested ADC chip and the tested DAC chip are connected for loop-back testing, if the analog signals output by the signal output port meet the requirements, the tested ADC chip and the tested DAC chip have no faults, otherwise, at least one of the tested ADC chip and the tested DAC chip has faults, so that the rapid screening of the fault-free test groups in the tested ADC chip and the tested DAC chip can be realized, and meanwhile, the FPGA is not required to participate in fault testing, and the time is not required to be spent for modifying and compiling the hardware language special for the FPGA.
In this embodiment, the quick detach chip test seat is adopted respectively to ADC chip test seat and DAC chip test seat, quick detach chip test seat includes base and clamp plate, the base is equipped with the contact with the pin one-to-one of chip, the base back lid top board of corresponding quick detach chip test seat is put into to the ADC chip that is tested and the DAC chip that is tested, make chip pin and corresponding contact through the downforce of clamp plate, can power on and test, open the clamp plate after the test is finished just can take out the ADC chip that is tested and the DAC chip that is tested, thereby just can carry out quick test under the condition that need not the welding.
In this embodiment, the number of pins at the output end of the tested ADC chip is the same as the number of pins at the input end of the tested DAC chip, the most common middle-high speed ADC data interface is LVDS level, and the number of bits is not more than 16 bits, so the number of pins at the output end of the tested ADC chip and the number of pins at the input end of the tested DAC chip in this embodiment are both 16+1.
In practical situations, the definition of the pins may be different for different types of ADC chips, for example, the pin No. 5 in the current type is GND, but the pin No. 5 in the other type is TX, which may be the case for different types of DAC chips. In order to improve the applicability of the chip fault test device of the embodiment, as shown in fig. 3, in the embodiment, a first connector, a second connector and a cable for connecting the first connector with the second connector are arranged on the test board card, in the ADC chip test seat, the contacts corresponding to the pins of the output end of the ADC chip to be tested are connected with the input side of the first connector, in the DAC chip test seat, the contacts corresponding to the pins of the input end of the DAC chip to be tested are connected with the output side of the second connector, so that the output end of the ADC chip to be tested is sequentially connected with the input end of the DAC chip to be tested through the first connector and the second connector, the output side of the first connector is provided with a first terminal, the input side of the second connector is provided with a second terminal, the first terminal is in one-to-one correspondence with the pins of the input end of the DAC chip to be tested, the first terminal, the second terminal is in one-to-one correspondence with the cable, and each first terminal is detachably connected with the second terminal through the cable.
Through the structure, as the first terminal at the output side of the first connector, the pin at the output end of the tested ADC chip, the pin at the input end of the tested DAC chip and the second terminal at the input side of the second connector are respectively in one-to-one correspondence, and the first terminals are detachably connected with the corresponding second terminals through the cables, when the definition of the pin at the output end of the tested ADC chip or the pin at the input end of the tested DAC chip is changed due to different models of the tested ADC chip or the tested DAC chip in the next group, the connection relation between each first terminal and the corresponding second terminal is only required to be adjusted, namely, the connection between all cables and the second terminals is disconnected, and the cable corresponding to the first terminal is connected with the corresponding second terminal according to the corresponding relation between the new first terminal and the second terminal, so that the data stream can be normally transmitted when the tested ADC chip and the tested DAC chip in the next group are tested.
In this embodiment, the first terminal and the second terminal are jacks respectively, two ends of the cable are respectively provided with a plug, and the plugs are inserted into the corresponding jacks. Thereby facilitating replacement of damaged cables. Meanwhile, in this embodiment, the cables are equal-length cables, that is, all cables have the same length, so that the signal transmission speeds from all the first terminals to the corresponding second terminals are kept consistent, and delay in the signal transmission process caused by different cable lengths can be avoided.
In this embodiment, as shown in fig. 3, the test board card is further provided with a clock port, where the clock port is connected to a contact corresponding to a pin of a clock end of the tested ADC chip in the ADC chip test seat, and is further connected to a contact corresponding to a pin of a clock end of the tested DAC chip in the DAC chip test seat, so that the clock end of the tested ADC chip and the clock end of the tested DAC chip receive clock signals of an external clock source through the clock port.
In this embodiment, as shown in fig. 3, a configuration port is further provided on the test board, where the configuration port is connected to a contact corresponding to a pin of a configuration end of a tested ADC chip in the ADC chip test seat through an SPI or I2C bus, and is further connected to a contact corresponding to a pin of a configuration end of a tested DAC chip in the DAC chip test seat, so that the configuration end of the tested ADC chip and the configuration end of the tested DAC chip receive an external configuration command through the configuration port to perform configuration.
In this embodiment, the test board card is further provided with a power supply port, and the power supply port is connected with a contact corresponding to a pin of a power supply end of the tested ADC chip in the ADC chip test seat and is also connected with a contact corresponding to a pin of a power supply end of the tested DAC chip in the DAC chip test seat, so that the power supply end of the tested ADC chip and the power supply end of the tested DAC chip are connected with an external power supply through the power supply port.
In this embodiment, the test board card is further provided with a ground port, and the ground port is connected with a contact corresponding to a ground pin of the tested ADC chip in the ADC chip test seat, and is also connected with a contact corresponding to a ground pin of the tested DAC chip in the DAC chip test seat, so that the ground end of the tested ADC chip and the ground end of the tested DAC chip are grounded through the ground port.
As shown in fig. 3, the chip fault testing device of the present embodiment further includes a spectrometer, where an input end of the spectrometer is connected to the signal output port. The analog signals output by the signal output port can be checked through the frequency spectrograph, the analog signals output by the signal output port are compared with the frequency of the analog signals input by the signal input port, whether the loop test of the tested ADC chip and the tested DAC chip is normal or not can be judged, the waveform of the analog signals output by the signal output port can be checked through the frequency spectrograph, and whether the performance indexes of the tested ADC chip and the tested DAC chip accord with expectations or not can be judged according to the SNR and the SFDR indexes.
For the tested ADC chip and the tested DAC chip in the test group in which the fault is detected, in order to determine the specific fault chip, as shown in fig. 4, the chip fault test device of this embodiment further includes a logic analyzer, and an input terminal of the logic analyzer is connected to an output terminal of the tested ADC chip through a first connector. The digital signal output by the tested ADC chip is checked through a logic analyzer, if the digital signal meets the expectations, the tested DAC chip can be determined to have faults, and if the digital signal does not meet the expectations, the tested ADC chip has faults.
As shown in fig. 3, the present invention further provides a chip fault test system, which includes an upper computer and a chip fault test device, where the chip fault test device is the chip fault test device described above, and the upper computer is connected to a configuration port of the chip fault test device, so that the configuration ends of the tested ADC chip and the tested DAC chip receive a configuration command from the upper computer through the configuration port to perform configuration.
The invention also provides a chip fault testing method which is applied to the chip fault testing device and comprises the following steps:
S1) installing a tested ADC chip on an ADC chip test seat, and installing the tested DAC chip on the DAC chip test seat;
S2) according to the pin definition of the output end of the tested ADC chip and the pin definition of the input end of the tested DAC chip, respectively configuring a first terminal corresponding to the output side of the first connector and a second terminal corresponding to the input side of the second connector, and connecting the corresponding first terminal and the corresponding second terminal through a cable;
s3) inputting the corresponding clock signals into the clock port according to the tested ADC chip and the sampling rate and the playback rate supported by the tested DAC chip;
s4) connecting the upper computer with a configuration port, and configuring the tested ADC chip, the sampling rate and the working mode of the tested DAC chip;
S5) after the configuration of the tested ADC chip and the tested DAC chip is finished, checking registers of the tested ADC chip and the tested DAC chip through an upper computer, if a clock link and a data link work normally, controlling an external signal source to input standard test signals to a signal input port, checking output signals of a signal output port through a spectrometer, if the waveforms of the output signals meet the requirements and the performance indexes of the tested ADC chip and the tested DAC chip meet expectations, the tested ADC chip and the tested DAC chip have no faults, ending and exiting, otherwise, executing the step S6);
In this step, the output signal waveform meeting the requirements specifically includes: if the output signal of the signal output port and the standard test signal are the same-frequency signals, the requirements are met, otherwise, the requirements are not met;
the performance indexes of the tested ADC chip and the tested DAC chip meet the expected specific requirements: judging whether the performance index accords with the expected or not according to the SNR and SFDR indexes; the expected values of the SNR and SFDR indexes are obtained by simulation and prediction according to the actual conditions of the device manual and the layout board, and whether the performance indexes accord with the expected or not can be determined by comparing the SNR and SFDR indexes of the tested ADC chip and the tested DAC chip with the expected values;
S6) disconnecting the cable from the second terminal, connecting the cable with an oscilloscope or a logic analyzer, configuring the tested ADC chip by an upper computer to output an increment number or a fixed number, judging whether the tested ADC chip has a connectivity problem or a time sequence problem by the oscilloscope or the logic analyzer, judging whether the connectivity and the time sequence problem are actually measured by the oscilloscope or the logic analyzer, judging whether the connection and the time sequence problem are met according to the establishment holding time in a device manual, namely reading the connection establishment holding time by the oscilloscope or the logic analyzer, comparing the connection establishment holding time with the establishment holding time recorded in the device manual, if the difference value is within a threshold value range, the connectivity problem or the time sequence problem does not exist in the tested ADC chip, and if the tested ADC chip has the connectivity problem or the time sequence problem, the tested ADC chip is in fault, otherwise, the tested DAC chip is in fault.
In this step, the outputting the signal waveform that does not meet the requirement further includes: the output signal spectrum displayed by the spectrometer has obvious stray or waveform jitter, which may be that the configuration parameter has a problem at the moment, after the connectivity problem or the time sequence problem is determined, the cable can be connected with the corresponding second terminal, and after the configuration information is modified and the tested ADC chip and the tested DAC chip are reconfigured by the upper computer, the step S5) is returned to restart the fault test.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. While the invention has been described with reference to preferred embodiments, it is not intended to be limiting. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention shall fall within the scope of the technical solution of the present invention.
Claims (9)
1. The chip fault testing device is characterized by comprising a testing board card, wherein the testing board card is provided with an ADC chip testing seat for installing an ADC chip to be tested and a DAC chip testing seat for installing the DAC chip to be tested, and is also provided with a signal input port and a signal output port, the signal input port is sequentially connected with the ADC chip to be tested and the DAC chip to be tested and the signal output port to form a testing channel, and the chip fault testing method of the chip fault testing device comprises the following steps:
S1) installing a tested ADC chip on an ADC chip test seat, and installing the tested DAC chip on the DAC chip test seat;
S2) according to the pin definition of the output end of the tested ADC chip and the pin definition of the input end of the tested DAC chip, respectively configuring a first terminal corresponding to the output side of the first connector and a second terminal corresponding to the input side of the second connector, and connecting the corresponding first terminal and the corresponding second terminal through a cable;
s3) inputting the corresponding clock signals into the clock port according to the tested ADC chip and the sampling rate and the playback rate supported by the tested DAC chip;
s4) connecting the upper computer with a configuration port, and configuring the tested ADC chip, the sampling rate and the working mode of the tested DAC chip;
S5) an external signal source inputs a standard test signal to the signal input port, the output signal of the signal output port is checked through a spectrometer, if the waveform of the output signal meets the requirement and the performance indexes of the tested ADC chip and the tested DAC chip meet the expectations, the tested ADC chip and the tested DAC chip have no faults, the test is ended and the test is exited, otherwise, the step S6) is executed;
S6) disconnecting the cable from the second terminal, connecting the cable with a logic analyzer, configuring the output increment number or the fixed number of the tested ADC chip through the upper computer, judging whether the connectivity problem or the time sequence problem exists through the logic analyzer, if so, testing the ADC chip, and otherwise, testing the DAC chip.
2. The chip fault testing device according to claim 1, wherein the test board card is provided with a first connector, a second connector and a cable for connecting the first connector with the second connector, the tested ADC chip is sequentially connected with the tested DAC chip through the first connector and the second connector, the output side of the first connector is provided with a first terminal, the input side of the second connector is provided with a second terminal, the first terminal is in one-to-one correspondence with the pins of the output end of the tested ADC chip, the second terminal is in one-to-one correspondence with the pins of the input end of the tested DAC chip, the first terminal, the second terminal and the cable are in one-to-one correspondence, respectively, and each first terminal is detachably connected with the corresponding second terminal through the cable.
3. The chip failure testing device according to claim 2, wherein the first terminal and the second terminal are jacks, plugs are respectively arranged at two ends of the cable, and the plugs are inserted into the corresponding jacks.
4. The chip failure testing device of claim 2, wherein the cable is an equal length cable.
5. The chip failure test device according to claim 1, wherein the test board card is further provided with a clock port connected to the clock terminal of the ADC chip under test and the clock terminal of the DAC chip under test.
6. The chip failure test device according to claim 1, wherein a configuration port is further provided on the test board card, and the configuration port is connected to the configuration terminal of the ADC chip under test and the configuration terminal of the DAC chip under test through an SPI or I2C bus.
7. The chip failure testing device of claim 1, further comprising a spectrometer, an input of the spectrometer being connected to the signal output port.
8. The chip failure testing device of claim 1, further comprising a logic analyzer, an input of the logic analyzer being connected to an output of the ADC chip under test.
9. The chip fault testing system is characterized by comprising an upper computer and a chip fault testing device, wherein the chip fault testing device is the chip fault testing device according to any one of claims 1-8, and the upper computer is connected with the configuration ends of the tested ADC chip and the tested DAC chip.
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| CN115128438A (en) * | 2022-09-02 | 2022-09-30 | 中诚华隆计算机技术有限公司 | Chip internal fault monitoring method and device |
| CN116346129A (en) * | 2023-02-15 | 2023-06-27 | 中国电子科技集团公司第二十九研究所 | A micro-module testing device and method based on standard interface definition |
| CN117632606A (en) * | 2023-11-24 | 2024-03-01 | 浙江正泰仪器仪表有限责任公司 | Chip detection method and chip detection device |
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