CN113904680B - Method to quickly relock DLL circuit - Google Patents

Abstract

The method for rapidly relocking the DLL circuit comprises the steps of detecting whether overflow or underflow exists in real time, correspondingly setting a control signal according to a detection result, and controlling delay of an internal clock. The method can greatly reduce the loss of instructions and data, can recover the normal phase locking state in time without resetting the DLL circuit, can provide the clock with minimum error for output data during overflow or underflow, has high data transmission accuracy and good stability, effectively solves the adverse effect of temperature change on clock processing, is beneficial to improving the reliability of DRAM operation, and further promotes the deep application of integrated circuit technology.

Description

Method for fast relocking DLL circuit

Technical Field

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a method for rapidly relocking a DLL circuit.

Background

The DRAM and the CPU of the external control chip accurately complete the transmission of instructions and data through clocks. In a read operation, the DRAM needs to provide an output clock dqs, dqs mainly for accurately distinguishing each transmission period within one clock period (tCK), and for accurately receiving data by a receiving side. When the output clock dqs and the external clock clk have large phase differences, the CPU can grasp erroneous instructions and data. The adjustment of the DRAM output clock dqs to phase align the output clock dqs with the external clock clk is currently mainly achieved by a delay locked loop DLL (Delay Locked Loop) circuit. The DLL circuit keeps the output clock dqs and the external clock clk phase aligned by providing an amount of delay.

Unstable voltage and temperature variations in the operation of a DRAM chip often cause the DLL circuit to fail, which is commonly referred to as a DLL circuit losing lock. There are two prominent out-of-lock conditions commonly referred to as overflow and underflow (underflow). The overflow is generally the instruction that the DLL circuit continues to issue to increase the delay, but the DLL circuit has provided the maximum amount of delay, cannot increase the amount of delay any more, the output clock dqs will remain in the current unlocked state, and no adjustments can be made. underflow is that the DLL circuit continues to issue instructions to reduce delay, but the DLL circuit has provided the least amount of delay it can adjust, cannot reduce the amount of delay any more, causes phase out-of-lock, and cannot make adjustments out of the current overflow or underflow. In any of the above cases, the memory chip cannot provide data and instructions at an accurate time, resulting in failure of data transmission. Particularly, with the development of integrated circuit technology and the deep application demands, when the device integrated with the DRAM is applied to an extreme environment, the temperature abrupt change occurs, and the phenomenon of overflow or underflow is more likely to occur, so that the output clock dqs of the DRAM cannot be aligned with the external clock clk, and at this time, the existing DLL circuit cannot correct the phase of the output clock dqs again, and the memory chip cannot accurately transmit data finally.

A known solution is to reset the DLL circuit. Resetting the DLL circuit takes a relatively long time, for example DDR4-2666 memory, requiring a DLL circuit latch time (locking time) of 854tCK. During this time the DRAM chip cannot receive any instructions and subsequent instructions will be lost. For DRAM chips that are in operation, it is clear that resetting the DLL circuit does not quickly relock the DLL circuit and is not an effective solution to the overflow or underflow. Adverse effects caused by temperature variations and the like that trigger overflow or underflow limit the application of DRAM memory and integrated circuit devices having the same in complex environments.

Therefore, a method for rapidly relocking the DLL circuit is needed to be studied, the DLL circuit can be restored to the normal locked state of the DLL circuit in a short time without resetting, and the problem that a large amount of instructions and data are lost when underflow or overflow occurs in the DLL circuit in the DRAM memory is solved, so that the deep development and wide application of the semiconductor integrated circuit technology are further promoted.

Disclosure of Invention

The invention aims to solve all or part of the problems in the prior art, and provides a method for rapidly relocking a DLL circuit, which is used for enabling the DLL circuit to jump out of an overflow or underflow state in time and relock in a short time so as to realize correct transmission of data and instructions.

In order to facilitate understanding of the present disclosure, the principles of DLL circuit operation and overflow and underflow phenomena related to the present disclosure are described by way of example and not limitation. As shown in fig. 1, the external clock clk is supplied by the CPU. The DLL circuit includes a duty cycle adjustment module DCC (Duty Cycle Correction) for adjusting the duty cycle of the clock and a delay chain module delay_line for providing an adjustable delay amount. There is also a fixed delay module DELAY REPLICA for reproducing the true delay of the Logic circuit of figure 1. This is because the Logic circuit needs to add the effect of this part of the Logic circuit on the clock to the DLL circuit after the DLL circuit so that the output clock dqs after passing through the Logic circuit may be phase aligned with clk. In the present invention, the overflow refers to the phase difference indication outputted by the phase detection module PHASE DETECT needs to continuously increase the delay amount provided by the current DLL circuit, but the delay_line of the delay chain module has provided the maximum delay amount. underflow is that the phase difference outputted by the phase detection module PHASE DETECT indicates that the delay is required to be reduced, but the delay chain module delay_line already provides the minimum delay. Since underflow or overflow results in the delay amount required to be provided by the delay line module delay_line, the adjustable range of the delay line module delay_line is exceeded, and if the control module control only increases or decreases the delay units participating in the delay link in the delay line module delay_line according to the phase difference output by the phase detection module PHASE DETECT, the delay line module delay_line will be blocked at the maximum value or the minimum value of the delay amount, so that the DRAM is in the out-of-lock state and needs to be locked again.

The method for rapidly relocking the DLL circuit comprises a control module and a delay chain module, wherein the delay chain module comprises a coarse tuning delay module and a fine tuning delay module which are connected in series, the method comprises the steps of S1, obtaining the phase difference between a current external clock and a feedback clock of the DLL circuit and the current delay amount provided by the coarse tuning delay module through the control module, S2, judging whether the current delay amount can be changed continuously to compensate the phase difference, detecting whether overflow or underflow exists in real time, if not, updating the current delay amount to update the feedback clock through the control module based on the phase difference, returning to the step S1, if so, randomly generating an updated control signal through the control module to set the current delay amount to enable the DLL circuit to deviate from the overflow or the underflow, returning to the step S1, and repeating the steps S1 to S2 until the external clock is aligned with the feedback clock. When the DLL circuit overflows or underflows, an updated delay amount can be set by randomly generating an updated control signal, a feedback clock can still be obtained in response to the control signal, and the locking process is restarted in time.

The coarse delay module comprises a plurality of delay links, the delay links comprise a plurality of delay units in cascade connection, the current delay amount is based on the number of the delay units experienced by an internal clock of the DLL circuit, the real-time detection of whether overflow or underflow exists comprises the steps of determining whether the current delay amount needs to be continuously increased or decreased according to the phase difference, obtaining the number of the delay units which are currently used through the control module, and judging whether the number of the delay units can be continuously changed to continuously increase or decrease the current delay amount.

The overflow is detected by determining that the overflow exists if the current delay amount needs to be increased continuously and the delay unit which is currently used is the most.

The underflow is detected by determining that an underflow exists if the current delay amount needs to be reduced continuously while the delay unit currently used is already at a minimum.

The control signals comprise first control signals and second control signals, the internal clock responds to the first control signals and goes through a plurality of delay units to obtain a first clock, the internal clock responds to the second control signals and goes through a plurality of delay units to obtain a second clock, the DLL circuit is separated from the overflow or the underflow by keeping the current first control signals unchanged to keep the current first clock unchanged, a new second control signal is randomly generated, the internal clock is controlled to go through a random number of delay units to update the second clock, and the feedback clock is updated based on the current first clock and the updated second clock.

The current first clock is passed through the DLL circuit as a temporary clock for current output data before the updated second control signal is randomly generated. When detecting that the DLL circuit overflows or underflows, the first clock is directly output to an external circuit as a temporary clock of output data after being delayed by a subsequent part of the DLL circuit, and the clock with the minimum error is provided for the output data before the re-locking as the temporary clock before the re-locking is realized, so that the interruption of the data reading at the moment is avoided, the continuity of the data reading of the DRAM is ensured, and the instruction and the data loss in the time required for realizing the re-locking are reduced.

The DLL circuit further comprises a duty ratio adjusting module connected with the input end of the coarse adjustment delay module and used for receiving an external clock and outputting the internal clock after adjusting the duty ratio of the external clock, the delay link comprises a first branched chain and a second branched chain which are respectively provided with N delay units, the first clock is obtained by delaying the internal clock by i delay units of the first branched chain to obtain a first clock, i is more than or equal to 1 and less than or equal to N, the second clock is obtained by delaying the internal clock by j delay units of the second branched chain to obtain a second clock, j is more than or equal to 1 and less than or equal to N, N, i and j are positive integers, and the process of judging whether the number of the delay units can be continuously changed to continuously increase or decrease the current delay amount comprises judging whether the difference value of i and j can be continuously increased or decreased.

The first clock is an odd frequency division signal, and the second clock is an even frequency division signal.

The method for updating the feedback clock comprises the steps that the fine tuning delay module responds to the fine tuning control signal, delays the first clock based on the phase difference of the first clock and the second clock to obtain and output a delay clock, and the delay clock accumulation system is fixedly delayed to obtain the feedback clock.

The method for obtaining the delay clock comprises the steps of equally dividing the phase difference between the first clock and the second clock into a plurality of delay step sizes based on the delay precision requirement, and delaying the first clock Zhong Leijia by m delay step sizes to obtain the delay clock. The unit delay step length is equally divided by the fine adjustment delay module according to the specific delay precision requirement, and the number of parts accumulation delay quantity of the delay step length is set by the fine adjustment control signal, so that the locking speed and precision are further improved.

Compared with the prior art, the invention has the main beneficial effects that:

1. The method for rapidly relocking the DLL circuit detects whether the DLL circuit overflows or underflows in real time by judging whether the current delay amount can be changed continuously to compensate the phase difference, correspondingly sets the control signal according to the detection result, can rapidly align the external clock with the feedback clock, and can recover to a normal phase locking state in a shorter time without resetting the DLL circuit by randomly updating the control signal, thereby ensuring the phase alignment of the output clock and the input clock of the DRAM. By using the first clock to directly output through the DLL circuit when overflow or underflow occurs, the clock which provides the minimum error for outputting data before being locked again is provided, transmission interruption is avoided, and the loss of instructions and data is greatly reduced.

2. The method for rapidly relocking the DLL circuit is extremely beneficial to improving the reliability of the operation of the DRAM, provides a practical and effective solution for breaking through the limit of adverse effects on the equipment application of the integrated DRAM caused by environmental factors such as temperature and the like, and further promotes the deep application of the integrated circuit equipment in a complex environment.

Drawings

Fig. 1 is a schematic diagram of an exemplary DLL circuit synchronous clock according to the present invention.

Fig. 2 is a block diagram of a DLL circuit according to a first embodiment of the present invention.

Fig. 3 is a simplified block diagram of a DLL circuit according to a first embodiment of the present invention.

Fig. 4 is a signal timing diagram of the DLL circuit in the first embodiment of the present invention when the DLL circuit is normally phase locked.

Fig. 5 is a schematic diagram of a basic structure of a delay chain module according to a first embodiment of the present invention.

Fig. 6 is a schematic diagram of a delay chain according to a first embodiment of the present invention.

Fig. 7 is a timing diagram of signals output by the fine tuning delay module according to the first embodiment of the present invention.

Fig. 8 is a schematic diagram of a delay link as soon as underflow occurs in an embodiment of the present invention.

FIG. 9 is a flowchart illustrating a method for fast relocking a DLL circuit according to an embodiment of the present invention.

Fig. 10 is a schematic diagram of delay links in a first embodiment of the invention for relocking a DLL circuit.

Fig. 11 is a schematic diagram of delay links in the second embodiment of the present invention when overflow occurs.

Fig. 12 is a schematic diagram of delay links in a second embodiment of the invention for relocking a DLL circuit.

Detailed Description

The operations of the embodiments are depicted in the following examples in a particular order, which is presented to provide a better understanding of the details of the embodiments and to provide a thorough understanding of the invention, but is not necessarily a one-to-one correspondence with the methods of the invention, nor is it intended to limit the scope of the invention in this regard.

Example 1

As shown in fig. 2, the DLL circuit illustrated in this embodiment includes a phase demodulation module PHASE DETECT, a control module control, a duty cycle adjustment module DCC, a delay chain module delay_line, and a fixed delay module delay_reply. Wherein the communication connections of the parts are the same as the conventional DLL circuit and are not expanded. After the external clock clk and the initial feedback clock clk_fb are subjected to phase comparison by the phase discrimination module PHASE DETECT, a control module control makes a control strategy to omit a control duty ratio adjustment module DCC and a delay chain module delay_line. In the example case, the duty cycle adjustment module DCC adjusts the duty cycle of the external clock clk to 50% to obtain the internal clock. The external clock clk is delayed by the delay chain module delay_line to obtain a delay clock clk_1, and the delay module delay_replica accumulation system is used for fixedly delaying and updating the feedback clock clk_fb by the clk_1. In order to facilitate understanding of the gist of the present invention, the work of the duty ratio adjustment module DCC is omitted, as shown in fig. 3, the delay chain module delay_line and the fixed delay module delay_reply in the DLL circuit structure of fig. 2 can be simplified in fig. 3, and the expansion example provides the working condition of the current delay amount. It should be noted that the above is simplified for convenience of description, and it cannot be considered that the duty ratio adjustment module DCC is not necessarily present in the DLL circuit structure of the present embodiment. In this embodiment, when the DLL circuit is normally locked, a timing chart of the delay clock clk_1 outputted by the delay line module, the inputted external clock clk, and the feedback clock clk_fb outputted by the DLL circuit during phase locking is shown in fig. 4. The analog delay link of the fixed delay module delay_reply is the delay amount of the replica system, and is affected by factors such as process drift, temperature, and the like. For clarity of description, the delay amount is characterized by a delay time in this embodiment. In the application scenario of the present embodiment, the temperature is positively correlated with the delay time of the fixed delay module delay_reply. When the temperature rises, the delay time t_rep of the fixed delay module delay_replica becomes long, and the total delay time t_delay of the normal phase lock is fixed, so that the delay time t_line of the delay chain module delay_line needs to be reduced to ensure the normal operation of the DLL circuit. However, when the temperature rises above a certain range, t_line needs to be reduced to be smaller than the minimum delay time provided by the delay chain module delay_line, and at this time, t_line cannot be reduced any more, so that the DLL circuit cannot be locked normally. This out-of-lock condition is referred to as underflow in this embodiment. Conversely, when the temperature decreases, the delay time t_rep of the delay_replica is correspondingly shortened, resulting in a continuous increase of the delay time t_line required by the delay_line of the delay chain module. When the delay time t_line is required to be increased to the maximum delay time that can be provided by the delay_line of the delay chain module, the t_line cannot be increased continuously, and the DLL circuit cannot be locked normally, and in this embodiment, the out-of-lock condition is referred to as an overslow. In the DRAM memory, the external clock clk is a command clock of the CPU, and the feedback clock clk_fb is a clock that outputs data. When the overflow or underflow occurs, the DLL circuit does not have a normal phase lock, the external clock clk and the current feedback clock clk_fb cannot be kept in phase, and the external clock clk and the current feedback clock clk_fb need to be quickly separated from the overflow or underflow, and the data of the DRAM can be ensured to be read normally by the CPU.

The delay chain module delay_line and the signal flow of the present embodiment are shown in fig. 5. The internal clock clk_coarse input to the coarse delay module coarse delay generates the first and second clocks input to the fine delay module FINE DELAY in response to the first and second control signals output from the control module control. The delay chain as illustrated in fig. 6 includes a first branch a and a second branch B each having N delay units. 1≤i≤N, 1≤j≤N, wherein N, i and j are positive integers. The control module control in this embodiment includes a detection unit, a first counter, a second counter, and a third counter. When underflow or overflow does not exist, the control module control outputs a command for increasing or decreasing the current delay amount according to the magnitude of the current phase difference. The example first control signal is an odd control code cnt_odd and the second control signal is an even control code cnt_even. The fine control signal is directly input to the fine delay module FINE DELAY, which includes a count control code cnt_fine. In this embodiment, the first clock clk_odd is an odd-numbered frequency-divided signal generated by the internal clock clk_coarse through i delay units, and the second clock clk_even is an even-numbered frequency-divided signal generated by the internal clock clk_coarse through j delay units. The first clock clk_odd and the second clock clk_even are input together to the fine delay module FINE DELAY. As shown in fig. 6, each delay unit is exemplified by three nand gates, and the output terminals of the two nand gates are respectively connected to the first input terminal and the second input terminal of the third nand gate. The delay unit may have other structures such as an inverter, a transmission gate, and the like, and a circuit structure for realizing a delay function is not limited. The delay cells illustrated in fig. 6 total 18, i.e. an exemplary value of N is 9. The first clock clk_odd can be generated using 9 delay cells at most, and the second clock clk_even can be generated using 9 delay cells at most. The number of delay units in the coarse delay module coarse delay and the maximum values of i and j are not limited, and can be set accordingly according to practical application or specific product design parameters. The number of nand gates undergone by the first clock clk_odd and the second clock clk_even in the present embodiment is either even or odd. The first clock clk_odd and the second clock clk_even have a phase difference. In this embodiment, the fine tuning control signal further includes a frequency division signal, which is configured to divide the frequency according to the actual requirement of the delay precision, and divide the phase difference between the first clock clk_odd and the second clock clk_even by several equal parts to further fine tune the delay amount, where each equal part is a delay step (the greater the number of equal parts, the smaller the single delay amount of fine tuning delay, and the higher the precision of delay). The phases of the first clock clk_odd and the second clock clk_even are differentiated into n equal parts, one delay step is one n times of the phase difference, and the fine tuning control signal cnt_fine is input into the fine tuning delay module FINE DELAY for selecting to delay the input first clock clk_odd by m delay steps, namely assigning the value to m. The delay clock clk_1 output by the delay chain module delay_line is obtained by adding m delay steps to the first clock clk_odd. In the example case shown in fig. 7, a 1/8 ratio divider is used, n is 8 and m is 2. the result of the fine delay is to add two delay steps on the basis of the first clock clk odd.

In the DLL circuit locking process of this embodiment, the control module control decides to increase or decrease the delay amount that has been provided currently according to the obtained phase difference, and the first control signal cnt_odd and the second control signal cnt_even that are generated correspondingly determine to use several delay units in the coarse delay module coarse delay, i.e. assign values to i and j. And the number of delay units used in the delay links through which the first clock clk_odd and the second clock clk_even pass is alternately increased or decreased, which is determined by the first control signal cnt_odd and the second control signal cnt_even. In this embodiment, the delay link when underflow occurs is as shown in fig. 8, and after comparing the phases of the external clock clk and the current feedback clock clk_fb, the command issued by the control module control is to continue to decrease the current delay amount, but at this time, the delay link has been engaged with the least delay unit, i.e. both current i and j are already at their minimum value of 1. It can be known that the number of delay units used in the second branch B, which is experienced by the first clock clk_odd and the second clock clk_even, cannot be continuously and alternately reduced, i.e., the difference between i and j cannot be continuously reduced. The phase difference between the first clock clk_odd and the second clock clk_even as illustrated in fig. 8 is already minimum, and the delay amount of the delay clock clk_1 cannot be continuously reduced, i.e., t_line cannot be reduced. The detection unit detects underflow that this time has occurred. As shown in fig. 9, the exemplary method of fast relocking the DLL circuit includes step s1 of acquiring, by a control module control, a phase difference between a current external clock clk and a feedback clock clk_fb and a current delay amount provided by a coarse delay module coarse delay. And S2, judging whether the current delay amount can be changed continuously to compensate the phase difference, and detecting whether underflow exists in real time. And if the delay amount is not present, the control module control updates the current control signal based on the phase difference to adjust the current delay amount to update the feedback clock, and the step S1 is returned, and if the delay amount is not present, the control module control randomly generates a new control signal to set the current delay amount so that the DLL circuit is separated from underflow, and the step S1 is returned. Steps S1 to S2 are repeated until the external clock clk is phase aligned with the feedback clock clk_fb. The method for fast relocking the DLL circuit of the present embodiment may be implemented by designing a control module by a digital ASIC flow in combination with a VLSI design and a corresponding algorithm. There are also specific applications implemented by analog circuit design, not limited thereto.

Control block control keeps the current first control signal cnt_odd unchanged at underflow, so that the current first clock clk_odd remains unchanged. The control module control randomly sets a new second control signal cnt_even to control the internal clock clk_coarse to obtain an updated second clock clk_even through a random number of delay units. As shown in fig. 10, the random number of the example of this embodiment is 5 delay units, and the random number is not limited as long as it is greater than the minimum value of j. The new second clock clk_even and the unchanged current first clock clk_odd are input into the fine tuning delay module FINE DELAY to generate an updated delay clock clk_1, the updated feedback clock clk_fb is output after the delay_replica is passed through the fixed delay module, the phase discrimination module PHASE DETECT performs phase comparison based on the updated feedback clock clk_fb and the external clock clk, and the control module control updates the first control signal and the second control signal according to the phase difference at the moment to restart the phase locking process of the DLL circuit until the external clock clk is aligned with the final feedback clock clk_fb. In this embodiment, taking the case that the first control signal is an odd control code cnt_odd and the second control signal is an even control code cnt_even as an example, for the sake of understanding the present invention, in other embodiments, the delay link structure of the coarse delay module coarse delay and the circuit structure of the fine delay module FINE DELAY are set correspondingly according to practical applications and product designs, the corresponding counter or the signal generated by the counter may have more, the control signal may be a digital signal or an analog signal, and the setting is corresponding according to the DLL circuit design of the specific application, but not limited thereto.

Example two

As shown in fig. 11, embodiment two expands an example of a method of quickly relocking a DLL circuit when overflow occurs. In step S2, it is determined whether the current delay amount can be changed continuously to compensate for the phase difference, and whether there is overflow is detected in real time. After comparing the phases of the external clock clk and the feedback clock clk_fb of the current input DLL circuit, the control module control determines that a command for increasing delay needs to be issued, and the detection unit determines that the most delay units in the current first branch a and second branch B have been used to participate in the delay link. I.e. it is determined that the values of current i and j respectively have reached their maximum values. Then it is detected that the DLL circuit is over-flowing at this time. As shown in fig. 11, the current first clock clk_odd is already generated after the internal clock clk_coarse passes through 9 delay units, and the second clock clk_even is also obtained after the internal clock clk_coarse passes through 9 delay units, and at this time, the current delay amount cannot be increased. As shown in fig. 12, the control module control keeps the current first control signal cnt_odd unchanged at this time, so that the current first clock clk_odd remains unchanged. On one hand, the clock output by the current first clock clk_odd after passing through the fine tuning delay module FINE DELAY and then passing through the fixed delay module delay_replica is used as the clock for outputting data, so that the current DRAM memory can read and write data normally without losing instructions and data. On the other hand, the control module control sets a new second control signal cnt_even to control the internal clock clk_coarse to obtain an updated second clock clk_even through a random number of delay units. The random number of the embodiment is 5 delay units, and the random number is smaller than the maximum value of j, and is not limited. The updated second clock clk_even and the unchanged current first clock clk_odd are input into the fine tuning delay module FINE DELAY to generate an updated delay clock clk_1, the updated delay clock clk_fb is output after passing through the fixed delay module delay_replica, the phase discrimination module PHASE DETECT performs phase comparison based on the updated feedback clock clk_fb and the external clock clk, and the control module control obtains a first control signal and a second control signal according to the phase difference at the moment to restart the phase locking process of the DLL circuit until the external clock clk is identical to the final feedback clock clk_fb in phase.

In this embodiment, the specific configuration of the control module control is exemplified by the detection unit and the counting unit, and the corresponding example of the control signal as the counter signal is taken for facilitating understanding of the specific application of the present invention. In other embodiments, the control module control is of other specific circuit structures, and may further include circuit elements such as an encoder, a buffer, and a logic unit, where the control signal is not a counter signal, such as a current signal or a voltage signal, or other analog signals, and is not limited. In this embodiment, an example is given of a method of detecting whether there is overflow in real time by the control module, and in some cases, other methods of combining specific circuit structures may be adopted, for example, by comparing the current phase difference with the phase difference at the previous time to determine whether the two phase comparison results are different, so as to detect whether the DLL circuit is in a normal working state, which is not limited.

The use of certain conventional english terms or letters for the sake of clarity of description of the invention is intended to be exemplary only and not limiting of the interpretation or particular use, and should not be taken to limit the scope of the invention in terms of its possible chinese translations or specific letters. It should also be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

Specific examples are set forth herein to illustrate the structure and principles of the invention, and the above examples are provided only to assist in understanding the methods and core concepts of the invention. It should be noted that it will be apparent to those skilled in the art that various improvements and modifications can be made to the present invention without departing from the principles of the invention, and such improvements and modifications fall within the scope of the appended claims.

Claims (9)

1. The method for rapidly relocking the DLL circuit comprises a control module and a delay chain module, wherein the delay chain module comprises a coarse tuning delay module and a fine tuning delay module which are connected in series, and the method is characterized by comprising the following steps:

s1, obtaining a phase difference between a current external clock and a feedback clock of the DLL circuit and a current delay amount provided by the coarse delay module through the control module;

S2, judging whether the current delay amount can be continuously changed to compensate the phase difference, and detecting whether overflow or underflow exists in real time;

if not, updating the current control signal based on the phase difference by the control module to adjust the current delay amount to update the feedback clock, returning to the step S1, and if so, randomly generating the updated control signal by the control module to set the current delay amount so that the DLL circuit is separated from the overflow or the underflow, and returning to the step S1;

repeating the steps S1 to S2 until the external clock is phase aligned with the feedback clock;

The control signal comprises a first control signal and a second control signal, wherein the internal clock responds to the first control signal and goes through a plurality of delay units to obtain a first clock;

The way to disengage the DLL circuit from the overflow or the underflow is:

maintaining the current first control signal unchanged to maintain the current first clock unchanged;

randomly generating a new second control signal, and controlling the internal clock to update the second clock through a random number of delay units;

the feedback clock is updated based on the current first clock and the updated second clock.

2. The method of fast relocking a DLL circuit of claim 1, wherein said coarse delay module comprises a plurality of delay links, said delay links comprising a plurality of delay cells in cascade, said current delay amount being based on the number of delay cells experienced by an internal clock of said DLL circuit, said detecting in real time whether there is an overflow or an underflow comprising:

determining that the current delay amount needs to be continuously increased or decreased according to the phase difference;

And acquiring the number of the delay units which are currently used through the control module, and judging whether the number of the delay units can be continuously changed to continuously increase or decrease the current delay amount.

3. The method of fast relocking DLL circuit of claim 2, wherein detecting the presence of the overflow is by determining that the overflow is present if the current delay amount needs to be increased further and the delay unit that has been currently used is the most.

4. The method of fast relocking DLL circuit of claim 2, wherein detecting the presence of the underflow is by determining that the underflow is present if the current delay amount needs to continue to be reduced while the delay cell that is currently in use is at a minimum.

5. The method of fast relocking a DLL circuit according to claim 1, wherein the current first clock is used as a temporary clock for current output data through the DLL circuit before randomly generating the updated second control signal.

6. The method of claim 1, wherein the DLL circuit further comprises a duty cycle adjustment module connected to the input of the coarse delay module for receiving an external clock and outputting the internal clock after adjusting the duty cycle thereof;

the method for obtaining the first clock is that the internal clock is delayed by i delay units of the first branched chain to obtain the first clock, i is more than or equal to 1 and less than or equal to N;

the method for obtaining the second clock is that the internal clock is delayed by j delay units of the second branched chain to obtain the second clock, wherein j is more than or equal to 1 and less than or equal to N;

Wherein N, i and j are positive integers, and determining whether the number of delay units can be changed continuously to continue to increase or decrease the current delay amount includes determining whether the difference between i and j can be increased or decreased continuously.

7. The method of fast relocking a DLL circuit of claim 6, wherein said first clock is an odd divided signal and said second clock is an even divided signal.

8. The method of claim 7, wherein the control signal further comprises a fine control signal, wherein updating the feedback clock comprises the fine delay module delaying the first clock based on a phase difference between the first clock and the second clock to obtain and output a delayed clock in response to the fine control signal, and wherein the delay clock accumulation system is fixedly delayed to obtain the feedback clock.

9. The method for quickly relocking the DLL circuit of claim 8, wherein the delay clock is obtained by dividing the phase difference between the first clock and the second clock into a plurality of delay steps based on the delay precision requirement;

Delaying the first clock Zhong Leijia by m delay steps to obtain the delay clock.