CN113890505B - Phase selector and phase selection signal output method - Google Patents
Phase selector and phase selection signal output methodInfo
- Publication number
- CN113890505B CN113890505B CN202111025426.9A CN202111025426A CN113890505B CN 113890505 B CN113890505 B CN 113890505B CN 202111025426 A CN202111025426 A CN 202111025426A CN 113890505 B CN113890505 B CN 113890505B
- Authority
- CN
- China
- Prior art keywords
- signal
- phase
- shift
- signals
- trigger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/16—Networks for phase shifting
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
本发明公开了一种相位选择器和相位选择信号输出方法，用以提高相位选择器的灵活性和移植性。相位选择器包括移位信号产生电路、移位电路和相位选择电路，移位信号产生电路在相位移动标志信号的控制下，对相位选择信号进行计数，并将得到的计数信号与移位个数信号进行比较，根据比较结果、相位移动标志信号和相位选择信号输出相位移动信号，移位电路在相位移动信号的控制下，改变相位选择开关信号，相位选择电路根据改变后的相位选择信号，从n个具有不同相位的数据信号中选择一个数据信号作为相位选择信号。由于在相位移动信号的控制下，改变相位选择开关，选择不同相位的数据信号作为相位选择信号，从而可以提高相位选择器的灵活性和可移植性。
The present invention discloses a phase selector and a phase selection signal output method for improving the flexibility and portability of the phase selector. The phase selector includes a shift signal generating circuit, a shift circuit, and a phase selection circuit. The shift signal generating circuit counts the phase selection signal under the control of a phase shift flag signal and compares the resulting count signal with a shift count signal. The phase shift signal is output based on the comparison result, the phase shift flag signal, and the phase selection signal. The shift circuit changes the phase selection switch signal under the control of the phase shift signal. The phase selection circuit selects a data signal from n data signals with different phases as the phase selection signal based on the changed phase selection signal. Since the phase selection switch is changed under the control of the phase shift signal to select a data signal with a different phase as the phase selection signal, the flexibility and portability of the phase selector can be improved.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a phase selector and a phase selection signal output method.
Background
The phase selector with the traditional structure can only realize one-time phase selection, or can only select a clock signal with a fixed phase before and after the phase, or can only respond to the change of a fixed phase difference number, so that the phase selector with the traditional structure cannot meet a circuit with complex functional requirements.
For example, in clock recovery circuits and clock generation circuits, phase locked loops have a phase selection of multiphase voltage controlled oscillators to meet fractional division requirements and low jitter requirements. Some circuit structures formed by analog transistors can realize slightly complex logic requirements, but the circuit scale is large, the performance is greatly influenced by the manufacturing process, and the design defects are relatively large. Conventional phase selectors do not meet the requirements of the above-described circuits. Therefore, the existing phase selector has poor flexibility and is not easy to transplant.
Disclosure of Invention
The invention provides a phase selector and a phase selection signal output method, which are used for solving the problems that the phase selector in the prior art is poor in flexibility and not easy to transplant.
In a first aspect, an embodiment of the present invention provides a phase selector including a shift signal generating circuit, a shift circuit, and a phase selecting circuit;
The shift signal generating circuit is used for counting the phase selection signal under the control of the phase shift mark signal to obtain a count signal, comparing the obtained count signal with a shift number signal, and outputting a phase shift signal for controlling phase shift according to a comparison result, the phase shift mark signal and the phase selection signal;
The shift circuit is used for changing a phase selection switch signal under the control of the phase shift signal;
the phase selection circuit is used for selecting one data signal from n data signals with different phases as the phase selection signal according to the changed phase selection signal and outputting the data signal, wherein n is a positive integer.
In one possible implementation, the shift signal generating circuit includes a counting circuit, a count comparing circuit, and a shift signal generating sub-circuit;
the counting circuit is used for counting the phase selection signals under the control of the phase movement mark signals and outputting m counting signals;
the counting comparison circuit is used for comparing m counting signals with m shifting number signals and outputting signals representing whether the m counting signals and the m shifting number signals are identical or not;
the shift signal generating sub-circuit is used for carrying out logic operation on the phase selection signal under the control of the signal with the same shift number and the phase shift mark signal, and outputting the phase shift signal;
wherein m is a positive integer greater than 2.
In one possible implementation, the counting circuit includes a first inverter, m flip-flops, and an inverter combination;
the input end of the first inverter is used for inputting the phase shift flag signal, and the output end of the first inverter is connected with the R end of each trigger;
in each combination, the D end of the trigger is connected with the output end of the inverter, and the Q end of the trigger is connected with the input end of the inverter and is used for sequentially outputting m counting signals;
In the first combination, the CK terminal of the flip-flop is used for inputting the phase selection signal, and in other combinations, the CK terminal of the flip-flop is connected with the output terminal of the inverter in the last combination.
In one possible implementation, the count comparison circuit includes m exclusive or gates and a first and gate;
For each exclusive or gate, a first input end of the exclusive or gate is used for inputting a counting signal, a second input end of the exclusive or gate is used for inputting a shift number signal corresponding to the counting signal, and an output end of the exclusive or gate is connected with one input end of the first and gate;
the output end of the first AND gate is used for outputting the signals with the same shifting number.
In one possible implementation, the shift signal generating sub-circuit includes a voltage clamp high logic tiehi gate, a first flip-flop, a second flip-flop, and a second and gate;
the output end of the tiehi gate is connected with the D end of the first trigger and is used for outputting a first level;
The R end of the first trigger is used for inputting the signals with the same shifting number, the CK end of the first trigger is used for inputting the phase shifting mark signals, and the Q end of the first trigger is connected with the D end of the second trigger;
The R end of the second trigger is used for inputting a reset signal, the ck end of the second trigger is used for inputting the phase selection signal, and the Q end of the second trigger is connected with the first input end of the second AND gate;
the second input end of the second AND gate is used for inputting the phase selection signal, and the output end of the second AND gate is used for outputting the phase shift signal.
In one possible embodiment, the shift circuit includes a third flip-flop, (n-1) fourth flip-flops, a second inverter, and a third inverter;
For (n-1) fourth flip-flops, the D terminal of the first fourth flip-flop is connected to the output terminal of the third inverter for outputting a first selection switch signal, the Q terminal of the last fourth flip-flop is connected to the input terminal of the second inverter for outputting a last selection switch signal, the Q terminal of the previous fourth flip-flop is connected to the D terminal of the next fourth flip-flop for sequentially outputting a selection switch signal, the R terminal of each fourth flip-flop is used for inputting a reset signal, and the CK terminal of each fourth flip-flop is used for inputting the phase shift signal;
the D end of the third trigger is connected with the output end of the second inverter, the Q end of the third trigger is connected with the input end of the third inverter, the R end of the third trigger is used for inputting the reset signal, and the CK end of the third trigger is used for inputting the phase shift signal.
In one possible embodiment, the phase selection circuit includes m fourth inverters and m switches corresponding to each fourth inverter;
for each group of fourth inverter and switch, the input end of the fourth inverter is connected with the first control end of the switch and is used for inputting a phase selection switch signal, and the output end of the fourth inverter is connected with the second control end of the switch;
The first end of the switch is used for inputting a data signal corresponding to the phase selection switch signal, and the second end of the switch is used for outputting the phase selection signal.
In one possible embodiment, the switch comprises a first switching tube and a second switching tube;
The control end of the first switching tube is used as a first control end of the switch, the first end of the first switching tube is connected with the first end of the second switching tube, and the second end of the first switching tube is connected with the second end of the second switching tube;
the control end of the second switching tube is used as a second control end of the switch.
In a second aspect, an embodiment of the present invention provides a phase selection signal output method, including:
under the control of the phase shift flag signal, counting the phase selection signal to obtain a count signal, comparing the obtained count signal with a shift number signal, and outputting a phase shift signal for controlling phase shift according to a comparison result, the phase shift flag signal and the phase selection signal;
under the control of the phase shift signal, changing a phase selection switch signal;
And selecting one data signal from n data signals with different phases as the phase selection signal according to the changed phase selection signal, and outputting the data signal, wherein n is a positive integer greater than 2.
In one possible implementation manner, the counting the phase selection signal under the control of the phase shift flag signal, obtaining a count signal, comparing the obtained count signal with the shift number signal, and outputting a phase shift signal for controlling the phase shift according to the comparison result, the phase shift flag signal and the phase selection signal, including:
under the control of the phase shift flag signal, counting the phase selection signals and outputting m counting signals;
Comparing the m count signals with the m shift number signals, and outputting signals representing whether the m count signals and the m shift number signals are identical in shift number or not;
under the control of the phase shift number same signal, the phase shift flag signal and the reset signal, carrying out logic operation on the phase selection signal and outputting the phase shift signal;
wherein m is a positive integer greater than 2.
The phase selector comprises a shift signal generating circuit, a shift circuit and a phase selecting circuit, wherein the shift signal generating circuit counts phase selecting signals under the control of phase shifting marking signals to obtain counting signals, compares the counting signals with shifting number signals, outputs phase shifting signals for controlling phase shifting according to comparison results, the phase shifting marking signals and the phase selecting signals, changes phase selecting switch signals under the control of the phase shifting signals, and selects one data signal from n data signals with different phases as a phase selecting signal according to the changed phase selecting signals and outputs the data signals, wherein n is a positive integer larger than 2. The phase selector can generate a phase shift signal for controlling phase shift, under the control of the phase shift signal, the phase selection switch can be changed, so that data signals with different phases can be selected as phase selection signals, phase selection can be performed according to actual needs, multiple times of phase selection can be realized, the phase of the output phase selection signals is not fixed, and the flexibility and portability of the phase selector can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a phase selector according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another phase selector according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a counting circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a count comparing circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a shift signal generating sub-circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a shift circuit according to an embodiment of the present invention;
Fig. 7 is a schematic diagram of a phase selection circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another counting circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of another count comparison circuit according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of another shift signal generating sub-circuit according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of another shift circuit according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of another phase selection circuit according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of a timing signal according to an embodiment of the present invention;
Fig. 14 is a flowchart of a phase selection signal output method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to solve the technical problems that a phase selector in the prior art is poor in flexibility and difficult to transplant, the phase selector provided by the embodiment of the invention can accurately select the phase, respond to the phase change requirement in each clock period, enable the next output clock to select the signal of the next phase on the basis of the phase of the last clock period, and select the data signal with the target phase after shifting and selecting for a plurality of times, so that the flexibility and portability of the phase selector are improved.
As shown in fig. 1, a phase selector according to an embodiment of the present invention includes a shift signal generating circuit 101, a shift circuit 102, and a phase selecting circuit 103;
The shift signal generating circuit 101 is configured to count the phase_mux of the phase selection signal under the control of the phase shift flag signal clk, obtain a count signal Q, compare the count signal Q with the shift number signal num, and output a phase shift signal phase_shift for controlling phase shift according to the comparison result, the phase shift flag signal clk, and the phase selection signal phase_mux;
a shift circuit 102 for changing the phase selection switch signal sel under the control of the phase shift signal phase_shift;
A phase selection circuit 103 for selecting one data signal from n data signals having different phases as the phase selection signal according to the changed phase selection signal sel, and outputting the same, wherein n is a positive integer greater than 2.
In the embodiment of the invention, a shift signal generating circuit counts a phase selection signal under the control of a phase shift mark signal to obtain a count signal, compares the count signal with a shift number signal, outputs a phase shift signal for controlling phase shift according to a comparison result, the phase shift mark signal and the phase selection signal, changes a phase selection switch signal under the control of the phase shift signal, and selects one data signal from n data signals with different phases as a phase selection signal and outputs the data signal according to the changed phase selection signal, wherein n is a positive integer greater than 2. The phase selector can generate a phase shift signal for controlling phase shift, under the control of the phase shift signal, the phase selection switch can be changed, so that data signals with different phases can be selected as phase selection signals, phase selection can be performed according to actual needs, multiple times of phase selection can be realized, the phase of the output phase selection signals is not fixed, and the flexibility and portability of the phase selector can be improved.
In the embodiment of the invention, the phase selection signal output by the phase selection circuit is taken as the input of the shift signal generation circuit, and when a plurality of phase shift mark signal clk periods need to be selected in phase, the counting and the shifting of the next clk period can be performed.
In an implementation, the shift signal generating circuit 101 may include a count circuit 1011, a count comparing circuit 1012, and a shift signal generating sub-circuit 1013, as shown in fig. 2.
As can be seen from fig. 2, the counting circuit 1011 is configured to count the phase_mux signal under the control of the phase shift flag signal clk, and output m count signals Qm-1.
The counting circuit 1011 is configured to count the phase_mux signal and output m count signals Qm-1..q.1, Q0, wherein the phase shift flag signal clk is a periodic signal for starting shifting the phase, and is a signal with a relatively low frequency; the phase selection signal phase_mux is a signal output by the phase selection circuit, the frequency is higher than the phase shift flag signal clk, the phase selection signal phase_mux is an output signal of the whole phase selector, and if a plurality of phase shift flag signal clk periods need phase selection as a final selection output result, the phase selection signal phase_mux is used as an input signal of the counting circuit 1011 to count and shift the next phase shift flag signal clk period, and the process is repeated.
When the phase shift flag signal clk signal is at a high level, the operation of counting the number of cycles and selecting the phase of the phase selection signal phase_mux is started, the count signals Qm-1. And the number of the counting digits is up to 1..11, the number of the counting digits is converted into decimal numbers and up to 2 m -1, the counting digits are reset to 0..00 for recycling counting after the number of the counting digits is more than the maximum counting range, the counting digits are consistent with the digits required to be shifted, and m is any positive integer. When the phase shift flag clk signal is low, the count stops and the output signal remains unchanged.
The count comparing circuit 1012 compares m count signals Qm-1..q 1, Q0 and m shift count signals num < m-1..num <1>, num <0>, and outputs a shift count identical signal indicating whether the m count signals and the m shift count signals are identical, where m is a positive integer.
Inputting m count signals Qm-1..q 1, Q0 and m shift number signals num < m-1..num <1>, num <0>, and outputting a shift number identical signal num_same; the shift number signals num <0>, num <1>. Are the least significant bits to the most significant bits of the number of phases to be shifted, and if the number is binary, the number of phases to be shifted=2 m-1+……+21+20＝2m -1. If the m count signals and the m shift count signals are the same, the output shift count same signal num_same is at a high level, which indicates that the shift count has reached the target count, and if the m count signals and the m shift count signals are different, the output shift count same signal num_same is at a low level.
In the embodiment of the invention, the counting signals and the shifting number signals are in one-to-one correspondence, whether the m counting signals and the m shifting number signals are identical or not is judged, namely whether each corresponding counting signal and each corresponding shifting number signal are identical or not is judged, and if all the corresponding counting signals and the corresponding shifting number signals are identical, the m counting signals and the m shifting number signals are identical.
For example, there are 4 count signals and 4 shift count signals, Q3, Q2, Q1, Q0 and num <3>, num <2>, num <1>, num <0>, respectively, and if Q3 and num <3> are the same, Q2 and num <2> are the same, Q1 and num <1> are the same, Q0 and num <0> are the same, then it is indicated that the 4 count signals and the 4 shift count signals are the same.
When the count signal and the shift count signal are compared, the level signals, such as a high level and a low level, are compared, and if the count signal and the shift count signal are both high or both low, the count signal and the shift count signal are the same.
The shift signal generating sub-circuit 1013 is configured to perform a logic operation on the phase selection signal phase_mux under the control of the shift number identical signal num_same and the phase shift flag signal clk, and output a phase shift signal phase_shift.
The phase shift flag signal clk, the phase selection signal phase_mux and the phase shift number identical signal num_same are input, and the phase shift signal phase_shift is output, namely under the control of the phase shift flag signal clk and the phase shift number identical signal num_same, the phase shift signal phase_shift is output according to the phase selection signal phase_mux, wherein the phase shift signal phase_shift is used for changing the phase selection switch signal sel.
Specifically, when the phase shift flag signal clk signal is at a high level, if the number of periods of the phase_mux is the same as the number of phases to be shifted, the same number of shifting bits num_same output by the count comparison circuit 1012 is at a high level, which indicates that the number of shifting times has reached the target number of times, and the same number of shifting bits num_same controls the output phase shift signal phase_shift of the subsequent shifting signal generating sub-circuit; when the number of periods of the phase selection signal phase_mux has not reached the number of phases to be shifted, the phase shift signal phase_shift is always inverted from logic 0 to logic 1 and from logic 1 to logic 0, the inversion period is the number of phase shifts required in the period of the phase shift flag signal clk, and the inversion frequency of the phase shift signal phase_shift is the same as that of the phase selection signal phase_mux because the phase shift signal phase_shift is logically operated by the phase selection signal phase_mux, and when the number of periods of the phase selection signal phase_mux reaches the number of phases to be shifted, the phase shift signal phase_shift is changed to 0 by the phase shift number same signal num_same, which marks the end of the shifting operation.
The shift circuit 102 is configured to change the phase selection switch signal sel under the control of the phase shift signal phase_shift.
The phase selection switch signals sel may be n, sel <0>, sel < 1..the phase selection switch signals sel < n >, i.e., the level signals sel <0>, sel < 1..sel < n >. Are changed.
Specifically, when the phase shift signal phase_shift is changed from logic 0 to logic 1, that is, from low level to high level, as the excitation signal of the shift circuit, the output signal phase selection switch signals sel <0>, sel < 1..sel < n > of the shift circuit are changed, and they are sequentially shifted on the basis of the last end.
For example, when sel <3> = 1 and the rest sel signals are 0 at the end of the last shift, if num <0> = 0 and num <1> = 1 and the rest num signals are 0, which means that 2 phase signals after the last data signal output need to be output in this shift, the phase shift signal phase_shift will generate 2 level inversions, that is, 2 inversion periods, when the phase shift signal phase_shift changes from low level to high level for the 1 st time, sel <3> = 0, sel <4> = 1 and rest sel is 0, when the phase shift signal phase_shift changes from low level to high level for the 2 nd time, sel <3> = 0, sel <4> = 0 and sel <5> = 1 rest sel is 0, so on, and this shift ends.
It should be noted that, in the embodiment of the present invention, the shifting is performed sequentially, rather than jumping from one phase to another, so that jitter may be reduced.
The phase selection circuit 103 is configured to select one data signal from n data signals phase having different phases as a phase selection signal phase_mux according to the changed phase selection signal sel, and output the selected data signal phase_mux, where n is a positive integer greater than 2. That is, the phase selection circuit 103 inputs n phase selection switch signals sel <0>, sel <1>,. Sel < n > and n data signals phase <0>, phase <1>,. Phase < n >, and outputs a phase selection signal phase_mux.
Specifically, sel <0>, sel <1>. Sel < n > are switches for selecting phases, and data signals phase <0>, phase <1>, phase < n > are data signals with different phases, and are multi-phase and same-frequency signals which need to be selected. One phase selection switch corresponds to one phase of the data signal: when sel <0> =1, the output signal phase_mux of the phase selection module selects phase <0> as an output, when sel <1> =1, the output signal phase_mux of the phase selection module selects phase <1> as an output. The output signal phase_mux of the phase selection module selects phase < n > as output, outputs the output signal as the input signal of the next phase selection, counts and shifts again when the next clk signal comes, and selects a new phase to come out, so that the function of continuously selecting any phase is realized.
As illustrated above, when it is necessary to output a signal of 2 phases after the last output data signal, if sel <3> =1 at the last end of shifting and the rest sel signals are 0, then phase <3> is selected as an output at the last time phase_mux, phase <4> is selected as an output at phase_shift 1 st time from low level to high level phase_mux, and phase <5> is selected as an output at phase_shift 2 nd time from low level to high level phase_mux, so phase_mux falls on phase <5> at the end of shifting.
If sel <0> = sel <1> =. The phase _ mux remains unchanged from the phase of the last cycle. Since the phase selection switches and the data signals of different phases are in one-to-one correspondence, the number thereof is the same.
It should be noted that, in the phase selector provided in the embodiment of the present invention, at the initial time, the phase selection signal selects a preset data signal, for example, a data signal phase <0>, which may be specifically set according to a specific structure of the circuit.
The respective circuits in the embodiments of the present invention are described below.
Fig. 3 is a schematic diagram of a counting circuit according to an embodiment of the invention. The counter circuit 1011 includes a first inverter INV1, m flip-flops, and an inverter combination 10111;
the input end of the first inverter INV1 is used for inputting a phase shift flag signal clk, and the output end of the first inverter INV1 is connected with the R end of each trigger DFF;
In each combination, the D end of the trigger DFF is connected with the output end of the inverter INV, and the Q end of the trigger DFF is connected with the input end of the inverter INV and is used for sequentially outputting m counting signals Qm-1.
In the first combination, the CK terminal of the flip-flop DFF is used for inputting the phase_mux signal, and in the other combinations, the CK terminal of the flip-flop DFF is connected to the output terminal of the inverter INV in the previous combination.
Fig. 4 is a schematic diagram of a count comparing circuit according to an embodiment of the invention. The count comparing circuit 1012 includes m exclusive or gates Y AND a first AND gate AND1;
For each exclusive-or gate, a first input end of the exclusive-or gate is used for inputting a counting signal Q, a second input end of the exclusive-or gate is used for inputting a shift number signal num corresponding to the counting signal, AND an output end of the exclusive-or gate is connected with one input end of a first AND gate AND 1;
the output terminal of the first AND gate AND1 is used for outputting a shift number identical signal num_same.
As shown in fig. 5, a schematic diagram of a shift signal generating sub-circuit according to an embodiment of the present invention is provided, where the shift signal generating sub-circuit 1013 includes tiehi gates, a first flip-flop DFF1, a second flip-flop DFF2, AND a second AND gate AND2;
the output end of the tiehi gate is connected with the D end of the first trigger DFF1 and is used for outputting a first level;
The R end of the first trigger DFF1 is used for inputting a signal num_same with the same shift number, the CK end of the first trigger DFF1 is used for inputting a phase shift mark signal clk, and the Q end of the first trigger DFF1 is connected with the D end of the second trigger DFF 2;
the R end of the second trigger DFF2 is used for inputting a reset signal rst, the CK end of the second trigger DFF2 is used for inputting a phase selection signal phase_mux, AND the Q end of the second trigger DFF2 is connected with the first input end of the second AND gate AND 2;
the second input terminal of the second AND gate AND2 is used for inputting the phase selection signal phase_mux, AND the output terminal of the second AND gate phase_mux is used for outputting the phase shift signal phase_shift.
As shown in fig. 6, a schematic diagram of a shift circuit according to an embodiment of the present invention includes a third flip-flop DFF3, (n-1) fourth flip-flops DFF4, a second inverter INV2, and a third inverter INV3;
For (n-1) fourth flip-flops DFF4, the D terminal of the first fourth flip-flop DFF4 is connected to the output terminal of the third inverter INV3 for outputting the first selection switch signal sel <0>, the Q terminal of the last fourth flip-flop DFF4 is connected to the input terminal of the second inverter INV2 for outputting the last selection switch signal sel < n-1>, among the other fourth flip-flops DFF4, the Q terminal of the preceding fourth flip-flop DFF4 is connected to the D terminal of the following fourth flip-flop DFF4 for sequentially outputting the selection switch signals sel <1>, sel <2>. Sel < n-2>, the R terminal of each fourth flip-flop DFF4 is for inputting the reset signal rst, and the CK terminal of each fourth flip-flop DFF4 is for inputting the phase shift signal se_shift;
The D end of the third flip-flop DFF3 is connected to the output end of the second inverter INV2, the Q end of the third flip-flop DFF3 is connected to the input end of the third inverter INV3, the R end of the third flip-flop DFF3 is used for inputting the reset signal rst, and the CK end of the third flip-flop DFF3 is used for inputting the phase shift signal phase_shift.
As shown in fig. 7, a schematic diagram of a phase selection circuit according to an embodiment of the present invention is provided, where the phase selection circuit 103 includes m fourth inverters INV4 and m switches K corresponding to each fourth inverter INV 4;
For each group of fourth inverter and switch, the input end of the fourth inverter INV4 is connected with the first control end of the switch K, and is used for inputting the phase selection switch signal sel, and the output end of the fourth inverter INV4 is connected with the second control end of the switch K;
The first terminal of the switch K is used for inputting the data signal phase corresponding to the phase selection switch signal sel, and the second terminal of the switch K is used for outputting the phase selection signal phase_mux.
In a specific implementation, the switch K may include a first switching tube M1 and a second switching tube M2;
the control end of the first switching tube M1 is used as a first control end of the switch K, the first end of the first switching tube M1 is connected with the first end of the second switching tube M2, and the second end of the first switching tube M1 is connected with the second end of the second switching tube M2;
The control terminal of the second switching tube M2 serves as a second control terminal of the switch K.
It should be noted that sel <0:m-1> in fig. 7 represents sel <0>, sel <1>, sel < 2..once again, sel < m-1>, that is, m inverters, and similarly includes m switches K.
For ease of understanding, the following description is given with specific examples.
The following describes an embodiment of the present invention by taking a 3-bit binary counter with a maximum number of mobile phases of 7 and a maximum number of selective phases of 8 (phase <0> -phase <7 >).
As shown in fig. 8, the counting circuit 1011 includes a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a fifth flip-flop DFF5, a sixth flip-flop DFF6, and a seventh flip-flop DFF7, wherein an input terminal of the fourth inverter INV4 is input with the phase shift flag signal clk, an output terminal of the fourth inverter INV4 is connected with an R terminal of the fifth flip-flop DFF5, an R terminal of the sixth flip-flop DFF6 and an R terminal of the seventh flip-flop DFF7, a D terminal of the fifth flip-flop DFF5 is connected with an output terminal of the fifth inverter INV5 and a CK terminal of the sixth flip-flop DFF6, a Q terminal of the fifth flip-flop DFF5 is connected with an input terminal of the fifth inverter INV5 for outputting the count signal Q0, and an output terminal of the seventh flip-flop DFF6 is connected with an output terminal of the seventh flip-flop DFF7, and an output terminal of the seventh flip-flop DFF7 is connected with an output terminal of the seventh flip-flop DFF7 for outputting the count signal Q0.
The counting circuit consists of four inverters and three D flip-flops, and each D flip-flop and one inverter are connected end to form a frequency division structure. The input signals of the counting circuit are a phase shift flag signal clk and a phase selection signal phase_mux, and the output signals are counting signals Q2, Q1 and Q0, wherein Q2 is the highest bit, and Q0 is the lowest bit.
The principle of a 3-bit binary counter is that the frequency is divided by two one, Q0 is half the frequency of phase_mux, Q1 is half the frequency of Q0, and Q2 is half the frequency of Q1. clkb is the inverse signal of clk and is connected to the reset terminals R of the three flip-flops. The reset terminals R of the three D flip-flops are all active high, and when the reset terminal R is 1, the Q output terminal of the D flip-flops is 0, i.e., when clk=1 (clkb=0), the phase_mux starts counting when it comes (high), and when clk=0 (clkb=1), q2=q1=q0=0, and the counting is stopped.
Fig. 9 is a schematic diagram of a counting and comparing circuit according to an embodiment of the invention. As shown in fig. 9, the count comparing circuit may include a first exclusive or gate Y1, a second exclusive or gate Y2, a third exclusive or gate Y3, AND a three-input AND gate AND3, wherein a first input terminal of the first exclusive or gate Y1 inputs the count signal Q0, a second input terminal of the first exclusive or gate Y1 inputs the shift count signal num <0>, an output terminal of the first exclusive or gate Y1 is connected to a first input terminal of the three-input AND gate AND3, a first input terminal of the second exclusive or gate Y2 inputs the count signal Q1, a second input terminal of the second exclusive or gate Y2 inputs the shift count signal num <1>, an output terminal of the third exclusive or gate Y2 is connected to a second input terminal of the three-input AND gate AND3, a first input terminal of the third exclusive or gate Y3 inputs the shift count signal num <2>, AND an output terminal of the third exclusive or gate Y3 is connected to a third input terminal of the three-input AND gate AND3, AND an output terminal of the three-input AND gate Y3 is used for outputting the same number of bits of shifts of signals num_same.
The counting comparison circuit consists of three two-input exclusive-or gates and a three-input AND gate, wherein the input signals of the counting comparison circuit are shift number signals num <2>, num <1>, num <0>, counting signals Q2, Q1 and Q0, and the output signals are shift number same signals num_same. When the level of any bit in the shift number signal and the level of any bit in the count signal are different, the values of the shift number signal and the count signal are not identical, and at the moment, the exclusive nor gate outputs 0, and the output signal num_same is also 0. Only when the shift count signal and the count signal are equal in each bit, i.e., num <2> =q2, num <1> =q1, num <0> =q0, which indicates that the number of periods of phase_mux reaches the target shift count at this time, the count signal and the shift count signal are the same in each bit level, and the three exclusive nor gate outputs are 1, the three-input nand gate output num_same is 1.
It should be noted that, the embodiment of the counting circuit and the counting comparison circuit provided by the invention can be used for expanding the bits of the counter and the counting comparison according to actual requirements or using other counting and counting comparison schemes with other structures.
In the embodiment of the invention, the shift signal generating circuit is used as an important intermediate link, the window opening mode of the shift signal generating circuit is very critical to the coordination of the counting circuit, the counting comparison circuit and the rear shift circuit, and the shift signal generating circuit determines the problem of when and how many phases to start shifting. The phase shift signal phase_shift is a key signal for entering a shift operation and phase selection.
As shown in fig. 10, a schematic diagram of a shift signal generating sub-circuit according to an embodiment of the present invention is shown in fig. 10, where the shift signal generating sub-circuit may include tiehi gates, eighth flip-flop DFF8, ninth flip-flop DFF9, AND two-input AND gate AND4, the output terminal of tiehi gates is connected to the D terminal of eighth flip-flop DFF8, the R terminal of eighth flip-flop DFF8 inputs the shift number same signal num_same, the CK terminal of eighth flip-flop DFF8 inputs the phase shift flag signal clk, the Q terminal of eighth flip-flop DFF8 is connected to the D terminal of nine flip-flop DFF9, the R terminal of nine flip-flop DFF9 inputs the reset signal rst, the CK terminal of nine flip-flop DFF9 inputs the phase selection signal phase_mux, the Q terminal of nine flip-flop DFF9 is connected to the first input terminal of two-input AND gate AND4, the second input terminal of two-input AND gate AND4 inputs the phase selection signal phase_mux, AND the output phase shift signal phase_phase phase shift of two-input AND 4.
The shift signal generating circuit is composed of two D flip-flops, one tiehi gate and one two-input AND gate. tiehi gate always outputs a high level tie_hi to the D input of the eighth flip-flop DFF 8. The reset end of the eighth flip-flop DFF8 is connected to the num_same signal output by the count comparing circuit, when num_same is 0, the shift reset signal shift_rst remains the same as the clk signal, when num_same is 1, shift_rst becomes 0, the eighth flip-flop DFF8 has the function of opening a window to allow shifting to occur, and the start and stop time of the window is from clk to clk from low level to high level until num_same signal is 1.
The D input end of the ninth trigger DFF9 is connected with a shift_rst, the reset end R of the ninth trigger DFF9 is connected with a reset signal rst of the whole circuit, the ck end of the ninth trigger DFF9 is connected with a phase selection signal phase_mux, the output Q end of the ninth trigger DFF9 outputs a mobile reset delay signal shift_ rstd, the function of the ninth trigger DFF9 is to beat the mobile reset signal shift_rst by using a phase_mux with higher frequency, a complete high-speed signal is exposed in a window opened by the mobile reset signal shift_rst, and the error of the number of mobile phases is avoided. Finally, the phase_mux and the shift_ rstd are subjected to logical AND operation to generate a phase shift signal phase_shift.
As shown in fig. 11, a schematic diagram of a shift circuit according to an embodiment of the present invention is provided, and as can be seen from fig. 11, the shift circuit may include a tenth flip-flop DFF10, an eleventh flip-flop DFF11, a twelfth flip-flop DFF12, a thirteenth flip-flop DFF13, a fourteenth flip-flop DFF14, a fifteenth flip-flop DFF15, a sixteenth flip-flop DFF16, a seventeenth flip-flop DFF17, an eighth inverter INV8, and a ninth inverter INV9, wherein the R terminal of each flip-flop inputs a reset signal rst, the CK terminal of each flip-flop inputs a phase shift signal phase_shift, the D terminal of the tenth flip-flop DFF10 is connected to the output terminal of the eighth inverter INV8, the Q terminal of the tenth flip-flop DFF10 is connected to the input terminal of the ninth inverter INV9, the output terminal of the ninth inverter INV9 is connected to the D terminal of the eleventh flip-flop f11, and the phase selection switch signal sel <0>, the Q terminal of the eleventh flip-flop DFF11 is connected to the D terminal of the twelfth flip-flop DFF12 for outputting the phase selection switch signal sel <1>, the Q terminal of the twelfth flip-flop DFF12 is connected to the D terminal of the thirteenth flip-flop DFF13 for outputting the phase selection switch signal sel <2>, the Q terminal of the thirteenth flip-flop DFF13 is connected to the D terminal of the fourteenth flip-flop DFF14 for outputting the phase selection switch signal sel <3>, the Q terminal of the fourteenth flip-flop DFF14 is connected to the D terminal of the fifteenth flip-flop DFF15 for outputting the phase selection switch signal sel <4>, the Q terminal of the fifteenth flip-flop DFF15 is connected to the D terminal of the sixteenth flip-flop DFF16 for outputting the phase selection switch signal sel <5>, the Q terminal of the sixteenth flip-flop DFF16 is connected to the D terminal of the seventeenth flip-flop DFF17 for outputting the phase selection switch signal sel <6>, the Q terminal of the seventeenth flip-flop DFF17 is connected to the input terminal of the eighth inverter 8, for outputting the phase selection switch signal sel <7>.
The shift circuit in fig. 11 is composed of eight D flip-flops and two inverters, which are connected end to form a closed loop, and cyclic shift is realized. The ck of all the D flip-flops is connected with the phase shift signal phase_shift generated by the shift signal generating circuit, the reset R of all the D flip-flops is connected with the reset signal rst of the whole circuit, and the output signal generated by the shift circuit is a phase selection switch signal sel<0>,sel<1>,sel<2>,sel<3>,sel<4>,sel<5>,sel<6>,sel<7>, for controlling the corresponding phase signal as an output result.
As shown in fig. 12, a schematic diagram of a phase selection circuit according to an embodiment of the present invention is shown, and as can be seen from fig. 12, the phase selection circuit may include eight inverters and eight switches, each switch may be composed of a pair of complementary mos transistor transmission gates, each pair of complementary mos transistor transmission gates is composed of a pmos transistor and an nmos transistor, and the purpose of the complementary switches is to prevent the gate voltage of a single mos transistor from being insufficient to the threshold voltage and being difficult to turn on.
The phase selection switch signals sel <0:7> become phase selection switch inverse signals selb <0:7> after passing through the inverter, sel <0:7> and selb <0:7> are opposite in high-low level, so that the mos transistors transmitting the switches can be controlled to be turned on and off simultaneously, namely when sel <0> =1, the rest sel=0, namely selb <0> =0, the rest selb=1, the pmos transistor and the nmos transistor of the first switch connected with sel <0> and selb <0> are turned on, the rest transmission gate switches are turned off, the phase selection signal phase_mux is output as a first phase data signal phase <0>, and when other phase selection switch signals are high-level 1, sel, selb and phase are in one-to-one correspondence. The input of each switch is connected with the data signals phase <0:7> of different phases, and the outputs of all the switches are connected together to be the phase selection signal phase_mux, and only one switch is conducted at a time, so that only one phase of data signal is selected.
This embodiment will be described with reference to the timing chart in fig. 13, and the circuit diagrams in fig. 8 to 12.
Fig. 13 is a timing chart of the signals corresponding to fig. 8 to 12. phase <0> to phase <7> are eight data signals with different phases, the reset signal rst of the whole circuit is low before the circuit works, namely the controlled D trigger works normally, the counter module starts counting when the phase shift flag signal clk is high, and the phase selection signal phase_mux selects the phase <0> signal at the initial moment. At time T1, the number of shift signals num <2> num <1> num <0> = 010, the first rising edge of the phase selection signal phase_mux comes, the count signal q2q1q0=001, the second rising edge of the phase selection signal phase_mux comes, the count signal q2q1q0=010, at this time q2=num <2>, q1=num <1>, q0=num <0>, and the number of shift signals num_same=1.
When clk is high, the shift reset signal shift_rst is high, when num_same=1, shift_rst is low, the shift reset delay signal shift_ rstd is a shift_rst delay result of one beat, the phase shift signal phase_shift generates 2 high levels at the time of T1 and the time of T2 respectively, after the shift module receives the two high levels, sel <1> becomes 1 at the time of T1, phase_mux selects phase <1> at the time of T2, sel <2> becomes 1 at the time of T2, phase_mux selects phase <2> at the time of T3, sel <2> keeps the high level unchanged, phase_mux keeps phase <2> output, and the next phase shift flag signal clk arrives. At time T4, the phase shift flag signal clk is at low level, and the counter module Q2Q1Q0 stops counting, so that power consumption can be saved. At time T5, the shift count signal num <2> num <1> num <0> =101, and num_same=1 when the count signal Q2Q1Q0 is counted up to 101, and phase_shift generates 5 high levels at times T5, T6, T7, T8, and T9, respectively. phase_mux selects phase <3> at T6, phase <4> at T7, phase <5> at T8, phase <6> at T9, phase <7> at T10, after which the phase select switch signal sel <7> remains at 1 and the phase_mux holds the phase <7> output. At time T11, the phase shift flag signal clk is low, and the counter block Q2Q1Q0 stops counting.
When the required shift number signal num <2> num <1> num <0> =000, the phase selection signal phase_mux keeps the previous phase output unchanged.
The shift circuit provided by the invention can be circularly shifted, in the embodiment, the phase selection signal is shifted to the data of the next phase each time, if the data of the last phase is required to be shifted, the shift times can be increased, for example, the output result is supposed to be shifted from phase <5> to phase <4>, and the shift time can be increased phase<5>→phase<6>→phase<7>→phase<0>→phase<1>→phase<2>→phase<3>→phase<4>.
The phase selector provided by the invention can achieve the function of continuously selecting any phase, namely, on the basis of the phase of ending the last clock period, the next output clock is increased by any phase, so that the purpose of accurately selecting the phase is achieved, the circuit structure is simple, and the implementation method is flexible.
Based on the same inventive concept, the embodiment of the present invention further provides a phase signal selection method, and the implementation of the method may refer to the implementation of the phase selector, and the repetition is not repeated.
As shown in fig. 14, a phase selection signal output method according to an embodiment of the present invention includes the following steps:
s1401, under the control of a phase shift flag signal, counting a phase selection signal to obtain a count signal, comparing the obtained count signal with a shift number signal, and outputting a phase shift signal for controlling phase shift according to a comparison result, the phase shift flag signal and the phase selection signal;
S1402, under the control of the phase shift signal, changing a phase selection switch signal;
s1403, selecting one data signal from n data signals having different phases as the phase selection signal according to the changed phase selection signal, and outputting the selected data signal, wherein n is a positive integer greater than 2.
Optionally, under the control of the phase shift flag signal, counting the phase selection signal to obtain a count signal, comparing the count signal with the shift number signal, and outputting a phase shift signal for controlling phase shift according to the comparison result, the phase shift flag signal and the phase selection signal, where the phase shift signal includes:
under the control of the phase shift flag signal, counting the phase selection signals and outputting m counting signals;
Comparing the m count signals with the m shift number signals, and outputting signals representing whether the m count signals and the m shift number signals are identical in shift number or not;
under the control of the phase shift number same signal, the phase shift flag signal and the reset signal, carrying out logic operation on the phase selection signal and outputting the phase shift signal;
wherein m is a positive integer greater than 2.
According to the phase selector and the phase selection signal output method provided by the embodiment of the invention, the phase selection signal is counted by the shift signal generating circuit under the control of the phase shift mark signal to obtain the count signal, the count signal is compared with the shift number signal, the phase shift signal for controlling the phase shift is output according to the comparison result, the phase shift mark signal and the phase selection signal, the phase selection switch signal is changed by the shift circuit under the control of the phase shift signal, and one data signal is selected as the phase selection signal from n data signals with different phases according to the changed phase selection signal and is output, wherein n is a positive integer greater than 2. The phase selector can generate a phase shift signal for controlling phase shift, under the control of the phase shift signal, the phase selection switch can be changed, so that data signals with different phases can be selected as phase selection signals, phase selection can be performed according to actual needs, multiple times of phase selection can be realized, the phase of the output phase selection signals is not fixed, and the flexibility and portability of the phase selector can be improved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (7)
1. A phase selector is characterized by comprising a shift signal generating circuit, a shift circuit and a phase selecting circuit;
The shift signal generating circuit is used for counting the phase selection signal under the control of the phase shift mark signal to obtain a count signal, comparing the obtained count signal with a shift number signal, and outputting a phase shift signal for controlling phase shift according to a comparison result, the phase shift mark signal and the phase selection signal;
The shift circuit is used for changing a phase selection switch signal under the control of the phase shift signal;
The phase selection circuit is used for selecting one data signal from n data signals with different phases as the phase selection signal according to the changed phase selection signal and outputting the data signal, wherein n is a positive integer;
The shift signal generation circuit comprises a counting circuit, a counting comparison circuit and a shift signal generation sub-circuit;
the counting circuit is used for counting the phase selection signals under the control of the phase movement mark signals and outputting m counting signals;
the counting comparison circuit is used for comparing m counting signals with m shifting number signals and outputting signals representing whether the m counting signals and the m shifting number signals are identical or not;
the shift signal generating sub-circuit is used for carrying out logic operation on the phase selection signal under the control of the signal with the same shift number and the phase shift mark signal, and outputting the phase shift signal;
wherein m is a positive integer greater than 2;
the shift signal generation sub-circuit comprises a voltage clamp high-level logic tiehi gate, a first trigger, a second trigger and a second AND gate;
the output end of the tiehi gate is connected with the D end of the first trigger and is used for outputting a first level;
The R end of the first trigger is used for inputting the signals with the same shifting number, the CK end of the first trigger is used for inputting the phase shifting mark signals, and the Q end of the first trigger is connected with the D end of the second trigger;
The R end of the second trigger is used for inputting a reset signal, the ck end of the second trigger is used for inputting the phase selection signal, and the Q end of the second trigger is connected with the first input end of the second AND gate;
the second input end of the second AND gate is used for inputting the phase selection signal, and the output end of the second AND gate is used for outputting the phase shift signal.
2. The phase selector of claim 1, wherein the counting circuit comprises a first inverter, m flip-flops, and an inverter combination;
the input end of the first inverter is used for inputting the phase shift flag signal, and the output end of the first inverter is connected with the R end of each trigger;
in each combination, the D end of the trigger is connected with the output end of the inverter, and the Q end of the trigger is connected with the input end of the inverter and is used for sequentially outputting m counting signals;
In the first combination, the CK terminal of the flip-flop is used for inputting the phase selection signal, and in other combinations, the CK terminal of the flip-flop is connected with the output terminal of the inverter in the last combination.
3. The phase selector of claim 1, wherein the count compare circuit comprises m exclusive-or gates and a first and gate;
For each exclusive or gate, a first input end of the exclusive or gate is used for inputting a counting signal, a second input end of the exclusive or gate is used for inputting a shift number signal corresponding to the counting signal, and an output end of the exclusive or gate is connected with one input end of the first and gate;
the output end of the first AND gate is used for outputting the signals with the same shifting number.
4. The phase selector of claim 1, wherein the shift circuit comprises a third flip-flop, n-1 fourth flip-flops, a second inverter, and a third inverter;
for n-1 fourth flip-flops, the D end of the first fourth flip-flop is connected with the output end of the third inverter for outputting a first selection switch signal, the Q end of the last fourth flip-flop is connected with the input end of the second inverter for outputting a last selection switch signal, the Q end of the previous fourth flip-flop is connected with the D end of the next fourth flip-flop for sequentially outputting a selection switch signal, the R end of each fourth flip-flop is used for inputting a reset signal, and the CK end of each fourth flip-flop is used for inputting the phase shift signal;
the D end of the third trigger is connected with the output end of the second inverter, the Q end of the third trigger is connected with the input end of the third inverter, the R end of the third trigger is used for inputting the reset signal, and the CK end of the third trigger is used for inputting the phase shift signal.
5. The phase selector as set forth in claim 1, wherein said phase selection circuit includes m fourth inverters and m switches corresponding to each fourth inverter;
for each group of fourth inverter and switch, the input end of the fourth inverter is connected with the first control end of the switch and is used for inputting a phase selection switch signal, and the output end of the fourth inverter is connected with the second control end of the switch;
The first end of the switch is used for inputting a data signal corresponding to the phase selection switch signal, and the second end of the switch is used for outputting the phase selection signal.
6. The phase selector of claim 5, wherein the switch comprises a first switching tube and a second switching tube;
The control end of the first switching tube is used as a first control end of the switch, the first end of the first switching tube is connected with the first end of the second switching tube, and the second end of the first switching tube is connected with the second end of the second switching tube;
the control end of the second switching tube is used as a second control end of the switch.
7. A phase selection signal output method, the method comprising:
under the control of the phase shift flag signal, counting the phase selection signal to obtain a count signal, comparing the obtained count signal with a shift number signal, and outputting a phase shift signal for controlling phase shift according to a comparison result, the phase shift flag signal and the phase selection signal;
under the control of the phase shift signal, changing a phase selection switch signal;
Selecting one data signal from n data signals with different phases as the phase selection signal according to the changed phase selection signal, and outputting the data signal, wherein n is a positive integer greater than 2;
Under the control of the phase shift flag signal, counting the phase selection signal to obtain a count signal, comparing the obtained count signal with a shift number signal, and outputting a phase shift signal for controlling phase shift according to a comparison result, the phase shift flag signal and the phase selection signal, wherein the phase shift signal comprises:
under the control of the phase shift flag signal, counting the phase selection signals and outputting m counting signals;
Comparing the m count signals with the m shift number signals, and outputting signals representing whether the m count signals and the m shift number signals are identical in shift number or not;
under the control of the phase shift number same signal, the phase shift flag signal and the reset signal, carrying out logic operation on the phase selection signal and outputting the phase shift signal;
wherein m is a positive integer greater than 2;
And under the control of the phase shift number same signal, the phase shift flag signal and the reset signal, performing logic operation on the phase selection signal, and outputting the phase shift signal, wherein the logic operation comprises the following steps:
the phase selection signal is subjected to logic operation by a shift signal generation sub-circuit under the control of the same shift number signal, the phase shift flag signal and the reset signal, and the phase shift signal is output;
the shift signal generation sub-circuit comprises a voltage clamp high-level logic tiehi gate, a first trigger, a second trigger and a second AND gate;
the output end of the tiehi gate is connected with the D end of the first trigger and is used for outputting a first level;
The R end of the first trigger is used for inputting the signals with the same shifting number, the CK end of the first trigger is used for inputting the phase shifting mark signals, and the Q end of the first trigger is connected with the D end of the second trigger;
The R end of the second trigger is used for inputting a reset signal, the ck end of the second trigger is used for inputting the phase selection signal, and the Q end of the second trigger is connected with the first input end of the second AND gate;
the second input end of the second AND gate is used for inputting the phase selection signal, and the output end of the second AND gate is used for outputting the phase shift signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111025426.9A CN113890505B (en) | 2021-09-02 | 2021-09-02 | Phase selector and phase selection signal output method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111025426.9A CN113890505B (en) | 2021-09-02 | 2021-09-02 | Phase selector and phase selection signal output method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113890505A CN113890505A (en) | 2022-01-04 |
| CN113890505B true CN113890505B (en) | 2025-08-08 |
Family
ID=79012075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111025426.9A Active CN113890505B (en) | 2021-09-02 | 2021-09-02 | Phase selector and phase selection signal output method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113890505B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106842247A (en) * | 2015-12-04 | 2017-06-13 | 航天恒星科技有限公司 | The L2C signal creating methods and device of a kind of GPS |
| CN111656447A (en) * | 2018-04-09 | 2020-09-11 | 美光科技公司 | Techniques for clock signal jitter generation |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6044122A (en) * | 1997-01-23 | 2000-03-28 | Ericsson, Inc. | Digital phase acquisition with delay locked loop |
| JP3671782B2 (en) * | 1999-12-10 | 2005-07-13 | 富士通株式会社 | Signal phase adjustment circuit |
| KR100656956B1 (en) * | 2006-01-04 | 2006-12-14 | 삼성전자주식회사 | Fast passband phase modulation device and method |
| JP2015103895A (en) * | 2013-11-22 | 2015-06-04 | 株式会社リコー | Spread spectrum clock generation circuit |
| WO2017066322A2 (en) * | 2015-10-14 | 2017-04-20 | Witricity Corporation | Phase and amplitude detection in wireless energy transfer systems |
| CN106130543A (en) * | 2016-06-21 | 2016-11-16 | 中国电子科技集团公司第五十八研究所 | A kind of high-resolution clock phase shift framework and the implementation method of algorithm |
| KR102701819B1 (en) * | 2019-06-10 | 2024-09-03 | 에스케이하이닉스 주식회사 | Read clock generation circuit and data processing circuit including the same |
| CN112953472B (en) * | 2021-02-05 | 2022-07-22 | 青岛信芯微电子科技股份有限公司 | Data bit conversion circuit |
-
2021
- 2021-09-02 CN CN202111025426.9A patent/CN113890505B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106842247A (en) * | 2015-12-04 | 2017-06-13 | 航天恒星科技有限公司 | The L2C signal creating methods and device of a kind of GPS |
| CN111656447A (en) * | 2018-04-09 | 2020-09-11 | 美光科技公司 | Techniques for clock signal jitter generation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113890505A (en) | 2022-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6093265B2 (en) | Semiconductor device | |
| US4935944A (en) | Frequency divider circuit with integer and non-integer divisors | |
| JP4780144B2 (en) | Frequency divider circuit | |
| US7822168B2 (en) | Frequency divider circuit | |
| US20050058236A1 (en) | Multi-modulus programmable frequency divider | |
| JP2018112861A (en) | Random number generator, integrated circuit | |
| CN116566383B (en) | Synchronous five-frequency dividing circuit and five-frequency dividing signal generation method | |
| KR100232017B1 (en) | Up/down conversion counter | |
| JP5465636B2 (en) | Random number generator | |
| CN106374914B (en) | A kind of programmable frequency divider | |
| US6404839B1 (en) | Selectable clock divider circuit with a 50% duty cycle clock | |
| CN113890505B (en) | Phase selector and phase selection signal output method | |
| US6686780B2 (en) | Frequency divider with selectable division factor | |
| US20080024184A1 (en) | Flip-flop having improved set-up time and method used with | |
| CN220139537U (en) | Frequency dividing circuit, frequency divider and frequency dividing system | |
| US7521972B2 (en) | Fifty percent duty cycle clock divider circuit and method | |
| CN108777575B (en) | Frequency divider | |
| KR20100101448A (en) | Clock dividing cicuit | |
| US10749530B1 (en) | Programmable divider with glitch-free load circuit | |
| JPH04295280A (en) | Pwm signal arithmetic circuit | |
| GB2403082A (en) | Arrangement and method for a digital delay line | |
| CN117176139B (en) | Frequency divider construction method and frequency divider with frequency division ratio of 2 plus or minus 1 to power N | |
| CN117176140B (en) | Synchronous seven-frequency dividing circuit and seven-frequency dividing signal generation method | |
| JP2010124228A (en) | Frequency division circuit and electronic apparatus | |
| US20240072807A1 (en) | Frequency divider for non-overlapping clock signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |