CN113889413B - Ring gate device, source-drain preparation method thereof, device preparation method and electronic equipment - Google Patents

Abstract

The invention provides a ring gate device, a source-drain preparation method thereof, a device preparation method and electronic equipment, wherein the source-drain preparation method of the ring gate device comprises the following steps: forming a fin on a substrate and a dummy gate crossing the fin, wherein the fin comprises a fin channel layer and a fin sacrificial layer which are alternately stacked; the fin channel layer comprises a first channel layer part positioned on the inner side of the dummy gate and a second channel layer part not positioned on the inner side of the dummy gate; releasing the fin sacrificial layer; respectively extending silicon on two sides of the fin along the channel direction based on the second channel layer part to form a silicon material layer, and taking the first channel layer part as a channel layer of the gate-all-around device; the silicon material layer is connected with all the channel layers; etching the silicon material layer based on the required source drain region; and based on the residual silicon material layer, extending the germanium-silicon layer, and forming a source electrode and a drain electrode on the germanium-silicon layer.

Description

Gate-all-around device and source-drain preparation method thereof, device preparation method, and electronic equipment

technical field

The present invention relates to the field of semiconductors, and in particular, to a gate-all-around device and a source-drain preparation method thereof, a device preparation method, and an electronic device.

Background technique

A transistor device can be understood as a switch structure made of semiconductor materials, one of which is a gate-all-around device, which can also be understood as a GAA device and a GAAFET. Among them, the full name of GAA is: Gate-All-Around, which means a surround gate technology.

In the prior art, in the scheme of SiGe source-drain epitaxy on the GAAFET device, as shown in FIG. 1 , the source-drain SiGe-Si bulk layer is epitaxially grown using the isolated silicon material extending from the side of the channel layer as the seed layer. Furthermore, the epitaxy starts from multiple isolated surfaces, and the epitaxial SiGe crystal planes between adjacent gates overlap, which is easy to form stacking faults, resulting in stress relaxation. If it results in complete relaxation, it cannot provide the channel. enough stress.

SUMMARY OF THE INVENTION

The present invention provides a gate-all-around device, a source-drain preparation method, a device preparation method, and an electronic device to solve the problem of stress relaxation caused by stacking faults.

According to a first aspect of the present invention, there is provided a source-drain preparation method of a gate-all-around device, comprising:

A fin on the substrate is formed, and a dummy gate spanning the fin is formed, the fin includes a fin channel layer and a fin sacrificial layer alternately stacked; the fin channel layer includes a fin channel layer in the dummy a first channel layer portion inside the gate, and a second channel layer portion not inside the dummy gate;

releasing the fin sacrificial layer;

On both sides of the fin along the channel direction, based on the second channel layer portion, epitaxial silicon is respectively formed to form a silicon material layer, and the first channel layer portion is used as the channel layer of the gate-all-around device ; The silicon material layer connects all channel layers;

Etching the silicon material layer based on the required source and drain regions;

Based on the remaining silicon material layer, a silicon germanium bulk layer is epitaxially formed, and a source electrode and a drain electrode are formed on the silicon germanium bulk layer.

Optionally, before releasing the fin sacrificial layer, the method further includes:

The fin is etched and thinned, and the fin channel layer and the fin sacrificial layer in the fin are both thinned;

After releasing the fin sacrificial layer, it also includes:

The released and etched space in the dummy gate forms an inner isolation layer.

Optionally, etching and thinning the fins includes:

The first side and the second side of the fin are respectively etched, and the first side and the second side are distributed on both sides of the fin along a specified direction, and the specified direction is perpendicular to the specified direction. the channel direction.

Optionally, the first side and the second side of the fin are respectively etched to thin the fin, including;

The first side and the second side of the fin are respectively etched in a selective etching manner.

Optionally, based on the required source and drain regions, the silicon material layer is etched, including:

A groove body is etched from the silicon germanium material layer, the height of the groove bottom of the groove body is matched with the height of the bottommost channel layer in the fin, and the groove body and the channel layer are separated by Silicon material is separated.

Optionally, the width of the silicon material in the groove bottom of the groove body along the specified direction matches the width of the fin that is not thinned.

Optionally, the material of the sacrificial fin layer is silicon germanium.

According to a second aspect of the present invention, there is provided a device fabrication method of a gate-all-around device, including: the source-drain fabrication method involved in the first aspect and its optional solutions.

According to a third aspect of the present invention, a gate-all-around device is provided, which is fabricated by using the device fabrication method involved in the second aspect and its optional solutions.

According to a fourth aspect of the present invention, an electronic device is provided, including the gate-all-around device involved in the third aspect and its optional solutions.

In the gate-all-around device, the source-drain preparation method, the device preparation method, and the electronic device provided by the present invention, after the channel layer is released, a part of the epitaxial silicon material layer is based on the second channel layer, so that high quality can be obtained in the source-drain region. of Si crystals. At this time, based on the epitaxial silicon material layer, the source and drain regions have been converted into complete and continuous Si. At this time, the S/D region etching is repeated, and the epitaxy of germanium and silicon can be completed on the basis of continuous Si to obtain high-quality silicon. SiGe bulk layer. Furthermore, the present invention can effectively solve the problem of stress relaxation caused by the epitaxy of the source-drain SiGe bulk layer merging between the dummy gates.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

Fig. 1 is a schematic diagram of the principle of the silicon germanium body layer of the epitaxial source and drain in a solution different from one of the present invention;

FIG. 2 is a schematic schematic diagram of the silicon germanium body layer of the epitaxial source and drain in a scheme different from that of the present invention. II;

FIG. 3 is a schematic diagram of the principle of the silicon germanium body layer of the epitaxial source and drain in a scheme different from that of the present invention. III;

FIG. 4 is a schematic flow chart 1 of a source-drain fabrication method of a gate-all-around device according to an embodiment of the present invention;

FIG. 5 is a second schematic flowchart of a source-drain fabrication method of a gate-all-around device according to an embodiment of the present invention;

FIG. 6 is a schematic view of the structure from a channel direction viewing angle after step S11 in an embodiment of the present invention;

7 is a schematic diagram of a cross-sectional structure under a viewing angle of a specified direction after step S11 in an embodiment of the present invention;

FIG. 8 is a schematic view of the structure from a channel direction viewing angle after step S16 in an embodiment of the present invention;

FIG. 9 is a schematic view of the structure from a channel direction viewing angle after step S12 in an embodiment of the present invention;

10 is a schematic diagram of a cross-sectional structure at a viewing angle in a specified direction after step S12 in an embodiment of the present invention;

11 is a schematic structural diagram of the view from the channel direction after step S17 in an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of the view from the channel direction after step S13 in an embodiment of the present invention;

Fig. 13 is the cross-sectional structure schematic diagram under the specified direction viewing angle after step S13 in one embodiment of the present invention;

Fig. 14 is the cross-sectional structure schematic diagram under the specified direction viewing angle after step S14 in one embodiment of the present invention;

15 is a schematic cross-sectional view of the structure after the epitaxial silicon germanium bulk layer in step S15 in an embodiment of the present invention at a viewing angle in a specified direction;

FIG. 16 is a schematic view of the structure from the perspective of the channel direction after the epitaxial silicon germanium bulk layer in step S15 in accordance with an embodiment of the present invention.

Description of reference numbers:

201-fin sacrificial layer;

202-fin channel layer;

203 - oxide layer;

204 - bottom layer silicon;

205 - dummy gate;

206 - isolation layer;

207-silicon material layer;

208-silicon germanium bulk layer;

209 - tank body;

210-channel layer;

211 - Silicon material at the bottom of the groove.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

In the description of the present specification, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "upper end", "lower end", "lower surface", "upper surface", etc. are based on the accompanying drawings The orientation or positional relationship shown is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a reference to the present invention. limits.

In the description of the specification of the present invention, the terms "first" and "second" are only used for the purpose of description, and should not be understood as indicating or implying the relative importance or the quantity of the indicated technical features. Thus, a feature defined as "first", "second" may expressly or implicitly include one or more of that feature.

In the description of the present invention, "plurality" means a plurality, such as two, three, four, etc., unless otherwise expressly and specifically defined.

In the description of the specification of the present invention, unless otherwise expressly specified and limited, the term "connection" and other terms should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integrated; it may be a mechanical connection , it can also be an electrical connection or can communicate with each other; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the internal communication between two elements or the interaction relationship between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

The technical solutions of the present invention will be described in detail below with specific examples. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

The SiGe source-drain (ie SiGe bulk layer of source and drain) selective epitaxy technology can provide effective compressive stress for the channel, thereby improving the mobility of holes in the PMOS device, so as to match the mobility of electrons and improve the overall performance. In advanced node GAAFET devices, channel stress technology based on SiGe source-drain (ie, silicon germanium bulk layer at source and drain) is indispensable for device performance improvement.

In order to facilitate the description of the gate-all-around device, the source-drain preparation method, the device preparation method, and the electronic device provided by the embodiments of the present invention, the following will be combined with FIG. 1 to FIG. The principle of the body layer is described.

Referring to FIGS. 1 to 3 , the SiGe source-drain (ie, the silicon germanium bulk layer 302 of the source and drain) on the gate-all-around device (ie, the GAAFET device) epitaxially starts from a plurality of isolated surfaces (the isolated surface refers to the channel layer draining from the source The structure of epitaxial silicon germanium material on the isolated surface can be as shown in FIG. 1 . At this time, part of the epitaxially grown silicon germanium extends outward from the isolated surfaces 301 , and the structure after further epitaxy can be as shown in FIG. 2 . As shown, the formed structure of the source and drain SiGe body layers 302 can be, for example, as shown in FIG. 3 , in which the epitaxial SiGe crystal planes between adjacent gates overlap, and stacking faults are easily formed to cause stress relaxation.

Specifically, before the epitaxial SiGe source and drain (ie, the SiGe bulk layer of the source and drain), the structure has a plurality of mutually isolated SiGe epitaxial starting surfaces (ie, isolated surfaces 301 ), and as the epitaxial thickness increases, these epitaxial starting surfaces The SiGe materials grown on the initial surface merge with each other, and may form a large number of stacking faults, resulting in stress relaxation of the SiGe source and drain (ie, the silicon germanium bulk layer of the source and drain), which can lead to complete relaxation in the worst case, so that it is impossible to give the grooves of silicon. provide sufficient stress.

In order to solve the above problems, in the embodiment of the present invention, please refer to FIG. 4 , the source-drain preparation method of the gate-all-around device includes:

S11: forming fins on the substrate, and dummy gates spanning the fins;

The structure after step S11 can be, for example, as shown in FIG. 6 and FIG. 7 ;

S12: releasing the fin sacrificial layer;

The structure after step S12 can be as shown in FIG. 9 ;

S13: On both sides of the fin along the channel direction, based on the second channel layer portion, epitaxial silicon is respectively formed to form a silicon material layer, and the first channel layer portion is used as the trench of the gate-all-around device Dao layer;

At this time, the silicon material layer can be understood as including epitaxial silicon and silicon of the second channel layer portion, and the silicon material layer is connected to all the channel layers (ie, all the first channel layer portions), Thus, complete and continuous silicon can be obtained;

The structure after step S13 can be, for example, shown in FIG. 12 and FIG. 13 ;

S14: Etch the silicon material layer based on the required source and drain regions;

The structure after step S14 can be as shown in FIG. 14 ;

S15: based on the remaining silicon material layer, epitaxially form a silicon germanium bulk layer, and form a source electrode and a drain electrode on the silicon germanium bulk layer;

The structure after epitaxially forming the silicon germanium bulk layer in step S15 may be shown in, for example, FIG. 15 and FIG. 16 .

During or before step S11, a preparatory channel layer (such as a silicon layer) and a preparatory sacrificial layer (such as a silicon germanium layer) may be epitaxially formed on the silicon substrate, and then the epitaxial preparatory channel layer, preparatory sacrificial layer, The silicon substrate is etched, and an oxide layer (such as the oxide layer 203 shown in FIG. 6 to FIG. 16) can also be prepared in the etched area. The silicon between the oxide layers can be understood as the bottom layer silicon 204, the bottom layer silicon 204 and the The remaining silicon germanium layer, the silicon layer and the silicon substrate portion on the upper side of the oxide layer 203 can be regarded as fins. Further, the substrate can be understood as including the underlying silicon 204 and the oxide layer 203.

The oxide layer 203 can also be described as an isolation oxide layer and an STI oxide layer, where the STI is specifically: Shallow Trench Isolation, and further, can be understood as shallow trench isolation. The material of the oxide layer 203 can be, for example, SiO ₂ , but is not limited thereto.

The fins may include alternately stacked fin channel layers 202 and fin sacrificial layers 201; in the illustrated example, only the fin channel layer 202 and the fin sacrificial layer 201 are shown in the fins, and in other For example, the structure of the fin may not be limited to the above fin channel layer 202 and fin sacrificial layer 201 . The thickness of each fin sacrificial layer can be the same or different, and the thickness of each fin channel layer can be the same or different. In other examples, the materials of the fin sacrificial layer and the fin channel layer can also be arbitrarily changed according to requirements, and at the same time, the thickness can also be arbitrarily changed according to requirements.

After the fins are formed, a dummy gate can be formed outside the fins and connected to the substrate (eg, connected to the oxide layer 203 ). The dummy gate can include, for example, a metal gate material used as a dummy gate, and can also include other A layer of material (eg, may include a multi-layer stack). In some solutions, the dummy gates spanning outside the fins may be distributed in sequence along a specified direction, and the specified direction may be understood as being perpendicular to the direction of the channel.

The left-right direction shown in FIGS. 7 , 10 , 13 , 14 , and 15 is the channel direction mentioned above, and the left-right direction shown in FIGS. 6 , 8 , 9 , 11 , 12 , and 16 That is, the specified direction perpendicular to the channel direction mentioned above.

The fin channel layer 202 includes a first channel layer portion inside the dummy gate, and a second channel layer portion not inside the dummy gate.

In a specific example, the material of the fin channel layer 202 is silicon (Si), and the material of the fin sacrificial layer 201 is silicon germanium (SiGe).

In one embodiment, the fins can be etched and thinned before step S12, and further, after the channel is released, nanowires for epitaxial silicon can be formed in the channel layer, which can be used as a template to perform the steps Epitaxy of Si in S13. In other parts of the examples, the scheme of not thinning or thinning in other ways is not excluded.

Further, please refer to FIG. 5, before step 12, may further include:

S16: the fin is etched and thinned, and the fin channel layer and the fin sacrificial layer in the fin are both thinned;

After step S12, it may further include:

S17 : forming an inner isolation layer in the space that is released and etched in the dummy gate.

In a specific solution, step S16 may specifically include:

The first side and the second side of the fin are respectively etched, and the first side and the second side finger are distributed on both sides of the fin along a specified direction.

The structure after step S16 can be, for example, as shown in FIG. 8, wherein the first side and the second side can be, for example, the left and right sides shown in FIG. Including the part not wrapped by the dummy gate, and further, two parts of the gap space can be formed between the fin and the dummy gate, and the two parts of the gap space are distributed on both sides of the fin along the specified direction (as shown in FIG. 8 ) Thinning the gap space on the left and right sides of the rear fin 8).

In an example of step S16, the first side and the second side of the fin may be etched separately in a selective etching manner. In other examples, no matter what manner is used to perform the etching, it does not deviate from the scope of the embodiments of the present invention.

The structure after step S12 can be, for example, as shown in FIG. 9 , wherein the process of releasing the sacrificial layer can be realized by referring to any method in the art, for example, silicon germanium can be removed by selective etching, thereby realizing the release of the sacrificial layer. After release, the fin channel layer can form nanowires.

At the same time, after the release, the fin sacrificial layer portion 2 forms a space, and further, a certain amount of space can be formed between the remaining fin channel layer and the dummy gate, and between the remaining fin channel layer 202 inside the dummy gate 205 For the space (the blank part near the fin channel layer 202 as shown in FIG. 9 ), in step S17 , the space can be filled with the isolation layer 206 .

The isolation layer 206 can be characterized as an Inner Spacer, through which the isolation layer can provide protection for subsequent etching and epitaxy steps, avoid the etching process from affecting the corresponding channel layer and sacrificial layer, and also ensure the device Electrical isolation between gate and source-drain.

The structure after step S13 can be, for example, as shown in FIGS. 12 and 13 , wherein the silicon material layer 207 can be, for example, the silicon material layer 207 on the left as shown in FIG. 13 and the silicon material layer 207 on the right as shown in FIG. 13 , The silicon material layer 207 is connected to all the channel layers 210 to form a complete continuous silicon.

In one embodiment, step S14 may specifically include: etching a groove body in the silicon germanium material layer.

The groove body 209 formed by etching can be, for example, the groove body 209 on the left and right sides shown in FIG. 14 . During etching, part of the silicon can be retained outside the fin, and further, the groove body 209 and the channel layer can be formed. The parts 210 are separated by the remaining silicon material, and the height of the part of the remaining silicon material is higher than that of the uppermost channel layer 210 . During etching, a part of silicon can also be retained on the substrate (eg, the oxide layer 203 ), and the retained thickness can be changed according to requirements. The height of the bottom channel layer 210 can be, for example, the height L shown in FIG. 10 and FIG. 14 , that is, the thickness of the silicon material 211 at the bottom of the trench matches the thickness of the bottommost channel layer 210 .

In a further example, taking FIG. 16 as an example, the width of the silicon material 211 at the bottom of the groove body along the specified direction matches the width of the fin that is not thinned (that is, matches the width of the underlying silicon 204 in the substrate). width).

The silicon germanium bulk layer 208 formed in step S15 can be, for example, as shown in FIG. 16 and FIG. 15 , wherein the silicon germanium bulk layer 208 is formed, and the source electrode and the drain electrode are formed on the silicon germanium bulk layer 208;

The epitaxy of the silicon germanium body layer 208 can be understood as being realized by an EPI (ie Epitaxy) process. The epitaxial silicon germanium body layer 208 may include three connection corners, two of which are opposite along a specified direction, and the other connection corner faces the substrate. ; Further, the silicon germanium bulk layer forming the three connection corners can be understood to be diamond-shaped or rhombus-shaped. It can be seen that in the specific solution of the present invention, by introducing high selectivity SiGe etching technology during source/drain (S/D) etching, silicon nanosheets (Nanosheet) are left in the S/D region, and thus Si epitaxy was performed as a template. High-quality Si crystals are obtained from the S/D region. At this point the S/D has been converted to full continuous Si. At this time, the S/D region etching is repeated to complete the epitaxy of SiGe on the basis of continuous Si, and high-quality SiGe can be obtained.

An embodiment of the present invention also provides a device fabrication method for a gate-all-around device, including: the source-drain fabrication method involved in the above optional solution.

The embodiment of the present invention also provides a gate-all-around device, which is prepared by using the device preparation method involved in the above optional solution.

An embodiment of the present invention also provides an electronic device, including the gate-all-around device involved in the above optional solution.

In the description of this specification, reference to the terms "an embodiment", "an example", "a specific implementation process", "an example", etc. refers to the specific features described in conjunction with the embodiment or example, A structure, material, or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (10)

1. a source-drain preparation method of a gate-all-around device, characterized in that, comprising: A fin on the substrate is formed, and a dummy gate spanning the fin is formed, the fin includes a fin channel layer and a fin sacrificial layer alternately stacked; the fin channel layer includes a fin channel layer in the dummy a first channel layer portion inside the gate, and a second channel layer portion not inside the dummy gate; releasing the fin sacrificial layer; On both sides of the fin along the channel direction, based on the second channel layer portion, epitaxial silicon is respectively formed to form a silicon material layer, and the first channel layer portion is used as the channel layer of the gate-all-around device ; The silicon material layer connects all channel layers; Based on the required source and drain regions, the silicon material layer is etched, and the etched silicon material layer is connected to all the channel layers; based on the remaining continuous silicon material layer, the epitaxial silicon germanium body layer is formed, and the etched silicon material layer is The silicon germanium bulk layer forms source and drain electrodes. 2 . The source-drain preparation method of a gate-all-around device according to claim 1 , wherein before releasing the fin sacrificial layer, the method further comprises: 3 . etching and thinning the fin, so that both the fin channel layer and the fin sacrificial layer in the fin are thinned; After releasing the fin sacrificial layer, it also includes: The released and etched space in the dummy gate forms an inner isolation layer. 3. The source-drain preparation method of a gate-all-around device according to claim 2, wherein etching and thinning the fins comprises: The first side and the second side of the fin are respectively etched, and the first side and the second side are distributed on both sides of the fin along a specified direction, and the specified direction is perpendicular to the specified direction. the channel direction. 4 . The source-drain preparation method of a gate-all-around device according to claim 3 , wherein the first side and the second side of the fin are respectively etched to reduce the thickness of the fin, comprising: 5 . The first side and the second side of the fin are respectively etched in a selective etching manner. 5. The source-drain preparation method of a gate-all-around device according to any one of claims 1 to 4, wherein, based on the required source and drain regions, the silicon material layer is etched, comprising: A groove body is etched from the silicon germanium material layer, the height of the groove bottom of the groove body matches the height of the bottommost channel layer, and the groove body and the channel layer are separated by silicon material. 6 . The source-drain fabrication method of a gate-all-around device according to claim 5 , wherein the width of the silicon material at the bottom of the groove body along a specified direction matches the width of the fin that is not thinned. 7 . 7 . The source-drain preparation method of a gate-all-around device according to claim 1 , wherein the material of the sacrificial fin layer is silicon germanium. 8 . 8 . A device fabrication method for a gate-all-around device, comprising: the source-drain fabrication method according to any one of claims 1 to 7 . 9 . A gate-all-around device, characterized in that, it is prepared by the device preparation method of claim 8 . 10 . An electronic device, comprising the gate-all-around device of claim 9 . 11 .

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