CN113885385B

CN113885385B - Distributed control system of power electronic device

Info

Publication number: CN113885385B
Application number: CN202111173987.3A
Authority: CN
Inventors: 刘苍; 孟庆云; 胡安琪; 霍冬阳
Original assignee: Naval University of Engineering PLA
Current assignee: Naval University of Engineering PLA
Priority date: 2021-10-09
Filing date: 2021-10-09
Publication date: 2024-07-23
Anticipated expiration: 2041-10-09
Also published as: CN113885385A

Abstract

The invention provides a distributed control system of a power electronic device, which comprises a master controller and a plurality of slave controllers, wherein the master controller is connected with the slave controllers; the main controller comprises a DSP and an FPGA; the DSP is used for executing a core control algorithm and sending instruction data to the FPGA according to the control algorithm result; the FPGA comprises a plurality of controller modules which are in one-to-one correspondence with a plurality of slave controllers and are communicated with each other; any one slave controller comprises a plurality of different functional modules, and the corresponding controller module of the slave controller is correspondingly provided with the corresponding functional module of the slave controller; the controller module operates the received instruction data from the DSP based on the configured functional module and outputs the operation result to the functional module of the corresponding slave controller. The invention is beneficial to popularization and application of the distributed ideas in the power electronic device.

Description

Distributed control system of power electronic device

Technical Field

The invention belongs to the technical field of power electronics, and particularly relates to a distributed control system of a power electronic device.

Background

Distributed computing has grown in popularity due to the huge power consumption and cost of centralized computing. With the breakthrough development of communication and network technology, distributed decentralization shadows can be seen in various industries, and the distributed decentralization idea accords with the great trend of the current technological development. Distributed control also has application prospects in high-power complex power electronic devices. With the continuous development of power electronics toward intelligent and data-driven power electronics, more and more data interfaces are introduced; the number and types of interfaces of the main controller for centralized control of the large-capacity power electronic device are numerous, and the difficulty and cost of high-reliability operation and automatic production are increased. Compared with centralized control, the introduction of the distributed control idea greatly increases the software development workload in the power electronic control device, and increases the development period and development difficulty of the power electronic device.

Disclosure of Invention

The invention aims to solve the defects in the background technology, and provides a distributed control system of a power electronic device, which is used for decoupling the coupling relation between controllers and the coupling relation between modules, reducing the development difficulty and the development cost of embedded software of the power electronic device adopting distributed control, and being more beneficial to popularization and application of a distributed idea in the power electronic device.

The technical scheme adopted by the invention is as follows: a distributed control system of a power electronic device comprises a master controller and a plurality of slave controllers; the main controller comprises a DSP and an FPGA; the DSP is used for executing a core control algorithm and sending instruction data to the FPGA according to the control algorithm result; the FPGA comprises a plurality of controller modules which are in one-to-one correspondence with a plurality of slave controllers and are communicated with each other; any one slave controller comprises a plurality of different functional modules, and the corresponding controller module of the slave controller is correspondingly provided with the corresponding functional module of the slave controller; the FPGA performs operation on the received instruction data from the DSP and outputs an operation result to a corresponding functional module of the slave controller based on the configured functional module; the slave controller executes corresponding operation of the operation result of the received instruction data based on the configured functional module and sends feedback data to the functional module of the corresponding controller module; the FPGA receives feedback data based on the configured functional module, performs operation, and outputs an operation result to the DSP.

In the technical scheme, the DSP and the FPGA complete data interaction through an EMIF bus; packaging the EMIF bus modules of the DSP and the FPGA; the FPGA comprises an EMIF protocol conversion module and an algorithm logic module; the EMIF protocol conversion module receives EMIF end data of instruction data through the EMIF bus module, and converts the EMIF end data into a register value serving as input of the algorithm logic module; the EMIF protocol conversion module receives the operation result of the algorithm logic module, converts the received operation result into EMIF end data and sends the EMIF end data to the DSP through the EMIF bus module.

In the above technical solution, the functional module of the controller module adopts a register file; the function module of the controller module is used as input or output of the algorithm logic module, and the register names of the function modules of the corresponding controller modules are defined according to the corresponding function modules of the slave controllers;

The algorithm logic module executes built-in algorithm logic based on the received EMIF end data or feedback data uploaded by the slave controller, and outputs an operation result to the EMIF protocol conversion module or to a corresponding functional module of the slave controller through a functional module of the controller module.

In the above technical solution, the functional modules of the slave controller include a register file and a functional logic module, where the register file is configured to receive instruction data from the functional module of the corresponding controller module and send the instruction data to the functional logic module; the functional logic module executes built-in algorithm logic based on the received instruction data, executes corresponding operation based on an operation result, and outputs feedback data of the executed operation to a functional module of the corresponding controller module through a register file.

In the technical scheme, part of the controller modules and the slave controllers are configured with the SRIO modules; the functional module of the controller module and the functional module of the slave controller are in interactive communication through the SRIO module; the partial controller module and the slave controller are configured with CAN modules; the functional module of the controller module and the functional module of the slave controller are in interactive communication through the CAN module.

In the above technical solution, each functional module of the master controller or the slave controller realizes configuration solidification and customization according to configuration data; the main controller or each functional module of the slave controller cleans and encapsulates the received configuration information, stores the configuration information into a register file, updates the corresponding register value, and encapsulates the data of the related register according to the requirement.

In the above technical solution, each functional module of the master controller or the slave controller configures data and address bit width, channel number, module base address, address depth and mode information through parameter parameters.

In the above technical solution, the time sequence implementation logic of each functional module of the master controller or the slave controller is: the function module sets the Ready signal to be low level when the function module is in a busy state and can not receive new data input, sets the Ready signal to be high level when the function module is in an idle state and can receive new data input, outputs effective addresses and data signals and continuously outputs Valid signals for 1 clock cycle at the high level when the data transmission module receives the Ready high level and the data transmission module is Ready for data and address signals, and latches the data and the address signals for carrying out operation on new data after receiving Valid high level information.

In the above technical solution, the logic for implementing the time sequence of each functional module of the master controller or the slave controller in the streaming mode is: the functional module outputs a Ready signal which can receive new effective data in the execution process of the effective input data, the data transmitting module receives the Ready high-level signal, outputs the prepared data and address signals, and simultaneously continuously outputs the Valid signal for 1 clock period at the high level; the functional module receives the Valid signal, latches the new data and the address signal, and performs operation by using the new data information after the current data execution is completed.

In the above technical solution, the logic for implementing the time sequence of each functional module of the master controller or the slave controller in the non-flow mode is: after the execution of the effective input data is finished, the functional module outputs a Ready signal which can receive new effective data, the data transmitting module receives a Ready high-level signal, outputs the prepared data and address signals, and simultaneously continuously outputs the Valid signal for 1 clock period at a high level; the function module performs an operation using the newly received data information after receiving the Valid signal.

The beneficial effects of the invention are as follows: the distributed control software design framework of the power electronic device solves the problems of high development difficulty and high development cost of embedded software in the related technology, and cures part of functional modules and protocol conversion modules to decouple the coupling relationship between controllers and the coupling relationship between modules; the software structure integrates ideas of reconfigurability, decentralization, cloud computing and the like, and supports are provided for the data-driven power electronic device and the power electronic device in an intelligent mode.

Drawings

FIG. 1 is a schematic diagram of an embedded software structure of a main controller provided by the invention;

FIG. 2 is a schematic diagram of the software structure of the slave controller a according to the present invention,

FIG. 3 is a schematic diagram b of a software configuration of a slave controller according to the present invention

FIG. 4 is a flow pattern logic timing diagram of an application of the present invention;

FIG. 5 is a logic timing diagram of another non-streaming mode of application of the present invention.

Detailed Description

The invention will now be described in further detail with reference to the drawings and specific examples, which are given for clarity of understanding and are not to be construed as limiting the invention.

As shown in fig. 1, the present invention provides a distributed control system for a power electronic device, including a master controller and a plurality of slave controllers; the slave controller adopts an FPGA. The main controller comprises a DSP and an FPGA; the DSP is used for executing a core control algorithm and sending instruction data to the FPGA according to the control algorithm result; the FPGA comprises a plurality of controller modules which are in one-to-one correspondence with a plurality of slave controllers and are communicated with each other; any one slave controller comprises N different functional modules, and the corresponding functional module of the slave controller is configured corresponding to the controller module of the slave controller; the N functional modules comprise solidified functional modules and self-defined functional modules, and the two functional modules can update configuration information according to actual requirements to switch. The FPGA performs operation on the received instruction data from the DSP and outputs an operation result to a corresponding functional module of the slave controller based on the configured functional module; the slave controller executes corresponding operation of the operation result of the received instruction data based on the configured functional module and sends feedback data to the functional module of the corresponding controller module; the FPGA receives feedback data based on the configured functional module and performs operation, the operation result is output to the DSP, and the DSP performs the next operation according to the feedback result from the controller.

In the technical scheme, the DSP and the FPGA complete data interaction through an EMIF bus; and packaging the DSP and the EMIF bus module of the FPGA to realize remote access of the DSP to the FPGA register, so that development of the DSP and development of the FPGA are decoupled.

The FPGA comprises an EMIF protocol conversion module and an algorithm logic module. The arithmetic logic module realizes the arithmetic of each controller module in the FPGA, and the register is mainly used for carrying out data interaction with the DSP and the slave controller; the EMIF protocol conversion module receives EMIF end data of instruction data through the EMIF bus module, and converts the EMIF end data into a register value serving as input of the algorithm logic module; the EMIF protocol conversion module receives the operation result of the algorithm logic module, converts the received operation result into EMIF end data and sends the EMIF end data to the DSP through the EMIF bus module.

In the above technical solution, the functional module of the controller module adopts a register file; the register file is used as input or output of an algorithm logic module, and corresponding register names are defined according to the corresponding functional modules of the slave controller; the algorithm logic module executes built-in algorithm logic based on the received EMIF end data or feedback data uploaded by the slave controller, and outputs an operation result to the EMIF protocol conversion module or to a corresponding functional module of the slave controller through a functional module of the controller module.

The functional modules of the slave controller comprise functional logic modules and register files. The functional logic module executes built-in algorithm logic based on instruction data received from a register file of the controller, executes corresponding operation based on operation results, and outputs feedback data of the executed operation to a functional module of a corresponding controller module through the register file.

As shown in fig. 2 and 3, the input and output of the functional logic module of the slave controller are the FPGA functional IO interface and the register file data, the functional logic module is used for implementing specific functions such as local protection, PWM output, ADC sampling, and the register file (i.e., the functional module) is used for performing information interaction with the master controller.

The arithmetic logic module finishes operation through the EMIF conversion register value and the slave controller uploading register value, and outputs the operation result to the EMIF protocol conversion register or the functional module of the controller module to the corresponding functional module of the slave controller. The functional modules (register files) in each controller module in the master controller and the register files in each functional module in each slave controller are used for realizing data interaction between the master controller and the slave controllers, and specific algorithm execution is realized through the algorithm logic module and the functional logic module respectively.

In the technical scheme, part of the controller modules and the slave controllers are configured with the SRIO modules; the functional module of the controller module and the functional module of the slave controller are in interactive communication through the SRIO module. The slave controller provided with the SRIO module is used as a core key slave controller, and an FPGA is adopted for collecting and controlling the state information of the core module of the power electronic device. The partial controller module and the slave controller are configured with CAN modules; the functional module of the controller module and the functional module of the slave controller are in interactive communication through the CAN module. The slave controller configured with the CAN module is a common slave controller, and adopts an FPGA or MCU for collecting and controlling the state information of the non-core module of the power electronic device. The SRIO module and the CAN module are both configured with IP addresses, so that one-to-one interactive communication between the controller module and the slave controller is ensured.

Specifically, the register file is used as input or output of the algorithm logic, and the register names of the corresponding functional modules are defined according to the functions (PWM maximum count value, rising edge dead zone value, A term voltage sampling value and the like) of each functional logic module or the algorithm logic; the FPGA of the master controller and the slave controller realize data interaction with the register files of the master controller and the slave controller through the encapsulation of the protocol. The operation of the register file (namely the functional modules of the master controller and the slave controller) is in a transparent transmission mode and a remote mode, the transparent transmission mode is that defined registers are transmitted through transmitting enabling according to the transmission time requirement of an algorithm, the slave controller end receives data through receiving enabling, and the remote mode is that the master controller end register and the slave controller end register are subjected to hot backup refreshing according to timing or a specific strategy, so that the master controller end register and the slave controller end register are kept consistent, and upper application logic only needs to operate the local registers.

In the above technical solution, each functional module of the master controller or the slave controller implements solidification and customization of configured algorithm logic according to configuration data; the main controller or each functional module of the slave controller cleans and encapsulates the received configuration information, stores the configuration information into a register file, updates the corresponding register value, and encapsulates the data of the related register according to the requirement. The slave controllers can be configured according to the distributed arrangement of the power electronic devices, and different slave controllers and corresponding controller modules are used for realizing the control of different equipment, so that the aim of controlling and decentering the power electronic devices is fulfilled.

In the above technical solution, each functional module (curing function x, custom function x) of the master controller or the slave controller uses parameter configuration data and information such as address bit width, channel number, module base address, address depth, and mode (streaming mode, non-streaming mode) to enhance versatility of each functional module.

In the above technical solution, each functional module (curing function xx, custom function xx) is used for receiving an instruction to control the outside or process information fed back externally. The time sequence implementation logic of each functional module of the master controller or the slave controller is as follows: the function module sets the Ready signal to be low level when the function module is in a busy state and can not receive new data input, sets the Ready signal to be high level when the function module is in an idle state and can receive new data input, outputs effective addresses and data signals and continuously outputs Valid signals for 1 clock cycle at the high level when the data transmission module receives the Ready high level and the data transmission module is Ready for data and address signals, and latches the data and the address signals for carrying out operation on new data after receiving Valid high level information.

As shown in fig. 4, the logic for implementing the time sequence of each functional module of the master controller or the slave controller in the streaming mode is as follows: the functional module outputs a Ready signal which can receive new effective data in the execution process of the effective input data, the data transmitting module receives the Ready high-level signal, outputs the prepared data and address signals, and simultaneously continuously outputs the Valid signal for 1 clock period at the high level; the functional module receives the Valid signal, latches the new data and the address signal, and performs operation by using the new data information after the current data execution is completed. The streaming mode has higher execution efficiency, but the next operation data needs to be latched in advance, so that more logic resources are consumed.

As shown in fig. 5, the logic for implementing the timing sequence of each functional module of the master controller or the slave controller in the non-flow mode is: after the execution of the effective input data is finished, the functional module outputs a Ready signal which can receive new effective data, the data transmitting module receives a Ready high-level signal, outputs the prepared data and address signals, and simultaneously continuously outputs the Valid signal for 1 clock period at a high level; the function module performs an operation using the newly received data information after receiving the Valid signal. Compared with the streaming mode, the non-streaming mode has lower execution efficiency, but does not need to latch the next operation data in advance, thereby saving logic resources

The logic design thought provided by the embodiment of the invention effectively decouples different processing chips (DSP and FPGA and different functional logic modules of the same FPGA) through the register file, and completes control logic through two signals of Valid and Ready, so that a logic interface is simplified, and the functional modules have higher universality through parameter parameterization function setting.

The distributed control software design method of the power electronic device solves the problems of high development difficulty and high development cost of embedded software in the related technology, and cures part of functional modules and protocol conversion modules, decouples the coupling relationship between controllers and the coupling relationship between modules; the software structure integrates ideas of reconfigurability, decentralization, cloud computing and the like, and supports are provided for data-driven power electronic devices and intelligent power electronic devices.

What is not described in detail in this specification is prior art known to those skilled in the art.

Claims

1. A distributed control system for a power electronic device, characterized by: the system comprises a master controller and a plurality of slave controllers; the main controller comprises a DSP and an FPGA; the DSP is used for executing a core control algorithm and sending instruction data to the FPGA according to the control algorithm result; the FPGA comprises a plurality of controller modules which are in one-to-one correspondence with a plurality of slave controllers and are communicated with each other; any one slave controller comprises a plurality of different functional modules, and the corresponding controller module of the slave controller is correspondingly provided with the corresponding functional module of the slave controller; the FPGA performs operation on the received instruction data from the DSP and outputs an operation result to a corresponding functional module of the slave controller based on the configured functional module; the slave controller executes corresponding operation of the operation result of the received instruction data based on the configured functional module and sends feedback data to the functional module of the corresponding controller module; the FPGA receives feedback data based on the configured functional module, performs operation, and outputs an operation result to the DSP;

the functional module of the controller module adopts a register file; the function module of the controller module is used as input or output of the algorithm logic module, and the register names of the function modules of the corresponding controller modules are defined according to the corresponding function modules of the slave controllers;

The algorithm logic module executes built-in algorithm logic based on the received EMIF end data or feedback data uploaded by the slave controller, and outputs an operation result to an EMIF protocol conversion module or a corresponding slave controller functional module through the controller functional module;

The functional modules of the slave controllers comprise register files and functional logic modules, and the register files are used for receiving instruction data from the functional modules of the corresponding controller modules and sending the instruction data to the functional logic modules; the functional logic module executes built-in algorithm logic based on the received instruction data, executes corresponding operation based on an operation result, and outputs feedback data of the executed operation to a functional module of the corresponding controller module through a register file.

2. A power electronics distributed control system according to claim 1, wherein: the DSP and the FPGA complete data interaction through an EMIF bus; packaging the EMIF bus modules of the DSP and the FPGA; the FPGA comprises an EMIF protocol conversion module and an algorithm logic module; the EMIF protocol conversion module receives EMIF end data of instruction data through the EMIF bus module, and converts the EMIF end data into a register value serving as input of the algorithm logic module; the EMIF protocol conversion module receives the operation result of the algorithm logic module, converts the received operation result into EMIF end data and sends the EMIF end data to the DSP through the EMIF bus module.

3. A power electronics distributed control system according to claim 2, wherein: the partial controller modules and the slave controllers are configured with SRIO modules; the functional module of the controller module and the functional module of the slave controller are in interactive communication through the SRIO module; the partial controller module and the slave controller are configured with CAN modules; the functional module of the controller module and the functional module of the slave controller are in interactive communication through the CAN module.

4. A power electronics distributed control system according to claim 2, wherein: the main controller or each functional module of the slave controller realizes the solidification and the customization of the configuration according to the configuration data; the main controller or each functional module of the slave controller cleans and encapsulates the received configuration information, stores the configuration information into a register file, updates the corresponding register value, and encapsulates the data of the related register according to the requirement.

5. A power electronics distributed control system according to claim 4, wherein: and each functional module of the master controller or the slave controller configures data and address bit width, channel number, module base address, address depth and mode information through parameter parameters.

6. A power electronics distributed control system according to claim 5, wherein: the time sequence implementation logic of each functional module of the master controller or the slave controller is as follows: the function module sets the Ready signal to be low level when the function module is in a busy state and can not receive new data input, sets the Ready signal to be high level when the function module is in an idle state and can receive new data input, outputs effective addresses and data signals and continuously outputs Valid signals for 1 clock cycle at the high level when the data transmission module receives the Ready high level and the data transmission module is Ready for data and address signals, and latches the data and the address signals for carrying out operation on new data after receiving Valid high level information.

7. A power electronics distributed control system according to claim 6, wherein: the time sequence realizing logic of each functional module of the master controller or the slave controller adopting the stream mode is as follows: the functional module outputs a Ready signal which can receive new effective data in the execution process of the effective input data, the data transmitting module receives the Ready high-level signal, outputs the prepared data and address signals, and simultaneously continuously outputs the Valid signal for 1 clock period at the high level; the functional module receives the Valid signal, latches the new data and the address signal, and performs operation by using the new data information after the current data execution is completed.

8. A power electronics distributed control system according to claim 7, wherein: the time sequence implementation logic of each functional module of the master controller or the slave controller adopting the non-flow mode is as follows: after the execution of the effective input data is finished, the functional module outputs a Ready signal which can receive new effective data, the data transmitting module receives a Ready high-level signal, outputs the prepared data and address signals, and simultaneously continuously outputs the Valid signal for 1 clock period at a high level; the function module performs an operation using the newly received data information after receiving the Valid signal.