CN113872643B - Anti-collision command processing and responding device - Google Patents
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- H—ELECTRICITY
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- H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
- H04B5/40—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by components specially adapted for near-field transmission
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Abstract
The application provides an anticollision command processing and response device, the device includes: the system comprises a cascade selector, a UID selector, an anti-collision command analysis module, a response calculation and data preparation module and a gating module; a cascade selector to indicate the UID length; a UID selector for determining a cascade to which UIDs for collision avoidance analysis belong; the anti-collision command analysis module is used for analyzing the anti-collision command; the response calculation and data preparation module is used for preparing related data; and the gating module is used for delaying enabling signals for two periods and is used for synchronously resetting and clock gating the anti-collision module. The application provides an anticollision command processing and answering device which processes the received byte command without registering, thereby saving a large number of buffers. Meanwhile, a parallel processing mode is adopted, the preparation of response data can be completed in two periods, and the response speed is greatly improved. Due to the use of the gating module, the power consumption of the system is greatly reduced.
Description
Technical Field
The application relates to the technical field of TYPEA label chips, in particular to an anti-collision command processing and responding device.
Background
At present, in contactless near field communication, one active device needs to face a plurality of tags. When a plurality of tags are present, collision is inevitable, and it is most important that the tags make accurate command processing and response.
At present, most of chips in the market do not support anti-collision, and a serial processing mode is basically adopted for part of chips supporting anti-collision, wherein the serial processing mode needs a large number of buffers to cache commands, and the commands are analyzed and processed after being received; in addition, the serial processing mode mostly adopts combinational logic design, the anti-collision is very complex data processing, and the serious problems of time sequence violation, competition and risk, metastable state and the like caused by excessive nesting are inevitable when the combinational logic is excessively used; secondly, because of the serial data processing mode, the main frequency is reduced due to the sensitivity to some power consumption, but the response speed is greatly reduced for the customized chip which has special requirements on the response speed and is used in special occasions.
Disclosure of Invention
The application provides an anti-collision command processing and responding device, aiming at solving the technical defects in the prior art.
The application provides an anticollision command processing and answering device, anticollision command processing and answering device includes: the system comprises a cascade selector, a UID selector connected with the cascade selector, an anti-collision command analysis module connected with the UID selector, a response calculation and data preparation module connected with the anti-collision command analysis module, and a gate control module connected with the anti-collision command analysis module and the response calculation and data preparation module;
the cascade selector is used for indicating the UID length of the anti-collision comparison;
the UID selector is used for determining the cascade to which the UID for anti-collision analysis belongs;
the anti-collision command analysis module is used for receiving an anti-collision command and analyzing the anti-collision command;
the response calculation and data preparation module is used for preparing SAK data and determining the number of complete bytes and the number of bits of incomplete bytes;
the gate control module is used for delaying enabling signals in two periods, synchronously resetting the anti-collision module and clock gating the anti-collision module.
According to the anti-collision command processing and responding device provided by the application, the cascade selector comprises two input selectors;
the two-input selector is used for indicating the UID length of the anti-collision comparison, wherein the UID length comprises a first UID length, a second UID length and a third UID length.
According to the anti-collision command processing and responding device provided by the application, the UID selector comprises two input selectors;
and the two-input selector is used for determining the cascade to which the UID for anti-collision analysis belongs according to a cascade counter in the cascade selector.
According to the anti-collision command processing and responding device provided by the application, the anti-collision command analysis module comprises a first state machine;
wherein the states of the first state machine include an idle state, an analysis state, a reply state, and an unselected state;
the first state machine is configured to analyze the anti-collision command according to the idle state, the analysis state, the response state, and the unselected state.
According to the anti-collision command processing and responding device provided by the application, the first state machine in the analysis state comprises a second state machine;
the states of the second state machine comprise a first byte state, a seventh byte state, a defective byte comparison state and a UID response state;
and the second state machine is used for carrying out splitting register, parameter comparison analysis or/and UID tearing on the anti-collision command according to the first byte state to the seventh byte state, the incomplete byte comparison state and the UID response state.
According to the anti-collision command processing and responding device provided by the application, the second state machine in the first byte state to the seventh byte state is used for performing splitting, registering and parameter comparison analysis according to the output byte data.
According to the anti-collision command processing and responding device provided by the application, the second state machine in the incomplete byte comparison and UID response states is used for carrying out parameter comparison analysis and tearing UID on incomplete bytes.
According to the anti-collision command processing and responding device provided by the application, the responding calculation and data preparation module comprises a collision byte calculation state machine;
and the collision byte calculation state machine is used for determining the number of the complete bytes to be sent by the tearing position.
According to the anti-collision command processing and responding device provided by the application, the response calculation and data preparation module comprises a collision bit calculation state machine;
and the collision bit calculation state machine is used for determining the bit number of the incomplete byte to be sent by the tearing position.
According to the anti-collision command processing and responding device provided by the application, the gate control module comprises two stages of synchronous registers and a gate control unit;
the two-stage synchronous register is used for two period delay enable signals and synchronous reset anti-collision modules;
the gating unit is used for clock gating the anti-collision module.
The anti-collision command processing and responding device provided by the application processes the one-byte command every time the one-byte command is received, does not need to register the received command, and saves a large amount of buffers for command registration. Meanwhile, due to the adoption of a parallel processing mode, the preparation of response data can be completed in two periods after the command is received, and the response speed is greatly improved. In addition, a door control module is added in the anti-collision command processing and responding device, so that the power consumption of the system is greatly reduced.
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In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an anti-collision command processing and responding apparatus provided in the present application;
fig. 2 is a UID tear schematic.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The following describes the collision avoidance command processing and responding apparatus provided in the present application with reference to fig. 1 to 2. Referring to fig. 1 to 2, fig. 1 is a schematic diagram of an anti-collision command processing and responding apparatus provided in the present application; fig. 2 is a UID tear schematic.
While the embodiments of the present application provide an embodiment of an anti-collision command processing and responding apparatus, it should be noted that, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order different from that shown or described herein.
Referring to fig. 1, fig. 1 is a schematic diagram of an anti-collision command processing and responding apparatus provided in the present application. The anti-collision command processing and responding device provided by the embodiment of the application comprises: the system comprises a cascade selector, a UID selector connected with the cascade selector, an anti-collision command analysis module connected with the UID selector, a response calculation and data preparation module connected with the anti-collision command analysis module, and a gate control module connected with the anti-collision command analysis module and the response calculation and data preparation module;
the cascade selector is used for indicating the UID length of the anti-collision comparison;
the UID selector is used for determining the cascade to which the UID for anti-collision analysis belongs;
the anti-collision command analysis module is used for receiving an anti-collision command and analyzing the anti-collision command;
the response calculation and data preparation module is used for preparing SAK data and determining the number of complete bytes and the number of bits of incomplete bytes;
the gate control module is used for delaying enabling signals in two periods, synchronously resetting the anti-collision module and clock gating the anti-collision module.
In this embodiment, the cascade selector is connected to the UID selector, and the current cascade parameter selector is synthesized together. The cascade selector is used for indicating the UID length of the anti-collision comparison, and further, in an embodiment, the cascade selector comprises a two-input selector which is used for indicating the UID length of the anti-collision comparison for the upper module, wherein the UID length comprises a first UID length, a second UID length and a third UID length, and the first UID length, namely UID length, only includes UIDCL1The second UID length, UID, comprises a UIDCL1And UIDCL2The third UID length, UID, comprises a UIDCL1、UID CL2And UIDCL3As shown in table 1, table 1 is a UID cascade diagram.
TABLE 1 UID Cascade schematic
It will be appreciated that the two-input selector is used to indicate to the upper module that the entire UID includes a UIDCL1、UID CL2、UID CL3UIDCL in (1)1Or UIDCL1And UIDCL2Or is also UIDCL1、UID CL2And UIDCL3And after the instruction, providing a condition for response processing to the SELECT command.
Further, the UID selector sequentially collides each cascaded UID to determine the cascade to which the UID for collision avoidance analysis belongs, and in an embodiment, the UID selector includes a two-input selector, and the two-input selector is configured to determine the cascade to which the UID for collision avoidance analysis belongs according to a current cascade counter in the cascade selector.
And the UID selector is connected with an anti-collision command analysis module and is used for receiving the anti-collision command and analyzing the anti-collision command. In an embodiment, the anti-collision command analysis module includes a first state machine, which may be defined as a large state machine, where the large state machine includes, but is not limited to, an idle state, an analysis state, an answer state, and an unselected state, and the large state machines in the above four states are all used to analyze different anti-collision commands, and jump after analysis, and output different information. In one embodiment, the big-state machine in the analysis state includes a second state machine, which may be defined as a small-state machine, the states of the small-state machine include, but are not limited to, a first byte state to a seventh byte state, and a defective byte comparison and UID response state, wherein the first byte state to the seventh byte state are a byte 0 state, a byte 1 state, a byte 2 state, a byte 3 state, a byte 4 state, a byte 5 state, and a byte 6 state, respectively. Therefore, in the byte 0 state to the byte 6 state, the small state machine performs the split register and parameter comparison analysis on the output byte data, where the byte data are 1 byte data, 2 byte data, 3 byte data, 4 byte data, 5 byte data, 6 byte data and 7 byte data, and it can be understood that the byte 0 state to the byte 6 state are used for the split register and parameter comparison analysis on the output 1 byte data to 7 byte data (without CRC). And when the incomplete bytes are compared and the UID responds, the second state machine performs parameter comparison analysis and UID tearing on the incomplete bytes.
Furthermore, the anti-collision command analysis module is connected to the response calculation and data preparation module, and the anti-collision command analysis module is mainly used for preparing SAK-related data, such as BCC calculation, determining whether UID is complete, and the like, and at the same time, the number of complete bytes and the number of bits of incomplete bytes need to be determined. In an embodiment, the anti-collision command analysis module includes two small state machines in response state, and one small state machine is a collision bit calculation state machine, and is configured to determine how many number of incomplete bytes need to be sent after the tear position, that is, the number of bits of the incomplete bytes to be sent needs to be calculated to indicate the lower module. The other small state machine is a collision byte calculation state machine and is used for determining how many complete bytes need to be sent after the tearing position, namely, the number of the complete bytes to be sent needs to be calculated so as to indicate the lower module.
Furthermore, the gating module is connected with the anti-collision command analysis module and the response calculation and data preparation module, the gating module can delay the enable signal for two periods and synchronously reset the anti-collision module, namely, the enable signal is delayed for two periods, so that the anti-collision module can be synchronously reset after the code enable is closed, and meanwhile, the anti-collision module can be clocked and gated, wherein the anti-collision command analysis module and the response calculation and data preparation module jointly form the anti-collision module. In one embodiment, the gate control module comprises a two-stage synchronous register and a gate control unit, and the two-stage synchronous register delays the enable signal by two cycles, so that the anti-collision module can be synchronously reset after the encoding enable is closed. And the gate control unit performs clock gate control on the anti-collision module.
Further, the anti-collision command processing and responding device provided by the application provides another embodiment.
Specifically, the anti-collision command processing and responding apparatus provided by the present application has two cascaded UID tags, and assuming that one of the cascaded UID tags is AAh _ BBh _ CCh _00000101b, the analysis of data analysis, command response data combination, and parameter calculation of the commands 93h +53h + AAh + BBh + CCh +101b in the cascade anti-collision is as follows.
The cascade selector mainly comprises a two-input selector. For indicating to upper module that entire UID includes UIDCL1、UID CL2、UID CL3UIDCL in (1)1Is also UID CL1、UID CL2Or is also UIDCL1、UID CL2、UID CL3Includes providing conditions for response processing to the SELECT command after the indication. At this time, the upper module configures the two-input selector of the cascade selector to 00b, so that the anti-collision data is ready to match with a cascade UID data. The UID selector mainly comprises a two-input selector. For selecting which cascade UID is currently collided according to the current cascade counter, and all collision commands need to be processed byAnd the cascade is transited to the second cascade from the first cascade and the second cascade to the third cascade in sequence, so that the malicious anti-collision command is prevented from directly accessing the third cascade. At this time, the anti-collision module performs a cascade collision stage, the counter of the cascade counter is 0, then the input value of the two input selectors in the UID selector is 00b, and a cascade UID is selected for anti-collision analysis, namely the anti-collision analysis module performs analysis.
Further, the collision avoidance analysis command analysis module analyzes as follows: .
The current cascade parameter selector is formed by combining a cascade selector and a UID selector. And the BCC calculation is to perform bitwise XOR operation on each cascaded four-byte data after the UID selector determines to obtain a BCC calculation result. A single byte completed process consists of two level one registers. After the coding and decoding module outputs the single byte processing completion signal, the coding and decoding single byte processing completion signal is respectively registered for mark edge detection. The mark edge detection identifies the edge of the signal after the encoding and decoding single byte processing through operation, and only maintains for a limited number of cycles.
When the data disassembly register detects a first signal at the mark edge, the data line of the decoding module is sampled to obtain first byte data (SEL) which is just decoded, and the first byte data is analyzed in real time. In this embodiment, it is first determined whether the first byte data is equal to 93h (first concatenation flag), and if it is determined that the first byte data is equal to 93h, the analysis of the next byte data is continued. If it is determined that the first byte data is not equal to 93h, the tag is stuck. It should be noted that, in the case of a tag being stuck, the tag can be restored only when the power is down, or the MCM controller recognizes that the command returns to the idle state.
In this embodiment, it may be assumed that the first byte data is equal to 93h, that is, the first byte data is successfully compared, and the next byte data is obtained. When the second signal is detected at the edge of the mark, the data line of the decoding module is sampled to obtain the second byte data which is just decoded, and the second byte data is analyzed (hereinafter, this description will be omitted, and is simply referred to as "data obtained by design"). And then, splitting the received second byte data, registering the upper four bits (NVB) after splitting as the received byte number, and registering the lower four bits (NVB) as the received incomplete bit number. Further, whether the number of received bytes at the time is equal to 2 or not is determined, and if the number of received bytes at the time is determined to be equal to 2, incomplete byte comparison is carried out. If the number of received bytes is determined to be not equal to 2 at the moment, the UID CLn comparison is carried out.
In this embodiment, the upper four bits of NVB are registered as having a received byte number equal to 5, so that the UID CLn comparison is performed, and after the NVB is judged again by the UID CLn comparison, the cascade first byte comparison is performed. At this time, data is acquired according to the design, if the acquired data is AAh, the comparison of the first byte of the cascade is correct, and the comparison of the second byte of the cascade is continued. If the alignment is misplaced in the second byte, the tag is not selected, and NOSELECT is entered and kept silent.
In this embodiment, it may be assumed that the comparison of the second byte is successful, and the comparison of the cascade second byte and the cascade third byte is completed as in the comparison of the cascade first byte. And when the third byte of the cascade is correct, performing incomplete byte comparison, and if the NVB received at the beginning is 70h, performing cascade fourth byte comparison, performing BCC (body-to-body communication) check, and judging whether the received seventh byte data is consistent with the BCC calculation data calculated by the BCC.
Returning to this embodiment, the incomplete byte comparison is performed, and according to the four lower bits of the NVB, that is, the number of received incomplete bits, the shift register is used to extract the incomplete bits corresponding to the last byte of the cascade for comparison, where the four lower bits of the NVB are equal to 3, and then the shift register extracts the incomplete bits corresponding to the last byte (00000101 b) of the cascade, that is, the last three bits 101b, which are consistent with the received 101b, and after the anti-collision command 93h +53h + AAh + BBh + CCh +101b is analyzed, the response calculation and data preparation module is then performed for analysis.
Further, the analysis of the answer calculation and data preparation module is as follows:
in the cascade counter, when NVB =70 and all cascade bytes and BCC comparison are completed, the cascade counter increments by one to indicate that the next command will enter the next cascade comparison, or to be used in the cascade count comparison to determine whether the entire UID has completed all cascade collisions. In the cascade count comparison, it is determined whether the entire UID has completed all cascade collisions to indicate SAK responses for data preparation.
Returning to this embodiment, the UID in the response calculation and data preparation module at this time is not completely responded. And in the UID incomplete response, outputting an UID incomplete mark and indicating the calculation of the number of sending bytes and the calculation of the number of sending bits to start operation.
According to the embodiment, the number of bytes sent is 53h, and the data disassembly register completes the disassembly of the NVB. The number of transmitted bytes = 7-the number of received bytes at this time, i.e. the number of transmitted bytes equals 2, the result being used to indicate the operation of the encoding module.
In this embodiment, the number of transmission bits is 53h, and the data disassembly register 12 completes the disassembly of the NVB. The number of transmitted bits = 8-the number of received incomplete bits, i.e. the number of transmitted bits is equal to 5 results at this time, for indicating the operation of the coding module.
Sending data preparation according to the number of sending bytes and the number of sending bits, and calculating the tearing UID, as shown in FIG. 2, FIG. 2 is a UID tearing diagram. The result of the number of transmitted bytes calculation is 2, the result of the number of transmitted bits calculation is 5, indicating a cascade UID, which will reply with the last byte, i.e. the last 5 bits of the fourth byte (this is 1 byte, although not complete), and a byte BCC, which is the result from the calculation in the BCC calculation.
At this point, the data and configuration parameters are ready, and if NVB =70 is initially received and all concatenated bytes and BCC comparison are completed, then the anti-collision response is not entered, but the SAK response is entered. The SAK response determines whether the UID is completely acquired as different responses according to the comparison result of the cascade comparison, and if the UID is completely acquired, the response is 00h + CRC-A. And if the UID is not completely acquired, responding to 04h + CRC-A. Returning to the embodiment, the anti-collision response is entered, the sending mark edge output in the mark edge detection is waited, and one byte of data is loaded to the sending data line once mark comes. By this point, the command analysis and response for the anti-collision command 93h +53h + AAh + BBh + CCh +101b is completed.
The anti-collision command processing and responding device provided by the embodiment processes the one-byte command every time the one-byte command is received, does not need to register the received command, and saves a large amount of buffers for command registration. Meanwhile, due to the adoption of a parallel processing mode, the preparation of response data can be completed in two periods after the command is received, and the response speed is greatly improved. In addition, a gating module is added in the anti-collision command processing and responding device, so that the power consumption of the system is greatly reduced, and the anti-collision command processing and responding device has good adaptability to some power consumption sensitive scenes. Meanwhile, all parts related to data processing of the anti-collision command processing and responding device provided by the embodiment are designed by adopting sequential logic, and the anti-collision command from the autonomous near-field equipment is processed in real time by adopting a parallel processing technology, so that the operation is guaranteed to be completed in a very short time, and the tag can complete the preparation of response data in two periods.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. An anti-collision command processing and responding apparatus, comprising: the system comprises a cascade selector, a UID selector connected with the cascade selector, an anti-collision command analysis module connected with the UID selector, a response calculation and data preparation module connected with the anti-collision command analysis module, and a gate control module connected with the anti-collision command analysis module and the response calculation and data preparation module;
the cascade selector is used for indicating the UID length of the anti-collision comparison;
the UID selector is used for determining the cascade to which the UID for anti-collision analysis belongs;
the anti-collision command analysis module is used for receiving an anti-collision command and analyzing the anti-collision command;
the response calculation and data preparation module is used for preparing SAK data and determining the number of complete bytes and the number of bits of incomplete bytes;
the door control module is used for delaying enabling signals in two periods, synchronously resetting the anti-collision module and clock gating the anti-collision module, wherein the anti-collision command analysis module and the response calculation and data preparation module jointly form the anti-collision module.
2. The collision avoidance command processing and responding device of claim 1, wherein said cascaded selector comprises a two-input selector;
the two-input selector is used for indicating the UID length of the anti-collision comparison, wherein the UID length comprises a first UID length, a second UID length and a third UID length.
3. The collision avoidance command processing and response apparatus of claim 1, wherein the UID selector comprises a two-input selector;
and the two-input selector is used for determining the cascade to which the UID for anti-collision analysis belongs according to a cascade counter in the cascade selector.
4. The collision avoidance command processing and answering device according to claim 1, wherein the collision avoidance command analysis module comprises a first state machine;
wherein the states of the first state machine include an idle state, an analysis state, a reply state, and an unselected state;
the first state machine is configured to analyze the anti-collision command according to the idle state, the analysis state, the response state, and the unselected state.
5. The collision avoidance command processing and answering device according to claim 4, wherein the first state machine in the analysis state comprises a second state machine;
the states of the second state machine comprise a first byte state, a seventh byte state, a defective byte comparison state and a UID response state;
and the second state machine is used for carrying out splitting register, parameter comparison analysis or/and UID tearing on the anti-collision command according to the first byte state to the seventh byte state, the incomplete byte comparison state and the UID response state.
6. The apparatus according to claim 5, wherein the second state machine in the first byte state to the seventh byte state is configured to perform split register and parameter comparison analysis on the output byte data.
7. The apparatus of claim 5, wherein the second state machine in the incomplete byte comparison and UID response state is configured to perform parameter comparison analysis on incomplete bytes and tear UID.
8. The collision avoidance command processing and response apparatus of claim 1, wherein said response calculation and data preparation module comprises a collision byte calculation state machine;
and the collision byte calculation state machine is used for determining the number of the complete bytes to be sent by the tearing position.
9. The collision avoidance command processing and response apparatus of claim 1, wherein said response calculation and data preparation module comprises a collision bit calculation state machine;
and the collision bit calculation state machine is used for determining the bit number of the incomplete byte to be sent by the tearing position.
10. The collision avoidance command processing and answering device according to claim 1, wherein the gating module comprises two levels of synchronization registers and gating cells;
the two-stage synchronous register is used for two period delay enable signals and synchronous reset anti-collision modules;
the gating unit is used for clock gating the anti-collision module.
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| CN100495424C (en) * | 2007-06-13 | 2009-06-03 | 华南理工大学 | Multi-tag dynamic bit arbitration anti-collision method for RFID system |
| DE102008053369A1 (en) * | 2008-10-27 | 2010-04-29 | Giesecke & Devrient Gmbh | A method for challenge-response authentication between a reader and a transponder based on a contactless data transmission |
| CN102479308B (en) * | 2010-11-23 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Radio frequency identification anti-collision circuit and realizing method thereof |
| CN108021957B (en) * | 2017-12-05 | 2021-07-23 | 深圳市艾特智能科技有限公司 | Anti-collision method and system, readable storage medium and card reading device |
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Inventor after: Wu Jin Inventor after: Li Yang Inventor after: Ding Yanyu Inventor after: Duan Zhikui Inventor after: Qin Junrui Inventor before: Wu Jin Inventor before: Li Yang Inventor before: Hu Jianguo Inventor before: Wang Deming Inventor before: Ding Yanyu Inventor before: Duan Zhikui Inventor before: Qin Junrui |