CN113871409A

CN113871409A - Semiconductor structure and forming method thereof

Info

Publication number: CN113871409A
Application number: CN202010613547.4A
Authority: CN
Inventors: 蔡巧明; 张烨; 王哲
Original assignee: Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
Current assignee: Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2021-12-31

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, including a memory area, a front-layer metal interconnection structure in the substrate, the front-layer metal interconnection structure exposed on the surface of the substrate, and a resistive memory cell structure formed on the memory area substrate , the bottom is connected to the front-layer metal interconnection structure, and a first dielectric layer covering the resistive memory cell structure is formed on the substrate; a first through hole interconnection structure is formed in the first dielectric layer on the top of the resistive memory cell structure ; forming a second dielectric layer on the first dielectric layer; forming a first metal interconnection structure electrically connected to the first via interconnection structure in the second dielectric layer on top of the resistive memory cell structure, the first metal interconnection structure The interconnect structure includes first metal interconnect lines; in the memory region, the first metal interconnect lines connect a plurality of first via interconnect structures. The invention reduces the probability of short circuit between the first metal interconnection line and the front-layer metal interconnection structure, or short circuit of the adjacent resistive memory cell structure through the first metal interconnection line.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

Semiconductor memory is an indispensable component of various electronic equipment systems, while nonvolatile memory has the characteristic of being able to still store data under the condition of power failure, and thus is widely applied to various mobile and portable devices, such as mobile phones, notebooks, palmtop computers, and the like.

The Resistive Random Access Memory (RRAM) has the advantages of simple preparation process, high read-write speed, high storage density, non-volatility, good compatibility with the traditional silicon integrated circuit process and the like, thereby having great application potential in the field of semiconductor memories.

A typical RRAM includes a bottom electrode, a top electrode, and a varistor layer therebetween, wherein the varistor layer is changed between a high resistance state and a low resistance state according to a voltage applied to the varistor layer, thereby opening or blocking a current flow path and storing various information using the properties.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a memory area, a front-layer metal interconnection structure is formed in the substrate, the front-layer metal interconnection structure is exposed out of the surface of the substrate, a plurality of resistance change memory unit structures are formed on the substrate of the memory area, the bottoms of the resistance change memory unit structures are connected with the front-layer metal interconnection structure, and a first dielectric layer covering the resistance change memory unit structures is formed on the substrate; forming a first through hole interconnection structure in a first dielectric layer on the top of the resistive random access memory unit structure; forming a second dielectric layer on the first dielectric layer; forming a first metal interconnection structure electrically connected with the first through hole interconnection structure in a second dielectric layer on the top of the resistive random access memory unit structure, wherein the first metal interconnection structure comprises a first metal interconnection line; wherein, in the memory region, the first metal interconnection line connects a plurality of the first via interconnection structures.

Accordingly, an embodiment of the present invention provides a semiconductor structure, including: the memory device comprises a substrate, a memory area, a first-layer metal interconnection structure and a second-layer metal interconnection structure, wherein the first-layer metal interconnection structure is formed in the substrate, and the first-layer metal interconnection structure is exposed out of the surface of the substrate; the resistive random access memory unit structures are positioned on the substrate of the memory area, and the bottoms of the resistive random access memory unit structures are connected with the front-layer metal interconnection structure; the first dielectric layer is positioned on the substrate and covers the resistive random access memory unit structure; the first through hole interconnection structure penetrates through the first dielectric layer on the top of the resistive random access memory unit structure; a second dielectric layer on the first dielectric layer; the first metal interconnection structure penetrates through the second dielectric layer on the top of the resistive random access memory unit structure and is electrically connected with the first through hole interconnection structure, and the first metal interconnection structure comprises a first metal interconnection line; wherein, in the memory region, the first metal interconnection line connects a plurality of the first via interconnection structures.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

according to the embodiment of the invention, a first through hole interconnection structure is formed in a first dielectric layer on the top of a resistive random access memory unit structure, and a first metal interconnection structure electrically connected with the first through hole interconnection structure is formed in a second dielectric layer above the first dielectric layer, wherein the first metal interconnection structure comprises a first metal interconnection line, and the first metal interconnection line of a memory area is connected with a plurality of first through hole interconnection structures; the method for forming the metal interconnection line generally comprises the step of etching a dielectric layer to form an interconnection groove, so that compared with the scheme of forming a metal interconnection line for connecting a plurality of resistive random access memory unit structures in a first dielectric layer on the top of the resistive random access memory unit structure, the longitudinal distance from the first metal interconnection line to the resistive random access memory unit structures is increased, so that the probability that the first dielectric layer between adjacent resistive random access memory unit structures is etched by mistake or even the bottom of the interconnection groove for forming the first metal interconnection line is exposed out of the side wall of the adjacent resistive random access memory unit structure or a front layer metal interconnection structure is reduced in the process of forming the first metal interconnection structure, and the probability that the first metal interconnection line and the front layer metal interconnection structure are short-circuited or the adjacent resistive random access memory unit structures are short-circuited through the first metal interconnection line can be reduced, thereby improving the performance of the semiconductor structure.

Drawings

Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

FIGS. 5-12 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;

fig. 13 to 16 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

At present, the forming process of the RRAM device is compatible with the back-end process, but the performance of the RRAM device is not good. The reason for the poor performance of a semiconductor structure is analyzed in combination with a method for forming a semiconductor structure.

Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a substrate (not labeled) is provided, which includes a memory region 10b and a non-memory region 10a, a front-level metal interconnection structure 11 is formed in the substrate, and the front-level metal interconnection structure 11 is exposed on the surface of the substrate. Specifically, the substrate includes a front dielectric layer 10, and the front metal interconnection structure 11 is located in the front dielectric layer 10 of the memory region 10b and the non-memory region 10 a.

With continued reference to fig. 1, a plurality of resistive memory cell structures 30 and a first dielectric layer 20 covering the resistive memory cell structures 30 are formed on the substrate of the memory region 10b, and the bottom of the resistive memory cell structure 30 is connected to the front metal interconnection structure 11.

Specifically, the first dielectric layer 20 includes a first sub-dielectric layer 21 and a second sub-dielectric layer 22 on the first sub-dielectric layer 21. The resistive memory cell structure 30 includes a bottom electrode layer 31, a resistance change material layer 32, and a top electrode layer 33 sequentially stacked from bottom to top, and in a formation process of the semiconductor structure, a trench is first formed in the first sub-dielectric layer 21 and filled to form the bottom electrode layer 31, then the stacked resistance change material layer 32 and the top electrode layer 33 are formed on the bottom electrode layer 31, and then the second sub-dielectric layer 22 covering the top electrode layer 33, the resistance change material layer 32, and the first sub-dielectric layer 21 is formed.

Referring to fig. 2, the first dielectric layer 20 of the memory region 10b is etched to form an interconnection trench 42 exposing the plurality of resistive memory cell structures 30 at the bottom and the remaining first dielectric layer 20 between adjacent resistive memory cell structures 30; the first dielectric layer 20 of the non-memory region 10a is etched to form an interconnect opening 41 with the bottom exposed from the front-level metal interconnect structure 11.

Specifically, the interconnect opening 41 includes an interconnect via 41 and an interconnect groove 42 communicating with the top of the interconnect via 41, and the interconnect groove 42 of the memory region 10b and the non-memory region 10a are formed in the same step.

Referring to fig. 3, the interconnect trench 42 and the interconnect via 41 are filled, and a first via interconnect structure 51 located in the interconnect via 41 and a first metal interconnect line 52 located in the interconnect trench 42 are formed. The first metal interconnection line 52 and the first via interconnection structure 51 of the non-memory region 10a constitute a first metal interconnection structure 50.

Referring to fig. 4, a second dielectric layer 60 is formed to cover the first dielectric layer 20 and the first metal interconnection structure 50, and a second metal interconnection structure 70 is formed in the second dielectric layer 60 of the non-memory region 10a, the bottom of the second metal interconnection structure 70 being connected to the first metal interconnection line 52. The second metal interconnection structure 70 includes a second metal interconnection 72 and a second via interconnection structure 71 between the second metal interconnection 72 and the first metal interconnection line 52.

In order to ensure that the interconnection trench 42 can expose the top surface of the corresponding resistive random access memory cell structure 30, in the process of etching the first dielectric layer 20, after the main etching is completed, an over etching (over etch) is usually performed, and in the process of performing the over etching, an over etching is easily performed on the remaining first dielectric layer 20 located between the adjacent resistive random access memory cell structures 30, so that the remaining first dielectric layer 20 between the adjacent resistive random access memory cell structures 30 is easily recessed (as shown by a dashed circle in fig. 2), and accordingly, the first metal interconnection line 52 filling the interconnection trench 42 is also recessed. When the problem of the mis-etching is serious, the interconnection groove 42 is easily caused to expose the opposite sidewalls of the adjacent resistive memory cell structures 30, and even expose the lower metal interconnection structure 11, so that a short circuit is easily caused between the adjacent resistive memory cell structures 30 through the first metal interconnection line 52, or a short circuit is easily caused between the first metal interconnection line 52 and the front metal interconnection structure 11, thereby causing the performance of the semiconductor structure to be degraded. In particular, the second sub-dielectric layer 22 is formed after the top electrode layer 33 and the resistance variable material layer 32 are formed, and the top electrode layer 33 and the resistance variable material layer 32 have a certain thickness, so that when the distance between adjacent resistance variable memory cell structures 30 is small, the gap filling capability of the material of the second sub-dielectric layer 22 between the adjacent resistance variable memory cell structures 30 is easily reduced, and thus a void (void) defect is easily generated in the second sub-dielectric layer 22 between the adjacent resistance variable memory cell structures 30, and the existence of the void defect may cause a high probability that the interconnection trench 42 exposes the opposite sidewalls of the adjacent resistance variable memory cell structures 30 or the front metal interconnection structure 11.

In order to solve the technical problem, in the embodiment of the invention, a first through hole interconnection structure is formed in a first dielectric layer on the top of a resistive random access memory cell structure, and a first metal interconnection structure electrically connected with the first through hole interconnection structure is formed in a second dielectric layer above the first dielectric layer, wherein the first metal interconnection structure comprises a first metal interconnection line, and the first metal interconnection line of the memory area is connected with a plurality of first through hole interconnection structures; in which, the process of forming the metal interconnection line generally includes a step of etching a dielectric layer to form an interconnection trench, and therefore, compared with a scheme of forming a metal interconnection line connecting a plurality of resistive memory cell structures in a first dielectric layer on the top of the resistive memory cell structure, the embodiment of the present invention increases the longitudinal distance from the first metal interconnection line to the resistive memory cell structure, thereby reducing the probability that the first dielectric layer between adjacent resistive memory cell structures is erroneously etched, or even the bottom of the interconnection trench for forming the first metal interconnection line exposes the sidewall of the adjacent resistive memory cell structure or the front metal interconnection structure, during the process of forming the first metal interconnection structure, so as to reduce the probability that the first metal interconnection line is short-circuited with the front metal interconnection structure or the adjacent resistive memory cell structure is short-circuited through the first metal interconnection line, thereby improving the performance of the semiconductor structure.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 5 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 5, a substrate (not shown) is provided, and includes a memory region 100b, a front layer metal interconnection structure 110 is formed in the substrate, the front layer metal interconnection structure 110 is exposed on a surface of the substrate, a plurality of resistive random access memory cell structures 300 are formed on the substrate of the memory region 100b, bottoms of the resistive random access memory cell structures 300 are connected to the front layer metal interconnection structure 110, and a first dielectric layer 200 covering the resistive random access memory cell structures 300 is formed on the substrate.

The substrate provides a process operation basis for subsequent processes. According to the actual process conditions, the base includes a substrate and a functional structure formed on the substrate, such as: the functional structure may include a semiconductor device such as a MOS field effect transistor, a resistive structure, and the like. In the present embodiment, the substrate includes a front dielectric layer 100, and a front metal interconnect structure 110 is located in the front dielectric layer 100. As an example, the top surface of the front dielectric layer 100 and the top surface of the front metal interconnect structure 110 are flush.

In this embodiment, the front dielectric layer 100 is an Inter Metal Dielectric (IMD) layer, and the front dielectric layer 100 is used for realizing electrical isolation between the front metal interconnection structures 110. The front dielectric layer 100 is made of a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the front dielectric layer 100 is made of an ultra-low k dielectric material, so as to reduce the parasitic capacitance between the back-end metal interconnection structures, thereby reducing the back-end RC delay. In particular, the ultra-low k dielectric material may be SiOCH.

In the present embodiment, the front metal interconnection structure 110 is a metal interconnection line in a back-end process. Specifically, the front-level metal interconnect structure 110 is a second-level metal interconnect line (i.e., M2 layer). In this embodiment, the material of the front metal interconnection structure 110 is Cu. The resistivity of Cu is low, which is beneficial to reducing RC delay (resistance-capacitance delay) of the device, and Cu has excellent electromigration resistance. In other embodiments, the material of the front-level metal interconnect structure may also be Al or W.

In the present embodiment, the substrate includes a memory region 100b for forming the RRAM device. In this embodiment, the substrate further includes a non-memory region 100a, and the non-memory region 100a is used to form other semiconductor devices besides RRAM devices, and the semiconductor devices include MOS devices. For example, the non-memory area 100a is a logic device area. The formation process of the RRAM device is compatible with the formation process of the conventional semiconductor device.

The resistive memory cell structure 300 is used to form a RRAM cell device. In this embodiment, the resistive random access memory cell structure 300 is formed on the substrate of the memory region 100b, so that the forming process of the RRAM device is compatible with the back end process in the forming process of the conventional semiconductor device. As an example, a plurality of resistive memory cell structures 300 are arranged in a matrix on a substrate, thereby forming a memory array. In this embodiment, the resistance change memory cell structure 300 includes a bottom electrode layer 310, a resistance change material layer 320, and a top electrode layer 330 stacked in sequence from bottom to top.

The bottom electrode layer 310 serves as the bottom electrode in the RRAM cell device. The material of the bottom electrode layer 310 includes one or more of TiN, TaN, Pt, AlCu, Au, Ti, Ta, W, WN, and Cu. As an example, the material of the bottom electrode layer 310 is TiN. In other embodiments, the material of the bottom electrode layer is TaN. The top electrode layer 330 serves as the top electrode in the RRAM cell device. As an example, the material of the top electrode layer 330 is TiN. For a detailed description of the material of the top electrode layer 330, reference may be made to the corresponding description of the bottom electrode layer 310, which is not repeated herein. The varistor layer 320 is varied between a high resistance state and a low resistance state according to a voltage applied to the varistor layer 320, thereby opening or blocking a current flow path and storing various information using the same. In this embodiment, the varistor material layer 320 is a metal oxide layer. Specifically, the material of the varistor material layer 320 includes one or more of hafnium oxide, tantalum oxide, and titanium oxide.

In this embodiment, the projection of the bottom electrode layer 310 on the substrate is located within the projection of the varistor layer 320 on the substrate, and the projection of the varistor layer 320 on the substrate coincides with the projection of the top electrode layer 330 on the substrate according to the device design requirements.

The first dielectric layer 200 is used to achieve electrical isolation between the resistive memory cell structures 300. The description of the first dielectric layer 200 can be combined with the corresponding description of the front dielectric layer 100, and will not be repeated herein.

In this embodiment, the resistive memory cell structure 300 is a stacked structure, and in order to reduce the difficulty of the process for forming the resistive memory cell structure 300, the first dielectric layer 200 is formed after the resistive memory cell structure 300 is formed. Therefore, in this embodiment, before forming the resistance change memory cell structure 300, the method further includes: a first sub-dielectric layer 210 is formed on the substrate.

Accordingly, the step of forming the resistive memory cell structure 300 includes: forming a bottom electrode layer 310 penetrating the first sub-dielectric layer 210; a stack of a varistor material layer 320 and a top electrode layer 330 is formed on the bottom electrode layer 310, the stack of the top electrode layer 330, the varistor material layer 320 and the bottom electrode layer 310 constituting the resistive memory cell structure 300. Specifically, a trench (not shown) exposing the top of the front-level metal interconnection structure 110 is formed in the first sub-dielectric layer 210, and then the bottom electrode layer 310 is formed in the trench.

In this embodiment, since the projection of the bottom electrode layer 310 on the substrate is located in the projection of the resistance change material layer 320 on the substrate, the process complexity of forming the resistance change memory cell structure 300 is reduced by forming the bottom electrode layer 310 in the first sub-dielectric layer 210. The first sub-dielectric layer 210 is used to provide a process foundation for the formation of the bottom electrode layers 310 and also to achieve electrical isolation between the bottom electrode layers 310. The description of the first sub-dielectric layer 210 can be combined with the corresponding description of the previous dielectric layer 100, and is not repeated herein.

In this embodiment, after forming the resistance change memory cell structure 300, the method further includes: the second sub-dielectric layer 220 is formed on the first sub-dielectric layer 210 exposed by the varistor material layer 320 and the top electrode layer 330, and the first sub-dielectric layer 210 and the second sub-dielectric layer 220 form the first dielectric layer 200 of the stacked structure. As an example, the second sub-dielectric layer 220 is formed through a deposition process and a planarization process (e.g., a chemical mechanical polishing process) sequentially performed such that the second sub-dielectric layer 220 has a flat top surface.

In other embodiments, when the projection of the bottom electrode layer on the substrate and the projection of the resistance variable material layer on the substrate coincide with each other, or the projection of the resistance variable material layer on the substrate is located in the projection of the bottom electrode layer on the substrate, the first dielectric layer may also be formed on the substrate exposed by the resistance variable memory cell structure after the resistance variable memory cell structure of the stacked structure is formed. At this time, the first dielectric layer is a single-layer structure.

In this embodiment, the RRAM device is formed in a back-end-of-line process, and thus the first dielectric layer 200 also covers the substrate of the non-memory region 100 a. The first dielectric layer 200 is also used to provide a process base for forming the metal interconnection structures in the non-memory region 100a and to achieve electrical isolation between the metal interconnection structures. In particular, the first dielectric layer 200 of the non-memory region 100a is used to provide a process base for subsequently forming a second metal interconnection structure electrically connected to the previous layer metal interconnection structure 110, and is used to achieve electrical isolation between the second metal interconnection structures of the non-memory region 100 a.

Referring to fig. 6 to 8 in combination, a first via (via) interconnection structure 530 is formed on the first dielectric layer 200 on top of the resistive memory cell structure 300 (as shown in fig. 8).

Subsequently forming a first metal interconnect structure electrically connected to the first via interconnect structures 530 in a second dielectric layer over the first dielectric layer 200, the first metal interconnect structure including a first metal interconnect line, and the first metal interconnect line of the memory region 100b being connected to the plurality of first via interconnect structures 530; in the method, the first through hole interconnection structure 530 is disposed between the resistive memory cell structure 300 and the first metal interconnection line, so as to increase a longitudinal distance from the first metal interconnection line to the resistive memory cell structure, thereby reducing a probability that the first dielectric layer 200 between adjacent resistive memory cell structures 300 is erroneously etched, even the bottom of the interconnection groove for forming the first metal interconnection line exposes the sidewall of the adjacent resistive memory cell structure 300 or the front metal interconnection structure 110, in a subsequent process of forming the first metal interconnection structure, thereby reducing a short circuit between the first metal interconnection line and the front metal interconnection structure 110, and forming an interconnection groove, Or the probability of short circuit of the adjacent resistive random access memory cell structures 300 through the first metal interconnection line, thereby improving the performance of the semiconductor structure. Wherein, the longitudinal direction refers to the direction of the normal of the substrate surface. Moreover, the first through hole interconnection structures 530 are connected with the resistive random access memory cell structures 300 in a one-to-one correspondence manner, and the lateral dimension of the first through hole interconnection structures 530 is generally smaller than that of the metal interconnection lines, so that the process of forming the first through hole interconnection structures 530 has a low probability of the first dielectric layer 200 between the adjacent resistive random access memory cell structures 300 being erroneously etched. Here, the lateral dimension refers to a dimension of the first via interconnection structure 530 in a direction parallel to the substrate surface, for example, the first via interconnection structure 530 is cylindrical, and the lateral dimension of the first via interconnection structure 530 is a diameter thereof.

In this embodiment, the forming process of the RRAM device is compatible with a back end process in a conventional semiconductor device forming process, and therefore, the forming method further includes: a second metal interconnection structure 500 (shown in fig. 8) electrically connected to the previous-layer metal interconnection structure 110 is formed in the first dielectric layer 200 of the non-memory region 100a, and the second metal interconnection structure 500 includes a second via interconnection structure 510 and a second metal interconnection line 520 located on top of the second via interconnection structure 510. In this embodiment, the second metal interconnection line 520 is a third metal interconnection line (i.e., M3 layer) in the back end of line.

It should be noted that, in the present embodiment, the first via interconnection structure 530 is formed only in the first dielectric layer 200 on the top of the resistive random access memory cell structure 300, and the formation of the first via interconnection structure 530 has little influence on the conventional back end of line process and the second metal interconnection structure 500. For example, the overall height of the second metal interconnect structure 500 can still meet performance requirements.

In this embodiment, in order to simplify the process steps, the second metal interconnection structure 500 and the first via interconnection structure 530 are formed in the same process. Specifically, the step of forming the first via interconnection structure 530 and the second metal interconnection structure 500 includes: a first interconnect opening 400 (shown in fig. 7) is formed in the first dielectric layer 200 in the non-memory region 100a, including a first interconnect via 410 and a first interconnect trench 420 communicating with the top of the first interconnect via 410, and in the step of forming the first interconnect via 410, the first interconnect via 410 is also formed in the first dielectric layer 200 on the top of the resistive memory cell structure 300. In the same step, the first interconnection via 410 is formed in the first dielectric layer 200 of the non-memory region 100a and the memory region 100b, thereby simplifying the process steps and improving the process compatibility of the RRAM formation process and the back-end process.

The first interconnect opening 400 of the non-memory region 100a is used to provide a spatial location for the subsequent formation of the second metal interconnect structure, and the first interconnect via 410 of the memory region 100b is used to provide a spatial location for the subsequent formation of the first via interconnect structure. In the present embodiment, the first interconnect via 410 of the non-memory region 100a and the first interconnect via 410 of the memory region 100b are located at different positions in the first dielectric layer 200 in the longitudinal direction, and therefore, in order to reduce the difficulty of the process for forming the first interconnect opening 400, the first interconnect opening 400 is formed in a manner of forming a via (via first), that is, after the first interconnect via 410 is formed, the first interconnect trench 420 is formed. As shown in fig. 6, the first dielectric layer 200 is etched using an anisotropic dry etch process to form a first interconnect via 410. By selecting an anisotropic dry etching process, the topography quality and the dimensional accuracy of the first interconnect via 410 are improved.

In this embodiment, the front metal interconnection structure 110 is exposed at the bottom of the first interconnection via 410 of the non-memory region 100a, and the resistive random access memory cell structure 300 is exposed at the bottom of the first interconnection via 410 of the memory region 100 b.

It should be noted that, in the process of etching the first dielectric layer 220, the etching amount of the first dielectric layer 220 in the non-memory region 100a is greater than the etching amount of the first dielectric layer 220 in the memory region 100b, the top electrode layer 330 is exposed first, but the material of the top electrode layer 330 contains metal, the etching selectivity between the first dielectric layer 220 and the top electrode layer 330 is relatively large, and the first dielectric layer 220 is less damaged by the etching process.

As shown in fig. 7, after the first interconnection via 410 is formed, a protection layer (not shown) is filled in the first interconnection via 410 for protecting the front-layer metal interconnection structure 110 and the resistive random access memory cell structure 300 at the bottom of the first interconnection via 410; after forming the protective layer, etching a part of the thickness of the first dielectric layer 200 around the first interconnection via 410 in the non-memory region 100a to form a first interconnection groove 420 communicating with the first interconnection via 410; and removing the protective layer.

As shown in fig. 8, the first interconnection trench 420 (shown in fig. 7) and the first interconnection via 410 (shown in fig. 7) are filled, a first via interconnection structure 530 is formed in the first interconnection via 410 of the memory region 100b, and a second metal interconnection structure 500 is formed in the first interconnection opening 400, including the second via interconnection structure 510 located in the first interconnection via 410 and the second metal interconnection line 520 located in the first interconnection trench 420.

Specifically, after the first interconnection trench 420 and the first interconnection via 410 are filled with a conductive material, the conductive material is planarized to form the second metal interconnection 500 and the first via interconnection structure 530 having a top surface level with the first dielectric layer 200.

In this embodiment, the second metal interconnection structure 500 and the first via interconnection structure 530 are both made of Cu. The detailed description of the second metal interconnection structure 500 and the first via interconnection structure 530 may be combined with the corresponding description of the previous layer metal interconnection structure 110, and will not be repeated herein.

In other embodiments, the second metal interconnection structure and the first via interconnection structure may also be formed in different process steps according to process requirements, for example, the first via interconnection structure is formed after the second metal interconnection structure is formed, or the second metal interconnection structure is formed after the first via interconnection structure is formed.

Referring to fig. 9, a second dielectric layer 600 is formed on the first dielectric layer 200.

The second dielectric layer 600 is used to provide a process base for the subsequent formation of the first metal interconnection structures, and is also used to realize electrical isolation between the first metal interconnection structures. Specifically, the second dielectric layer 600 covers the second metal interconnection structure 500 and the first via interconnection structure 530.

In the present embodiment, the second dielectric layer 600 covers not only the first dielectric layer 200 of the memory region 100b, but also the first dielectric layer 200 of the non-memory region 100a, so as to facilitate the back-end process of the conventional semiconductor process. In the back end of the conventional semiconductor process, each dielectric layer is used to form a metal interconnection structure.

It should be noted that, no protrusion structure is formed on the first dielectric layer 200, which is beneficial to avoiding the problem of poor gap filling capability of the second dielectric layer 600, the top surface of the second dielectric layer 600 has high flatness, and the probability of void (void) defects in the second dielectric layer 600 is low. The description of the second dielectric layer 600 can be combined with the corresponding description of the previous dielectric layer 100, and is not repeated herein.

Referring to fig. 10 to 12 in combination, a first metal interconnection structure 800 electrically connected to the first via interconnection structure 530 is formed in the second dielectric layer 600 on top of the resistive memory cell structure 300, the first metal interconnection structure including a first metal interconnection line 820. Wherein, in the memory area 100b, the first metal interconnection lines 820 electrically connect the plurality of first via interconnection structures 530.

The first metal interconnection structure 800 in the memory area 100b is used to electrically connect the resistive memory cell structure 300 with other circuits. In the memory area 100b, a plurality of resistive memory cell structures 300 are arranged in a matrix on a substrate to form a memory array, and thus, the first metal interconnection lines 820 extend in a row direction or a column direction of the matrix and are connected to the plurality of first via interconnection structures 530.

In this embodiment, the first metal interconnection line 820 is a fourth metal interconnection line (i.e., M4 layer) in the back end of line process. As an example, the first metal interconnection line 820 of the memory area 100b is used as a word line (BL) of the memory array.

In this embodiment, the first metal interconnection structure 800 is further formed in the second dielectric layer 600 on top of the second metal interconnection structure 500 of the non-memory region 100a, and the first metal interconnection structure 800 further includes a third via interconnection structure 810 located at the bottom of the first metal interconnection line 820. Correspondingly, in the memory area 100b, the third via interconnection structures 810 are connected to the resistance change memory cell structures 300 in a one-to-one correspondence manner, and the first metal interconnection line 820 is connected to the plurality of third via interconnection structures 810.

In this embodiment, the first metal interconnection structure 800 is formed in the second dielectric layer 600 of the memory region 100b and the non-memory region 100a, that is, the forming method of this embodiment adopts a forming process of a conventional back end of line process, so that the first metal interconnection structure 800 of the memory region 100b is electrically connected to the first via interconnection structure 530, thereby making the forming process of the RRAM device compatible with the back end of line process and having little influence on the conventional back end of line process. For example, the overall height of the second metal interconnect structure 500 of the non-memory region 100a can still meet its performance requirements. Moreover, not only the first through hole interconnection structure 530 but also the third through hole interconnection structure 810 are arranged between the first metal interconnection line 820 and the resistive memory cell structure 300, so that the longitudinal distance from the first metal interconnection line 820 to the resistive memory cell structure 300 is further increased, and the probability that the first metal interconnection line 820 and the front layer metal interconnection structure 110 are short-circuited or the adjacent resistive memory cell structure 300 is short-circuited through the first metal interconnection line 820 is further reduced.

In the longitudinal direction, the greater the number of layers of the through hole interconnection structures disposed between the first metal interconnection line 820 and the resistive memory cell structure 300, the greater the longitudinal distance from the first metal interconnection line 820 to the resistive memory cell structure 300, and the lower the probability that the first metal interconnection line 820 and the previous metal interconnection structure 110 are short-circuited or the adjacent resistive memory cell structure 300 is short-circuited through the first metal interconnection line 820. However, since the lateral dimension of the via interconnection structure is generally small, the greater the number of layers of the via interconnection structure in the longitudinal direction, the greater the difficulty in accurately controlling the alignment shift (overlay shift), so that the reliability of the electrical connection between the first metal interconnection line 820 and the resistive memory cell structure 300 is easily reduced.

Therefore, in this embodiment, only the first through hole interconnection structure 530 and the third through hole interconnection structure 810 are disposed between the first metal interconnection line 820 and the resistive memory cell structure 300, which is beneficial to improving the alignment accuracy of the first through hole interconnection structure 530 and the third through hole interconnection structure 810, and is further beneficial to ensuring the reliability of the electrical connection between the first metal interconnection line 820 and the resistive memory cell structure 300. Moreover, the longitudinal distance from the first metal interconnection line 820 to the resistive memory cell structure 300 is not too large, so that the signal transmission rate is increased.

In other embodiments, the number of layers of the via interconnection structure between the first metal interconnection line and the resistive memory cell structure in the longitudinal direction may also be more than two, depending on the process conditions. For example, the first metal interconnection line is a fifth metal interconnection line (i.e., M5 layer) in a back-end process, and accordingly, a three-layer through-hole interconnection structure is disposed between the first metal interconnection line and the resistive random access memory cell structure.

Specifically, the step of forming the first metal interconnection structure 800 includes: as shown in fig. 11, a second interconnection opening 730 is formed in the second dielectric layer 600, including a second interconnection via 710 and a second interconnection groove 720 communicating with the top of the second interconnection via 710, and the second interconnection groove 720 of the memory region 100b communicates with the plurality of second interconnection vias 710; as shown in fig. 12, the second interconnect opening 730 is filled to form the first metal interconnect structure 800, including the third via interconnect structure 810 in the second interconnect via 710 and the first metal interconnect line 820 in the second interconnect trench 720.

In this embodiment, the second metal interconnection structure 500 is exposed at the bottom of the second interconnection opening 730 in the non-memory area 100a, the first via interconnection structure 530 is exposed at the bottom of the second interconnection opening 730 in the memory area 100b, such that the first metal interconnection structure 800 in the non-memory area 100a is electrically connected to the second metal interconnection structure 500, and the first metal interconnection structure 800 in the memory area 100b is electrically connected to the first via interconnection structure 530.

As an example, the second interconnection opening 730 is formed in such a manner that a via first (via first) is formed, that is, the second interconnection groove 720 is formed after the second interconnection via 710 is formed. Specifically, as shown in fig. 10, the second dielectric layer 600 is etched to form a plurality of second interconnect vias 710 penetrating the second dielectric layer 600; after the second interconnection via 710 is formed, filling a protection layer in the second interconnection via 710 for protecting the second metal interconnection structure 500 and the first via interconnection structure 530 at the bottom of the second interconnection via 710; as shown in fig. 11, after forming the protective layer, etching a portion of the thickness of the second dielectric layer 600 around the second interconnect via 710 to form a second interconnect trench 720 in the second dielectric layer 600; and removing the protective layer. In other embodiments, the second interconnect opening may also be formed by forming the interconnect trench (trench first) first, that is, after forming the second interconnect trench, forming the second interconnect via. In other embodiments, the second interconnect opening may be formed by an All In One (AIO) etching process, where the AIO etching process is performed by etching the interconnect via and etching the interconnect trench in the same process step.

In this embodiment, after the second interconnect opening 730 is filled with a conductive material, the conductive material is planarized to form the first metal interconnect structure 800 having a top surface flush with the second dielectric layer 600. In this embodiment, the material of the first metal interconnection structure 800 is Cu. The specific description of the first metal interconnect structure 800 can be combined with the corresponding description of the previous metal interconnect structure 110, and is not repeated herein.

In this embodiment, the plurality of resistive memory cell structures 300 are arranged in a matrix to form a memory array, and therefore, in the memory area 100b, the second interconnection trenches 720 extend in a row direction or a column direction of the matrix, and therefore, the second interconnection trenches 720 cross the plurality of resistive memory cell structures 300.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: in the same step, the first via interconnection structure 530b and the first metal interconnection structure 800b are formed.

Referring to fig. 13, after forming a plurality of resistive memory cell structures 300b on a substrate (not labeled) of a memory region 100f and a first dielectric layer 200b covering the resistive memory cell structures 300b, a second metal interconnection structure 500b electrically connected to a front layer metal interconnection structure (not labeled) is formed in the first dielectric layer 200b of a non-memory region 100 e; after forming the second metal interconnection structure 500b, a second dielectric layer 600b is formed on the first dielectric layer 200 b.

In this embodiment, the second metal interconnection structure 500b includes a second via interconnection structure 510b and a second metal interconnection line 520b located on top of the second via interconnection structure 510 b.

Referring to fig. 14 to 16 in combination, a first metal interconnection structure 800b is formed in the second dielectric layer 600b of the non-memory region 100e and the memory region 100f, and a first via interconnection structure 530b is formed in the first dielectric layer 200b at the bottom of the first metal interconnection structure 800b of the memory region 100 f. The first metal interconnection structures 800b in the non-memory region 100e are connected to the second metal interconnection structures 500b, and the first via interconnection structures 530b are connected to the resistive random access memory cell structures 300b in a one-to-one correspondence manner.

Specifically, the step of forming the first via interconnection structure 530b and the first metal interconnection structure 800b includes:

referring to fig. 14 and 15 in combination, a second interconnect opening 730b is formed in the second dielectric layer 600b on top of the second metal interconnect structure 500b, and the first dielectric layer 200b and the second dielectric layer 600b on top of the resistive memory cell structure 300b, including a second interconnect via 710b and a second interconnect trench 720b in communication with the top of the second interconnect via 710b, and the second interconnect trench 720b of the memory region 100f is in communication with the plurality of second interconnect vias 710 b.

In this embodiment, the second interconnect trench 720b is located in a partial thickness of the second dielectric layer 600 b. In the memory region 100f, the portion of the second interconnect via 710b in the first dielectric layer 200b is used to provide a spatial location for the subsequent formation of the first via interconnect structure.

In this embodiment, the second interconnection opening 730b is formed in such a manner that a via hole (via first) is formed first, that is, after the second interconnection via 710b is formed, the second interconnection groove 720b is formed. In the non-memory region 100a, not only the second dielectric layer 600b but also the first dielectric layer 200b need to be etched, and thus, by adopting the via first process, it is advantageous to reduce the difficulty of the process for forming the first interconnect opening 400.

Specifically, as shown in fig. 14, the second dielectric layer 600b and the first dielectric layer 200b are etched to form a plurality of second interconnect vias 710b, the second interconnect vias 710b of the non-memory region 100e penetrate through the second dielectric layer 600b on the top of the second metal interconnect structure 500b, and the second interconnect vias 710b of the memory region 100f penetrate through the second dielectric layer 600b and the first dielectric layer 200b on the top of the resistive random access memory cell structure 300 b; after the second interconnection through hole 710b is formed, filling a protective layer in the second interconnection through hole 710b for protecting the second metal interconnection structure 500b and the resistive random access memory cell structure 300b at the bottom of the second interconnection through hole 710 b; as shown in fig. 15, after forming the protection layer, the second dielectric layer 600b is etched to a partial thickness around the second interconnection via 710b, and a second interconnection groove 720b is formed in the second dielectric layer 600 b; and removing the protective layer.

It should be noted that, during the etching process of the first dielectric layer 220b, the second metal interconnection structure 500b of the non-memory region 100e is exposed, but the material of the second metal interconnection structure 500b is a metal material, and the etching selectivity of the first dielectric layer 220b and the second metal interconnection structure 500b is higher, so that the second metal interconnection structure 500b is less damaged by the etching process.

Referring to fig. 16, the second interconnect opening 730b is filled (as shown in fig. 15), a first via interconnect structure 530b is formed in the second interconnect opening 730b located in the first dielectric layer 200b, and a first metal interconnect structure 800b is formed in the remaining second interconnect opening 730b, wherein the first metal interconnect structure 800b includes a first metal interconnect line 820b located in the second interconnect trench 720b and a third via interconnect structure 810b located in the remaining second interconnect via 710 b.

For the specific description of the forming method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.

Correspondingly, the invention also provides a semiconductor structure. With continued reference to fig. 12, a schematic diagram of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate (not labeled) including a memory region 100b, wherein a front-level metal interconnection structure 110 is formed in the substrate, and the front-level metal interconnection structure 110 is exposed on the surface of the substrate; the resistive random access memory comprises a plurality of resistive random access memory cell structures 300, a plurality of first metal interconnection structures 110 and a plurality of second metal interconnection structures, wherein the resistive random access memory cell structures 300 are positioned on a substrate of a memory area 100 b; a first dielectric layer 220 on the substrate and covering the resistive memory cell structure 300; a first via interconnection structure 530 penetrating the first dielectric layer 200 on the top of the resistive memory cell structure 300; a second dielectric layer 600 on the first dielectric layer 200; a first metal interconnection structure 800 in the second dielectric layer 600 on top of the resistive memory cell structure 300 and electrically connected to the first via interconnection structure 530, the first metal interconnection structure 800 including a first metal interconnection line 820; wherein, in the memory area 100b, the first metal interconnection lines 820 electrically connect the plurality of first via interconnection structures 530.

The first metal interconnection structure 800 is located in the second dielectric layer 600 on the top of the resistive memory cell structure 300 and electrically connected to the first via interconnection structure 530, the first metal interconnection structure 800 includes a first metal interconnection line 820, wherein the process of forming the metal interconnection line generally includes a step of etching the dielectric layer to form an interconnection trench, and thus, compared with a scheme of forming a metal interconnection line connecting a plurality of resistive memory cell structures in the first dielectric layer on the top of the resistive memory cell structure, the present embodiment provides the first via interconnection structure 530 between the resistive memory cell structure 300 and the first metal interconnection line 820, and increases the longitudinal distance from the first metal interconnection line 820 to the resistive memory cell structure 300, thereby reducing the mis-etched first dielectric layer 200 between adjacent resistive memory cell structures 300 during the process of forming the first metal interconnection structure 800, Even the probability that the bottom of the interconnection groove for forming the first metal interconnection line 820 exposes the side wall of the adjacent resistive random access memory cell structure 300 or the front layer metal interconnection structure 110 can be reduced, so that the probability that the first metal interconnection line 820 and the front layer metal interconnection structure 110 are short-circuited or the adjacent resistive random access memory cell structure 300 is short-circuited through the first metal interconnection line 820 can be reduced, and the performance of the semiconductor structure can be improved.

Moreover, the first via interconnection structures 530 are connected to the resistive memory cell structures 300 in a one-to-one correspondence, and the lateral dimension of the first via interconnection structures 530 is generally smaller than that of the metal interconnection lines, so that the process of forming the first via interconnection structures 530 has a low probability of the first dielectric layer 200 between the adjacent resistive memory cell structures 300 being mis-etched.

According to the actual process conditions, the base includes a substrate and a functional structure formed on the substrate, for example: the functional structure may include a semiconductor device such as a MOS field effect transistor, a resistive structure, and the like. In the present embodiment, the substrate includes a front dielectric layer 100, and a front metal interconnect structure 110 is located in the front dielectric layer 100. As an example, the top surface of the front dielectric layer 100 and the top surface of the front metal interconnect structure 110 are flush.

In this embodiment, the front dielectric layer 100 is an inter-metal dielectric layer, and the front dielectric layer 100 is used to achieve electrical isolation between the front metal interconnection structures 110. The front dielectric layer 100 is made of a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or the like.

In the present embodiment, the front metal interconnection structure 110 is a metal interconnection line in a back-end process. Specifically, the front-level metal interconnect structure 110 is a second-level metal interconnect line (i.e., M2 layer). In this embodiment, the material of the front metal interconnection structure 110 is Cu. The resistivity of Cu is low, so that the RC delay of the device is reduced, and the Cu has excellent electromigration resistance. In other embodiments, the material of the front-level metal interconnect structure may also be Al or W.

In this embodiment, the substrate further includes a non-memory region 100a for forming other semiconductor devices than the RRAM device, including a MOS device. For example, the non-memory area 100a is a logic device area.

The resistive memory cell structure 300 is used to form a RRAM cell device. The resistive memory cell structure 300 is located on the substrate of the memory region 100b, so that the forming process of the RRAM device is compatible with the back end process in the forming process of the conventional semiconductor device. As an example, a plurality of resistive memory cell structures 300 are arranged in a matrix on the substrate to form a memory array.

In this embodiment, the resistance change memory cell structure 300 includes a bottom electrode layer 310, a resistance change material layer 320, and a top electrode layer 330 stacked in sequence from bottom to top.

The bottom electrode layer 310 serves as the bottom electrode in the RRAM cell device. The material of the bottom electrode layer 310 includes one or more of TiN, TaN, Pt, AlCu, Au, Ti, Ta, W, WN, and Cu. As an example, the material of the bottom electrode layer 310 is TiN. In other embodiments, the material of the bottom electrode layer is TaN.

The top electrode layer 330 serves as the top electrode in the RRAM cell device. As an example, the material of the top electrode layer 330 is TiN. For a detailed description of the material of the top electrode layer 330, reference may be made to the corresponding description of the bottom electrode layer 310, and further description is omitted here.

The varistor layer 320 is varied between a high resistance state and a low resistance state according to a voltage applied to the varistor layer 320, thereby opening or blocking a current flow path and storing various information using the same. In this embodiment, the varistor material layer 320 is a metal oxide layer. Specifically, the material of the varistor material layer 320 includes one or more of hafnium oxide, tantalum oxide, and titanium oxide.

The first dielectric layer 200 is used to achieve electrical isolation between the resistive memory cell structures 300. For the description of the first dielectric layer 200, reference may be made to the corresponding description of the front dielectric layer 100, which is not repeated herein.

In this embodiment, in order to reduce the difficulty of the process for forming the resistive memory cell structure 300, the first dielectric layer 200 is formed after the resistive memory cell structure 300 is formed. Thus, in the present embodiment, the first dielectric layer 200 includes: a first sub-dielectric layer 210 on the substrate at the side of the bottom electrode layer 310; the second sub-dielectric layer 220, the potential variable resistance material layer 320 and the top electrode layer 330 are exposed on the first sub-dielectric layer 210.

In this embodiment, the RRAM device is formed in a back-end-of-line process, and thus the first dielectric layer 200 also covers the substrate of the non-memory region 100 a. The first dielectric layer 200 is also used to provide a process base for forming the metal interconnection structures in the non-memory region 100a and to achieve electrical isolation between the metal interconnection structures.

In this embodiment, the forming process of the RRAM device is compatible with the back end of line process in the conventional semiconductor process, and therefore the semiconductor structure further includes: and a second metal interconnection structure 500 penetrating the first dielectric layer 200 of the non-memory region 100a and electrically connected to the previous-layer metal interconnection structure 110, the second metal interconnection structure 500 including a second via interconnection structure 510 and a second metal interconnection line 520 on top of the second via interconnection structure 510. In this embodiment, the second metal interconnection line 520 is a third metal interconnection line in a back-end process.

It should be noted that, in the present embodiment, the first via interconnection structure 530 is only disposed in the first dielectric layer 200 on the top of the resistive random access memory cell structure 300, and the formation of the first via interconnection structure 530 has little influence on the conventional back end of line process and the second metal interconnection structure 500. For example, the overall height of the second metal interconnect structure 500 can still meet performance requirements. In this embodiment, the material of the second metal interconnection structure 500 and the first via interconnection structure 530 are both Cu. Specific descriptions of the second metal interconnection structure 500 and the first via interconnection structure 530 may be combined with the corresponding descriptions of the previous layer metal interconnection structure 110, and are not repeated herein.

The second dielectric layer 600 is used to provide a process base for forming the first metal interconnection structures 800 and also used to achieve electrical isolation between the first metal interconnection structures 800. Specifically, the second dielectric layer 600 covers the second metal interconnection structure 500 and the first via interconnection structure 530.

It should be noted that, no protrusion structure is formed on the first dielectric layer 200, which is beneficial to avoiding the problem of poor gap filling capability of the second dielectric layer 600, the top surface of the second dielectric layer 600 has high flatness, and the probability of having a hole defect in the second dielectric layer 600 is low. The description of the second dielectric layer 600 can be combined with the corresponding description of the previous dielectric layer 100, and is not repeated herein.

The first metal interconnection structure 800 in the memory area 100b is used to electrically connect the resistive memory cell structure 300 with other circuits. In the present embodiment, in the memory area 100b, the first metal interconnection lines 820 connect the plurality of first via interconnection structures 530. Specifically, in the memory region 100b, a plurality of resistive memory cell structures 300 are arranged in a matrix on a substrate to form a memory array, and thus, the first metal interconnection lines 820 extend in a row direction or a column direction of the matrix and are connected to the plurality of first via interconnection structures 530, and the first metal interconnection lines 820 cross the plurality of resistive memory cell structures 300.

In this embodiment, the first metal interconnection line 820 is a fourth-layer metal interconnection line in a back-end process. As an example, the first metal interconnection lines 820 of the memory area 100b are used as word lines of the memory array.

In this embodiment, the first metal interconnection structure 800 is further located in the second dielectric layer 600 on top of the second metal interconnection structure 500 of the non-memory region 100a, and the first metal interconnection structure 800 further includes a third via interconnection structure 810 located at the bottom of the first metal interconnection line 820. Correspondingly, in the memory area 100b, the third via interconnection structures 810 are connected to the resistance change memory cell structures 300 in a one-to-one correspondence manner, and the first metal interconnection line 820 is connected to the plurality of third via interconnection structures 810.

In this embodiment, the first metal interconnection structure 800 is located in the second dielectric layer 600 of the memory region 100b and the non-memory region 100a, i.e. the forming method of the semiconductor structure is compatible with the back-end process of the conventional semiconductor process, so that the first metal interconnection structure 800 of the memory region 100b is electrically connected to the first via interconnection structure 530, thereby making the forming process of the RRAM device compatible with the back-end process and having little influence on the conventional back-end process. For example, the overall height of the second metal interconnect structure 500 of the non-memory region 100a can meet its performance requirements. Moreover, not only the first through hole interconnection structure 530 but also the third through hole interconnection structure 810 are arranged between the first metal interconnection line 820 and the resistive memory cell structure 300, so that the longitudinal distance from the first metal interconnection line 820 to the resistive memory cell structure 300 is further increased, and the probability that the first metal interconnection line 820 and the previous layer metal interconnection structure 110 are short-circuited or the adjacent resistive memory cell structure 300 is short-circuited through the first metal interconnection line 820 is further reduced.

In the longitudinal direction, the greater the number of layers of the through hole interconnection structures disposed between the first metal interconnection line 820 and the resistive memory cell structure 300, the greater the longitudinal distance from the first metal interconnection line 820 to the resistive memory cell structure 300, and the lower the probability that the first metal interconnection line 820 and the previous metal interconnection structure 110 are short-circuited or the adjacent resistive memory cell structure 300 is short-circuited through the first metal interconnection line 820. However, since the lateral dimension of the via interconnection structure is generally small, the greater the number of layers of the via interconnection structure in the longitudinal direction, the greater the difficulty in accurately controlling the alignment deviation, so that the reliability of the electrical connection between the first metal interconnection line 820 and the resistive memory cell structure 300 is easily reduced. Therefore, in this embodiment, only the first through hole interconnection structure 530 and the third through hole interconnection structure 810 are disposed between the first metal interconnection line 820 and the resistive memory cell structure 300, which is beneficial to improving the alignment accuracy of the first through hole interconnection structure 530 and the third through hole interconnection structure 810, and is further beneficial to ensuring the reliability of the electrical connection between the first metal interconnection line 820 and the resistive memory cell structure 300. Moreover, this allows the longitudinal distance from the first metal interconnection line 820 to the resistive memory cell structure 300 not to be too large, thereby increasing the rate of signal transmission. In other embodiments, the number of layers of the via interconnection structure between the first metal interconnection line and the resistive memory cell structure in the longitudinal direction may be more than two, depending on the process conditions. For example, the first metal interconnection line is a fifth metal interconnection line (i.e., M5 layer) in a back-end process, and accordingly, a three-layer through-hole interconnection structure is disposed between the first metal interconnection line and the resistive memory cell structure.

In this embodiment, the material of the first metal interconnection structure 800 is Cu. The detailed description of the first metal interconnect structure 800 can be combined with the corresponding description of the previous metal interconnect structure 110, and is not repeated herein.

The semiconductor structure described in this embodiment may be formed by using the formation method described in the first embodiment, may be formed by using the formation method described in the second embodiment, and may be formed by using other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a memory area, a front-layer metal interconnection structure is formed in the substrate, the front-layer metal interconnection structure is exposed out of the surface of the substrate, a plurality of resistance change memory unit structures are formed on the substrate of the memory area, the bottoms of the resistance change memory unit structures are connected with the front-layer metal interconnection structure, and a first dielectric layer covering the resistance change memory unit structures is formed on the substrate;

forming a first through hole interconnection structure in a first dielectric layer on the top of the resistive random access memory unit structure;

forming a second dielectric layer on the first dielectric layer;

forming a first metal interconnection structure electrically connected with the first through hole interconnection structure in a second dielectric layer on the top of the resistive random access memory unit structure, wherein the first metal interconnection structure comprises a first metal interconnection line;

wherein, in the memory region, the first metal interconnection line connects a plurality of the first via interconnection structures.

2. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises a non-memory region;

the forming method further includes: and forming a second metal interconnection structure connected with the front-layer metal interconnection structure in the first dielectric layer of the non-memory area, wherein the second metal interconnection structure comprises a second through hole interconnection structure and a second metal interconnection line positioned at the top of the second through hole interconnection structure.

3. The method of forming a semiconductor structure of claim 2, wherein in the step of forming the first metal interconnect structure, the first metal interconnect structure is further formed in a second dielectric layer on top of a second metal interconnect structure of the non-memory region, the first metal interconnect structure further comprising a third via interconnect structure at a bottom of the first metal interconnect line;

in the memory area, the third via interconnection structures are connected with the resistive random access memory unit structures in a one-to-one correspondence manner, and the first metal interconnection line is connected with the plurality of third via interconnection structures.

4. The method of forming a semiconductor structure of claim 2, wherein the step of forming the first via interconnect structure and the second metal interconnect structure comprises:

forming a first interconnection opening exposing the front-layer metal interconnection structure in the first dielectric layer in the non-memory region, wherein the first interconnection opening comprises a first interconnection through hole and a first interconnection groove communicated with the top of the first interconnection through hole, and in the step of forming the first interconnection through hole, the first interconnection through hole is also formed in the first dielectric layer on the top of the resistive random access memory unit structure;

and filling the first interconnection groove and the first interconnection through hole, forming a first through hole interconnection structure in the first interconnection through hole of the memory area, and forming a second metal interconnection structure in the first interconnection opening of the non-memory area, wherein the second through hole interconnection structure is positioned in the first interconnection through hole and the second metal interconnection line is positioned in the first interconnection groove.

5. The method of forming a semiconductor structure of claim 4, wherein the first interconnect trench is formed after the first interconnect via is formed.

6. The method of forming a semiconductor structure of claim 3, wherein forming the first metal interconnect structure comprises:

forming a second interconnection opening in the second dielectric layer, wherein the second interconnection opening comprises a second interconnection through hole and a second interconnection groove communicated with the top of the second interconnection through hole, and the second interconnection groove of the memory area is communicated with a plurality of second interconnection through holes;

and filling the second interconnection opening to form a first metal interconnection structure which comprises a third through hole interconnection structure positioned in the second interconnection through hole and a first metal interconnection line positioned in the second interconnection groove.

7. The method of forming a semiconductor structure of claim 3, wherein the first via interconnect structure and the first metal interconnect structure are formed in the same step, the step of forming the first via interconnect structure and the first metal interconnect structure comprising:

forming a second interconnection opening in the second dielectric layer on the top of the second metal interconnection structure and the first dielectric layer and the second dielectric layer on the top of the resistive random access memory unit structure, wherein the second interconnection opening comprises a second interconnection through hole and a second interconnection groove communicated with the top of the second interconnection through hole, and the second interconnection groove of the memory area is communicated with the plurality of second interconnection through holes;

and filling the second interconnection opening, forming a first through hole interconnection structure in the second interconnection opening positioned in the first dielectric layer, and forming a first metal interconnection structure in the rest of the second interconnection openings, wherein the first metal interconnection structure comprises a first metal interconnection line positioned in the second interconnection groove and a third through hole interconnection structure positioned in the rest of the second interconnection through holes.

8. The method of forming a semiconductor structure of claim 7, wherein the second interconnect trench is formed after forming the second interconnect via.

9. The method for forming a semiconductor structure according to claim 1, wherein the resistive memory cell structure includes a bottom electrode layer, a resistive material layer, and a top electrode layer, which are sequentially stacked from bottom to top.

10. The method for forming a semiconductor structure according to claim 1, wherein the first dielectric layer is formed after the resistive memory cell structure is formed.

11. The method for forming a semiconductor structure according to claim 10, wherein before forming the resistive memory cell structure, the method further comprises: forming a first sub-dielectric layer on the substrate;

the step of forming the resistive random access memory cell structure comprises the following steps: forming a bottom electrode layer penetrating through the first sub-dielectric layer; forming a stacked varistor material layer and a top electrode layer on the bottom electrode layer, wherein the stacked top electrode layer, the varistor material layer and the bottom electrode layer form a resistive random access memory unit structure;

after the resistive random access memory unit structure is formed, the method further comprises the following steps: and forming a second sub-dielectric layer on the exposed first sub-dielectric layer of the varistor material layer and the exposed top electrode layer, wherein the first sub-dielectric layer and the second sub-dielectric layer form the first dielectric layer.

12. A semiconductor structure, comprising:

the memory device comprises a substrate, a memory area, a first-layer metal interconnection structure and a second-layer metal interconnection structure, wherein the first-layer metal interconnection structure is formed in the substrate, and the first-layer metal interconnection structure is exposed on the surface of the substrate;

the resistive random access memory unit structures are positioned on the substrate of the memory area, and the bottoms of the resistive random access memory unit structures are connected with the front-layer metal interconnection structure;

the first dielectric layer is positioned on the substrate and covers the resistive random access memory unit structure;

the first through hole interconnection structure penetrates through the first dielectric layer on the top of the resistive random access memory unit structure;

a second dielectric layer on the first dielectric layer;

the first metal interconnection structure penetrates through the second dielectric layer on the top of the resistive random access memory unit structure and is electrically connected with the first through hole interconnection structure, and the first metal interconnection structure comprises a first metal interconnection line;

13. The semiconductor structure of claim 12, wherein the substrate further comprises a non-memory region;

the semiconductor structure further includes: and the second metal interconnection structure is positioned in the first dielectric layer of the non-memory area and is connected with the front-layer metal interconnection structure, and comprises a second through hole interconnection structure and a second metal interconnection line positioned at the top of the second through hole interconnection structure.

14. The semiconductor structure of claim 13, wherein the first metal interconnect structure further extends through a second dielectric layer on top of a second metal interconnect structure of the non-memory region, the first metal interconnect structure further comprising a third via interconnect structure located at a bottom of the first metal interconnect line;

15. The semiconductor structure of claim 12, wherein the resistive memory cell structure comprises a bottom electrode layer, a resistive material layer, and a top electrode layer stacked in this order from bottom to top.

16. The semiconductor structure of claim 15, wherein the first dielectric layer comprises:

a first sub-dielectric layer on the substrate at the side of the bottom electrode layer;

and the second sub-dielectric layer is positioned on the first sub-dielectric layer exposed by the variable resistance material layer and the top electrode layer.