CN1138629C - multilayer substrate - Google Patents

Abstract

To provide a module whose thickness does not increase even if a semiconductor device is mounted. The semiconductor device 47 is accommodated in the accommodation portion 57 of the laminated substrate 10a on the side of the container, the bonding land 42 of the semiconductor device 47 is brought into contact with the bump 16a exposed on the bottom surface of the accommodation portion 57, heated and pressed, The adhesive layer on the housing part 57 is melted, the semiconductor device is attached to the laminated substrate 10a on the container side, and then the laminated substrate 6b on the lid side is electrically and mechanically connected to the laminated substrate on the container side. 10a on.

Description

multilayer substrate

The present invention relates to the technical field of multilayer substrates, and particularly relates to the technical field of multilayer substrates suitable for mounting semiconductor devices such as integrated circuits.

Hitherto, as a multilayer substrate on which semiconductor devices such as integrated circuits are mounted, a multilayer substrate having a high degree of freedom of wiring has been used. Reference numeral 106 in FIG. 9A is a multilayer substrate, which is formed by laminating a plurality of single-layer substrates 101 .

Each single-layer substrate 101 has a base film 122 made of a polyimide film, a wiring film 115 disposed on the base film 122 , and an adhesive film 121 disposed on the wiring film 115 and the base film 122 .

Conductive bumps 116 are formed on the wiring film 115 , and the tips thereof protrude from the adhesive film 121 . The base film 122 is patterned so that predetermined positions on the back surface of the wiring film 115 are partially exposed.

When stacking a plurality of single-layer substrates 101, the bump 116 of one single-layer substrate 101 faces the back surface of the wiring film 115 of the stacked single-layer substrate 101, and the front end of the bump 116 is in contact with the back surface of the wiring film 115. By bonding each other with the adhesive film 121, a multilayer substrate 106 having a desired number of films can be obtained.

The surface of the multilayer substrate 106 is covered with a protective film 120, and bumps indicated by reference numerals 116a protrude from the surface.

Reference numeral 133 is a semiconductor device in which a plurality of circuits are formed. This circuit is connected with the bonding pad 134 formed on the semiconductor device 133, making the bonding pad 134 face the surface of the multilayer substrate 106, as shown in FIG. 9B, making the bonding pad 134 correspond to the bump 116a Then, if thermocompression bonding is performed, the solder coating film on the surface of the bump 116a melts, and the internal circuit of the semiconductor device 133 is connected to the wiring film 115 in the multilayer substrate 106 through the bonding pad 134 and the bump 116a.

When the semiconductor device 133 in a chip state is mounted on the above-mentioned multilayer substrate 106, it is not necessary to package the semiconductor device 133, which greatly contributes to miniaturization of electronic devices.

However, if the semiconductor device 133 is mounted on the above-mentioned conventional multilayer substrate 106 , the thickness of the entire multilayer substrate 106 increases by that of the semiconductor device 133 .

In addition, in the existing multilayer substrate 106, since the semiconductor device 133 must be protected, as shown in FIG. 9C, in the case of covering the semiconductor device 133 with the resin 135, there is a part where the overall thickness increases the resin 135. The problem of thickness.

In recent years, since mobile phones, personal computers, and the like are required to be further miniaturized and thinned, thin multilayer substrates are required even when semiconductor devices are mounted thereon.

The present invention was conceived to solve the above-mentioned disadvantages of the prior art, and its object relates to a multilayer substrate whose thickness does not increase even if a semiconductor device is mounted thereon.

In order to solve the above-mentioned problems, the multilayer substrate of the present invention includes at least a plurality of first single-layer substrates. The first single-layer substrate used in the present invention has: a first resin film; a first wiring film arranged on the first resin film; and a through-hole penetrating from the front to the back.

Furthermore, in the multilayer substrate of the present invention, at least two of the above-mentioned first single-layer substrates are electrically connected to each other, and the above-mentioned through-holes are arranged in communication to form an accommodation portion.

In general, since the area of the semiconductor chip is 1 mm ² or more, the area of each of the above-mentioned through holes must also be 1 mm ² or more, and the opening area of the above-mentioned receiving portion formed by stacking each of the through holes is also 1 mm ² or more. The depth of the housing portion is determined by the number of stacked first single-layer substrates.

Furthermore, in the present invention, first bumps connected to the first wiring film and first connection holes are provided on the first single-layer substrate, the first connection holes are formed on the first resin film, and the first connection holes are formed on the first resin film. The first wiring film is located on the bottom surface.

Furthermore, in two adjacent first single-layer substrates, the first bumps on one of the first single-layer substrates are connected to the first wiring film at the bottom surface of the other first connection hole.

Accordingly, desired wiring films of the first wiring films in the laminated first single-layer substrate of the multilayer substrate of the present invention are electrically connected to each other.

In addition, in the multilayer substrate of the present invention, a first adhesive layer that exhibits adhesiveness when heated and disposed on the first wiring film is provided on the first single-layer substrate, and the first bumps The tips of the dots protrude from the surface of the first adhesive layer.

At this time, by heating the plurality of sheets of the first single-layer substrate to make them stick together, the adhesive force of the first adhesive layer is developed, and the first single-layer substrates are bonded to each other. .

In addition, the multilayer substrate of the present invention has a second single-layer substrate.

The second single-layer substrate has a second resin film and a second wiring film disposed on the second resin film, and has no through hole at least at the position where the housing portion is formed.

Furthermore, the second single-layer substrate is further laminated on the laminated first single-layer substrate, and the second single-layer substrate is located on the bottom surface of the housing portion.

Further, in the multilayer substrate of the present invention, the second wiring film of the second single-layer substrate is electrically connected to the first wiring film of the first single-layer substrate adjacent to the second single-layer substrate. at least partly.

In addition, the second single-layer substrate of the multilayer substrate of the present invention has a second bump connected to the second wiring film, and the second bump is conductively connected to the above-mentioned substrate adjacent to the second single-layer substrate. On the bottom of the first connection hole of the first single-layer substrate on the first wiring film.

In addition, the second single-layer substrate of the multilayer substrate of the present invention has a second connection hole formed on the second resin film, the second wiring film is located on the bottom surface thereof, and is connected to the second single-layer substrate. The first bump of the first single-layer substrate adjacent to the substrate is connected to the second wiring film at the bottom surface of the second connection hole.

In addition, the second single-layer substrate of the multilayer substrate of the present invention has a second adhesive layer that exhibits adhesiveness when heated and is disposed on the second wiring film, and the tip of the second bump extends from the above-mentioned The surface of the second adhesive layer protrudes, and the second single-layer substrate is bonded to the first single-layer substrate by the adhesive force of the second adhesive layer.

In the multilayer substrate of the present invention, the second bumps are arranged on the bottom surface of the housing portion.

On the other hand, in the multilayer substrate of the present invention, on the second adhesive layer of the second single-layer substrate, a bonding pad is formed by utilizing an opening in the bottom surface where the wiring film is located, and the bonding pad The zone is arranged on the bottom surface of the above-mentioned housing part.

Either one or both of the second bump and the bonding pad may be disposed on the bottom surface of the housing portion.

Furthermore, in the multilayer substrate of the present invention, the first bump of the first single-layer substrate is connected to the second wiring film located in the second connection hole of the second single-layer substrate, and the above-mentioned The adhesive force of the first adhesive layer bonds the first single-layer substrate and the second single-layer substrate to each other.

Furthermore, in the multilayer substrate of the present invention, electrical components are disposed in the housing portion formed by using the through holes of the laminated first single-layer substrates.

In the multilayer substrate of the present invention, the electrical component is electrically connected to the second bump disposed on the bottom surface of the housing portion.

When the electric element is a semiconductor device in a chip state, the metal wiring film of the semiconductor device is connected to the second bump.

On the other hand, in another multilayer substrate of the present invention, the electrical component is electrically connected to the second bonding pad of the second single-layer substrate disposed on the bottom surface of the housing portion.

At this time, when the electric element is a semiconductor device in a chip state, bumps of the semiconductor device are connected to the bonding pads.

Furthermore, in the multilayer substrate of the present invention, the above-mentioned housing portion is covered with a single-layer substrate used as a cover having at least a resin film.

In the multilayer substrate of the present invention, a wiring film is provided on the resin film of the single-layer substrate used as a cover. The above-mentioned first or the above-mentioned second single-layer substrate may be laminated on the single-layer substrate used as the lid. In addition, the above-mentioned second single-layer substrate can also be used as the single-layer substrate used as the lid.

Further, in the multilayer substrate of the present invention, a wiring film having an area larger than that of the semiconductor device is disposed at a position extending the accommodating portion in the stacking direction. This large-area wiring film is connected to the ground potential and can be used as a shielding film.

The present invention is constituted as above, and is a multilayer substrate formed by laminating single-layer substrates and a multilayer substrate capable of accommodating electric components such as semiconductor integrated circuits in housing portions formed by utilizing cavities in the multilayer substrates.

The multilayer substrate of the present invention is constituted by stacking a plurality of single-layer substrates. For example, if an adhesive layer is formed on each of the single-layer substrates, and the adhesive layer is bonded to a resin film, the single-layer substrates are connected to form a multilayer substrate.

The copper or aluminum foils of the first and second wiring films of the first and second single-layer substrates of the present invention are patterned and distributed on the first and second resin films.

On such first and second wiring films, first and second bumps can be formed. Moreover, if an opening is formed on the first and second resin films, the first and second wiring films are exposed on the bottom surface to form a connection portion, and if the first single-layer substrate or the second single-layer substrate is laminated, the The bumps of one of the adjacent single-layer substrates coincide with the connection portion of the other single-layer substrate, and the front end of the bump is connected to the wiring film on the bottom surface of the connection portion, and the wiring film of each single-layer substrate Conductive connections are made using bumps.

Furthermore, if a solder cover film is provided on the surface of the bump in advance, and the solder cover film is melted and solidified while the bump is in contact with the wiring film, the bump is mechanically and electrically connected by solder. To the wiring film, the connection between the laminated wiring films becomes reliable.

Furthermore, the first single-layer substrate of the present invention has a through-hole, and if a plurality of through-holes of the first single-layer substrate are connected and stacked, a receiving portion is formed by the connected through-hole. When the second single-layer substrate is further laminated on the multilayer substrate on which the first single-layer substrate is laminated, the second single-layer substrate is positioned on the bottom surface of the housing portion.

If the second bump is exposed on the part of the bottom surface of the housing part of the second single-layer substrate, when electrical components such as semiconductor integrated circuits are accommodated in the housing part of the multilayer substrate, the lead wires derived from the electrical components or The metal wiring film formed on the surface of the electric component is connected to the bump.

Anisotropic conductive film can be placed between bumps and metal wiring, and the adhesive force and conductive connectivity of anisotropic conductive film can be used to connect bumps and metal wiring or leads, and the surface of bumps can also be used Solder, connected to the metal wiring or leads of electrical components.

In addition, by partially exposing the second wiring film of the second single-layer substrate on the bottom surface of the housing portion, the leads or bumps provided on the electrical components can be brought into contact for connection. In this case, a solder coating film is formed in advance on the surface of the leads or bumps of the electrical component, and the second wiring film may be connected with solder, or an anisotropic conductive film may be used.

In addition, a single-layer substrate or a multilayer substrate on which a single-layer substrate is stacked can be used as build. The surface of the multilayer substrate after the cap is formed becomes flat.

The first single-layer substrate can be used to form the first single-layer substrate on the cover-side single-layer substrate, and the upper part of the electric component can be accommodated in the cover-side accommodating portion. The first wiring films of the first single-layer substrate constituting the two housing portions can be electrically connected to each other.

If a wiring film having an area larger than that of the electrical components is provided on the multilayer substrate, and the wiring film is connected to the ground potential as a shield, noise will not intrude into the electrical components accommodated in the housing portion of the multilayer substrate. Shields can be placed on both the front and back of the electrical component. In the case where the electrical element is a semiconductor integrated circuit, since the semiconductor substrate on the side opposite to the surface on which the tiny electrical element is formed in the semiconductor integrated circuit is grounded, only the side of the surface on which the tiny electrical element is formed can be grounded. Set shielding part.

1A to 1F are manufacturing process diagrams of a single-layer substrate used in the present invention, 1G to 1M are subsequent manufacturing process diagrams of a single-layer substrate, and 1N is a first single-layer substrate.

FIG. 2A is a second single-layer substrate, FIG. 2B is a third single-layer substrate, and FIG. 2C is a fourth single-layer substrate.

3A is an enlarged view of a bump portion of an example of the multilayer substrate of the present invention, FIG. 3B is a cross-sectional view of a housing portion, and FIG. 3C is a schematic perspective view showing a housing portion.

4A to 4D are manufacturing process diagrams of an example of the module of the present invention.

Fig. 5 is a diagram showing the end of the module.

6A to 6D are manufacturing process diagrams of another example of the module of the present invention.

Fig. 7 is a diagram showing an example of a module of the present invention having a shield.

FIG. 8 is a diagram illustrating a shield portion.

9A to 9C are manufacturing process diagrams of a conventional module.

1A to 1M are process diagrams of a single-layer substrate used in the multilayer substrate of the present invention.

Referring to Figures 1A to 1F, first, a metal foil 11 is prepared (here, a rolled copper foil with a thickness of 18 μm is used) (Figure 1A), a protective film 12 is pasted on the back side, and a mask capable of ultraviolet exposure is pasted on the surface. Film (dry film manufactured by Asahi Kasei Co., Ltd.: SPG-152) 13 ( FIG. 1B ).

Next, the mask film 13 is exposed using a glass mask with a predetermined pattern (exposure light intensity: 100 mJ), and developed with chemicals to form openings 14 at predetermined positions (FIG. 1C). The forming accuracy of the opening 14 at this time is that the diameter of the opening is ±2.5 μm relative to the pattern of the mask, which is a circle with a diameter of 30 μm to 50 μm.

In this state, if the whole is immersed in an electrolytic solution for copper electroplating and an electric current flows, copper grows on the surface of the metal foil 11 exposed on the bottom surface of the opening, forming conductive bumps 16 (FIG. 1D) .

Next, the mask film 13 and the protective film 12 are removed using an alkaline solution (FIG. 1E). In this state, mushroom-shaped conductive bumps 16 stand on the surface of metal foil 11 .

A carrier film 17 is pasted on the back side of the metal foil (the side opposite to the bump 16), and a resin raw material composed of a polyimide precursor is applied on the surface of the metal foil 11 and dried to form a polyimide film. Precursor cover film 18 made of imide precursors (FIG. 1F). In this state, the precursor cover film 18 bulges around the bump 16 and its vicinity, but becomes flat at a position separated from the bump 16 . The thickness of the flat portion of the precursor cover film 18 is formed thinner than the height of the bump. Reference numeral 19 in FIG. 1F shows a film in a state where the precursor coating film 18 is formed.

Next, referring to FIGS. 1G to 1J , the film 19 is rolled with rollers 31 ₁ , 31 ₂ ( FIG. 1G ), and the precursor coating film 18 on the bump 16 becomes thinner. Next, when an alkaline solution is sprayed on the precursor cover film 18 to etch the surface, the tip of the bump 16 is exposed on the surface of the precursor cover film 18 ( FIG. 1H ).

Next, after peeling off the carrier film 17 on the back, if heating (280° C., 10 minutes), the precursor cover film 18 is thinned, and an adhesive layer made of polyimide resin is formed on the surface of the metal foil 11. Connect layer 21 (FIG. 1I). The adhesive layer 21 is thermoplastic and has no adhesive force at normal temperature, or its adhesive force is negligibly small, but has the property of exhibiting adhesive force when heated.

Next, a resist film is formed on the back surface of the copper foil 11 and patterned. Symbol 22 of FIG. 1J shows a patterned resist film. The metal foil 11 is exposed on the bottom surface of the opening 32 of the resist film 22. If etching is performed in this state, the pattern of the resist film 22 is transferred to the metal foil 11 to form a wiring film.

FIG. 1K shows a state where the resist film 22 has been removed, and reference numeral 15 shows a patterned wiring film. The portion of the wiring film 15 where the bump 16 is formed is patterned to have a slightly wider width. At this time, by patterning the metal foil 11 , together with the wiring film 15 , a shield portion to be described later is collectively formed.

Reference numeral 33 in FIG. 1K indicates a portion where a through hole described later is formed in a region where the metal foil 11 is removed.

Next, a polyimide precursor is applied to the back side of the wiring film 11 (the surface on which the bumps 16 are not formed) to form a precursor cover film 23 (FIG. 1L). The precursor cover film 23 is in contact with the wiring film 15 at a portion where the wiring film 15 is present, and is in contact with the adhesive layer 21 at a portion where the wiring film is not present.

Next, a resist film is formed on the surface of the precursor cover film 23 and patterned. Reference numeral 24 in FIG. 1M shows the patterned resist film 24 to form openings 34 . The opening 34 is composed of an opening 34 a provided at a portion where the precursor cover film 23 is in close contact with the adhesive layer 21 and an opening 34 b provided at a portion where the precursor cover film 23 is in contact with the wiring film 15 .

Using the resist film 24 as a mask, the precursor cover film 23 exposed on the bottom surfaces of the openings 34a and 34b is removed for patterning. At this time, the adhesive layer 21 is also removed together with the precursor cover film 23 at the portion where the precursor cover film 23 contacts the wiring film 15 .

After removing the resist film 24, if heat treatment is performed to harden the precursor coating film 23, the first single-layer substrate shown by the symbol 1 in FIG. 1N can be obtained, and the symbol 25 shows the patterned precursor coating. The film 23 is hardened and becomes a resin film of a polyimide film. Since the resin film 25, the wiring film 15, and the adhesive layer 21 are flexible, the first single-layer substrate is also flexible and bendable.

Openings 35 are partially formed on the resin film 25 and the adhesive layer 21 . The wiring film 15 is not provided in the opening 35, and a through-hole 35a penetrating from the front surface to the back surface of the first single-layer substrate 1 is formed in a portion where both the adhesive layer 21 and the resin film 25 are removed. In the portion where the wiring film 15 exists, since the wiring film 15 and the adhesive layer remain, only the resin film 25 is removed, and an opening is formed as a connection hole 35b. The connection hole 35b is not penetrated, and the wiring film 15 is exposed on the bottom surface.

The through-hole 35a is a portion for forming an accommodating portion described later by each through-hole 35a when stacking a plurality of first single-layer substrates 1. The size of the through-hole 35a of each first single-layer substrate 1 to be stacked is the The chip-like semiconductor device is the same size. For example, the size of one side of the through-hole 35a is approximately 1 mm or more and a size of several tens of mm or less. The end of the wiring film 15 is not exposed in the through hole 35a, and when a chip-shaped semiconductor device is accommodated in the housing portion formed by the through hole 35a, the side surface of the semiconductor device is not brought into contact with the wiring film 15.

On the other hand, the size of the connection hole 35b is substantially the same as that of the bump 16 (approximately 50 to 500 μm), and the tip of the bump 16 is brought into contact with the surface of the wiring film 15 exposed on the bottom surface of the connection hole 35b.

Reference numeral 2 in FIG. 2A is a second single-layer substrate without the through hole 34a. In this second single-layer substrate 2, the opening 34a of the resist film 24 is not formed in the portion where the adhesive layer 21 and the precursor cover film 23 are in close contact, and the same process as that of the first single-layer substrate 1 is used. process to form. Therefore, the second single-layer substrate 2 is also flexible like the first single-layer substrate 1 .

The second single-layer substrate 2 is disposed under the stacked first single-layer substrate 1, and constitutes the bottom surface of the container or the cover of the container.

Reference numeral 3 in FIG. 2B indicates a third single-layer substrate disposed on the uppermost portion of the multilayer substrate when the single-layer substrates are stacked to form a multilayer substrate. The wiring film 15 of the third single-layer substrate 3 is also formed of a patterned copper film. A protective film 21 made of the same material as the resin film 25 of the first single-layer substrate 1 is formed on the surface of the wiring film 15 of the third single-layer substrate 3 . In the case of the third single-layer substrate 3 , there are cases where there are no bumps 16 and where there are bumps 16 . In addition, there are cases where the through hole 35 a is formed and not formed.

Reference numeral 4 in FIG. 2C shows a fourth single-layer substrate arranged at the bottom of the multilayer substrate. The structure of the fourth single-layer substrate 4 is the same as that of the second single-layer substrate 2, and the same materials are used for the wiring film and the resin film. Therefore, the fourth single-layer substrate 4 is also flexible. In the fourth single-layer substrate 4, the connection hole 35b may or may not be present.

In the case where the first to fourth single-layer substrates 1 to 4 above are laminated to constitute the multilayer substrate of the present invention, in the mutually laminated single-layer substrates, the positions of the connection holes 35b and the bumps 16 are arranged as follows, The bumps 16 of the other single-layer substrate are brought into contact with the connection holes 35b of the one single-layer substrate. When the bumps 16 are brought into contact with the wiring film 15 exposed on the bottom surface of the connection hole 35b and pressure-bonded while heating, the adhesive layer 21 softens and exhibits adhesive force, and the substrates are bonded together.

When the solder coating film is formed on the surface of the bump 16, the wiring film 15 and the bump 16 are electrically and mechanically connected by melting the solder. At this time, a gold coating film can be formed on the surface of the solder coating film. In addition, conductive connection is possible without providing a solder coating.

FIG. 3A shows an enlarged view of a connection portion between bump 16 and wiring film 15 when a plurality of single-layer substrates are stacked.

Reference numeral 6a in FIG. 3B is a cross-section of a multilayer substrate in which one fourth single-layer substrate 4, two second single-layer substrates 2 ₁ , 2 ₂ , and three first single-layer substrates 1 ₁ to 1 ₃ are stacked in the following order. picture. Through-holes 35a ₁ to 35a ₃ having the same size are formed at the same positions on the first single-layer substrates _{1 1} to 1 ₃ .

Since the first single-layer substrate ₁₁ at the bottom layer is connected to the second single-layer substrate ₂₂ , the second single-layer substrate ₂₂ is located on the bottom surface of the housing portion 26 . Therefore, the bottomed accommodation portion 26 is formed by the through-holes 35a ₁ to 35a ₃ of the first single-layer substrates 1 ₁ to 1 ₃ and the second single-layer substrate 2 ₁ disposed on the bottom surface thereof.

Reference numeral 16a in FIG. 3B indicates a bump exposed on the bottom surface of the housing portion 26 among the bumps 16 provided on the second single-layer substrate ₂₂ .

In addition, reference numeral 16b in FIG. 3B shows the bumps of the first single-layer substrate ₁₃ located on the surface of the multilayer substrate 6a, and reference numeral 16c shows the bumps located inside the multilayer substrate 6a and connected to the wiring film 15. point.

FIG. 3C shows a schematic oblique view of the part of the multilayer substrate 6 a forming the receptacle 26 . The bumps 16a of the second single-layer substrate 22 are exposed on the bottom surface of the housing portion ₂₆ , but are omitted in this perspective view.

Next, the process of mounting electrical components on the multilayer substrate 6a will be described. Reference numeral 41 in FIG. 4A is a semiconductor device such as a semiconductor integrated circuit, which is an example of a mountable electrical component. Tiny electrical components are placed on one side of a semiconductor device to form a circuit. On the surface on which this circuit is formed, bonding pads 42 made of a metal thin film are formed.

When semiconductor device 41 is mounted on multilayer substrate 6 a , bonding pad 42 is inserted into accommodating portion 26 so that it faces the bottom surface side of accommodating portion 26 .

The bumps 16 a in the housing portion 26 are arranged at positions corresponding to the bonding pads 42 , and when the positions are aligned, the bonding pads 42 are placed on the bumps 16 a.

In the state where the bonding land 42 is placed on the bump 16a, if the semiconductor device 41 is heated and the semiconductor device 41 is pressed onto the multilayer substrate 6a, the surface of the semiconductor device 41 and the housing portion 26 The surface of the adhesive layer 21 on the bottom surface is in contact with each other, and the semiconductor device 41 is bonded to the multilayer substrate 6 a by the softened adhesive layer 21 ( FIG. 4B ).

As described above, the multilayer substrate shown by symbol 6b in FIG. 4C is prepared separately from the multilayer substrate 6a having the accommodation portion 26. As shown in FIG.

This multilayer substrate 6b is constituted by laminating two second single-layer substrates 2 ₃ and 2 ₄ and a third single-layer substrate 3 in the following order. The multilayer substrate 6b is used as a cover, and the multilayer substrate 6a on which the housing portion 26 is formed is used as a container. After the semiconductor device 41 is accommodated in the housing portion 26, the lid side is covered from the multilayer substrate 6a on the container side. multilayer substrate 6b.

The connection hole 35b of the second single-layer substrate ₂₃ is arranged on the bottom surface of the multilayer substrate 6b on the lid side, and the connection hole 35b corresponds to the bump 16b exposed on the multilayer substrate 6a on the container side. configured on .

Therefore, when the multilayer substrate 6b on the side of the lid and the multilayer substrate 6a on the side of the container are overlapped and covered, the bumps 16b on the multilayer substrate 6a on the side of the container will not match the bumps 16b on the multilayer substrate 6a on the side of the lid. The surface of the wiring film 15 exposed on the bottom surface of the connection hole 35 of the layer substrate 6b is in contact with it.

If heating and pressing are performed in this state, the multilayer substrate 6a on the container side and the multilayer substrate 6b on the cover side are bonded together by the adhesive layer 21, and at the same time, the cover side is bonded together by the bumps 16b. The wiring film 15 in the multilayer substrate 6b and the wiring film 15 in the multilayer substrate 6a on the housing portion 26 side are electrically connected to each other to form an integrated multilayer substrate 6 . The semiconductor device 41 is housed inside the multilayer substrate 6 , and the house portion 27 is formed by utilizing a sealed cavity.

In this way, if the semiconductor device 41 is integrated to form a single multilayer substrate 6 in a state where the semiconductor device 41 is accommodated, the multilayer substrate 6 and the semiconductor device 41 embedded in the sealed housing portion 27 constitute a chip-mounted multilayer substrate. 62 (Fig. 4D).

The circuits in the semiconductor device 41 are respectively connected to the wiring films 15 of the single-layer substrates 1 to 4 constituting the multilayer substrate 6 through the bonding pads 42 and the bumps 16 .

On the end portion of the multilayer substrate 62 in this chip mounting state, as shown in FIG. The wiring film 15 is electrically connected to other circuit boards and the like. Therefore, the semiconductor device 41 in the multilayer substrate 62 is electrically connected to another circuit substrate or the like by using the bumps 36 and the connection holes 37 .

In addition, the wiring film 15 having a relatively large area may be exposed on the bottom surface of the end portion to form the connection terminal 38, and the connection terminal may be used to connect to another circuit board or the like.

Thus, in the multilayer substrate 62 described above, since the semiconductor device 41 is embedded in the multilayer substrate 6, the overall thickness of the semiconductor device 41 does not increase.

In addition, since the first to fourth single-layer substrates 1 to 4 constituting the multilayer substrate 62 are flexible, the multilayer substrate 62 is flexible except for the portion where the semiconductor device 41 is mounted.

In this example, only one semiconductor device 41 is embedded in the multilayer substrate 6 to constitute the multilayer substrate, but a plurality of semiconductor devices may be embedded to constitute the multilayer substrate. At this time, the conductive connection between the embedded semiconductor devices can be ensured by the wiring film 15 and the bumps 16 inside the multilayer substrate 6 .

Next, another example of the present invention will be described. Reference numeral 7a in FIG. 6A shows a multilayer substrate having the same structure as the multilayer substrate 6a on the container side described above. The multilayer substrate 7a on the container side and the multilayer substrate 7b on the lid side are formed by laminating the second single layer substrate 2 and the third single layer substrate 3 on the stacked first single layer substrate 1. .

On the multilayer substrate 7a on the container side, a bottomed housing portion 53 is formed by using the through hole 35a of the stacked first single layer substrate 1, and on the multilayer substrate 7b on the cover side, also by using the through hole 35a. A bottomed receiving portion 54 is formed.

The above-mentioned semiconductor device 41 is accommodated in the accommodation portion 53 of the multilayer substrate 7a on the side of the container, and if it is bonded to the multilayer substrate 7a, it is electrically connected to the wiring film 15, and then connected to the cover from its upper portion. The multilayer substrate 7b on one side is bonded together, and the multilayer substrate 7a, 7b is electrically and mechanically connected to form an integrated multilayer substrate 7. Then, the semiconductor device 41 is accommodated in two accommodation parts 53, 54. formed in the cavity.

The structure of the multilayer substrate 7 is the same as that of the multilayer substrate 6 shown in FIG. 4D , and electrical components can also be mounted thereon.

Next, reference numeral 43 in FIG. 6B shows a semiconductor device on which bumps 44 are formed on the surface. In the case of using this semiconductor device 43, the surface of the wiring film 15 can be partially exposed on the bottom surface of the housing portion 55 of the multilayer substrate 8a on the container side so as to be in contact with the bump formed in the semiconductor device 43. 44 connected.

When this multilayer substrate 8a is bonded to the cover-side multilayer substrates 6b and 7b shown in FIG. 4C or FIG. 6A, an integrated multilayer substrate 8 can be obtained. The multilayer substrate of the present invention in a chip-mounted state is constituted by the multilayer substrate 8 and the semiconductor device 43 embedded in the multilayer substrate 8 .

Reference numeral 9 in Fig. 6C is a multilayer substrate having a third single-layer substrate 3' provided with through holes.

In this multilayer substrate 9, a plurality of first single-layer substrate 1 and third single-layer substrate 3' are laminated in the following order. A resin film serving as a protective film is formed on the surface of the third single-layer substrate 3'. The through-holes of the third single-layer substrate 3' are arranged at the same positions as the through-holes 35a of the first single-layer substrate 1, and are electrically and mechanically connected in the housing portion 56 constituted by these through-holes. In the case of , the semiconductor device 41 is accommodated.

The back surface of the semiconductor device 41 is exposed on the surface of the multilayer substrate 9 . In addition, the back surface of the semiconductor device 41 and the surface of the multilayer substrate 9 are located at substantially the same height, and are substantially on the same plane.

In the chip-mounted multilayer substrate 63 composed of the multilayer substrate 9 and the semiconductor device 41 , since the back surface of the semiconductor device 41 is exposed, heat dissipation is good.

Reference numeral 64 in FIG. 6D is a multilayer substrate in which a protective film 29 is bonded to the multilayer substrate 63 described above. Since the surface of the multilayer substrate 64 is covered with the protective film 29, it is excellent in moisture resistance and the like.

Secondly. The multilayer substrate 10a on the side of the container of the multilayer substrate 65 shown in FIG. A plurality of first single-layer substrates 1 stacked thereon and a third single-layer substrate 3 that is the uppermost layer are constituted.

The second single-layer substrate 5 adjacent to the second single-layer substrate 2 on which the semiconductor device 47 is mounted has a shield portion 28 composed of a large-area wiring film 15 as shown in FIG. 8 . Here, the second single-layer substrate 5 having the shield portion 28 is connected to the fourth single-layer substrate 4 .

The multilayer substrate 65 is composed of a multilayer substrate 10a serving as a container and a multilayer substrate 6b serving as a lid. The multilayer substrate 10a on the container side has the stacked first single-layer substrates 1, and the through-holes 35a of the respective first single-layer substrates 1 constitute the accommodating portion 57. Furthermore, in the housing portion 57 , the cover-side multilayer substrate 6 b is placed on the housing portion 57 in a state where the semiconductor device 47 is housed, and the housing portion 57 is sealed. This semiconductor device 47 is a semiconductor integrated circuit in a chip state.

When the metal foil 11 is patterned to form the wiring film 15 having a narrow width, the shielding portion 28 is formed simultaneously with the wiring film 15 to have approximately the same area as the bottom surface of the housing portion 57 or an area larger than the bottom surface of the housing portion 57. to form. Therefore, the shield portion 28 is arranged parallel to the bottom surface so as to cover the bottom surface of the housing portion 57 .

The semiconductor device 47 is housed in the housing portion 57 . In the semiconductor device 47, on the surface 49 on which the circuit is formed by the tiny electrical components, the bonding land 42 is provided by the metal wiring film connecting the tiny electrical components, and the bonding layer 42 is arranged on the bottom surface of the housing portion 57, It is mechanically connected to the second single-layer substrate 2 of the multilayer substrate 10a on the container side. In addition, the bumps 16 a of the second single-layer substrate 2 in contact with the bonding pads 42 are electrically connected to the circuit in the semiconductor device 47 and the wiring film 15 . In this state, the lid-side multilayer substrate 6b is electrically and mechanically connected to the container-side multilayer substrate 10a.

Therefore, in a state where the semiconductor device 47 is embedded in the housing portion 57 , the circuit formation surface of the semiconductor device 47 faces the shield portion 28 and is covered by the shield portion 28 .

Generally, in a semiconductor integrated circuit, a metal film 48 is formed on the back surface opposite to the surface on which the bonding pad 42 is formed, and the metal film 48 is connected to a ground potential.

Therefore, if the wiring film 15 connected to the shield portion 28 is connected to the ground potential, the radio noise that intends to enter the semiconductor device 47 from the outside of the multilayer substrate 65 is absorbed by the shield portion 28 and the metal film 48 on the back side. , so it will not invade into the semiconductor device 47 .

In this way, the multilayer substrate 65 in FIG. 7 is composed of the multilayer substrate 10 having the shield portion 28 and the semiconductor device 47 embedded in the multilayer substrate 10 , and is highly resistant to noise.

As described above, the solder coating film is provided on the surface of the bump, and the solder is melted to connect the bump and the wiring film, but the conductive connection can also be made by bringing the bump and the wiring film into close contact. At this time, a gold coating film instead of a solder coating film may be formed on the bump surface in advance.

In the case where a gold coating is provided, the bumps and the wiring film may be brought into close contact, and ultrasonic waves may be applied to electrically and mechanically connect the bumps and the wiring film.

In addition, in the above description, the semiconductor integrated circuit is used as an example of the electrical element, but the present invention is not limited thereto, and may be a discrete transistor or diode element, and is not limited to an integrated circuit.

In addition, in the present invention, the electrical components that can be accommodated in the housing portion are not limited to semiconductor devices, and include electrical components other than semiconductor devices such as capacitors, inductance elements, and resistance elements. The semiconductor device is not limited to a device in a chip state, and a device housed in a resin or ceramic package may be accommodated in the housing portion.

When a semiconductor element in a chip state is accommodated in the accommodation portion, it is only necessary to connect the metal wiring or the bump of the semiconductor element to the bump or the bonding land on the bottom surface of the accommodation portion.

As for the electrical components placed in the package, it is only necessary to connect the leads drawn out of the package to the bumps or the bonding pads on the bottom surface of the housing portion.

The present invention has the effect that the thickness does not increase even if a semiconductor device is mounted. In addition, it is difficult for noise to penetrate due to the shielding portion.

Claims (25)

1. multilager base plate is characterized in that:

Have multi-disc the 1st single layer substrate, above-mentioned the 1st single layer substrate has: the 1st resin molding; The 1st wiring membrane that on above-mentioned the 1st resin molding, disposes; And the through hole that penetrates into the back side from the surface,

Among the 1st single layer substrate of above-mentioned multi-disc, above-mentioned the 1st wiring membrane of the 1st single layer substrate more than 2 is electrically connected mutually,

Dispose above-mentioned through hole communicatively, formed the accommodation section.

2. the multilager base plate described in claim 1 is characterized in that:

The aperture area of above-mentioned accommodation section is at 1mm ²More than.

3. the multilager base plate described in claim 1 is characterized in that:

Above-mentioned the 1st single layer substrate has:

The 1st salient point that is connected with above-mentioned the 1st wiring membrane; And

The 1st connecting hole, the 1st connecting hole forms on above-mentioned the 1st resin molding, and above-mentioned the 1st wiring membrane is positioned at the bottom surface of the 1st connecting hole,

2 above-mentioned the 1st single layer substrates in adjacency are mutual, and above-mentioned the 1st salient point of above-mentioned the 1st single layer substrate of the side is connected with above-mentioned the 1st wiring membrane of the basal surface position of above-mentioned the 1st connecting hole of the opposing party's above-mentioned the 1st single layer substrate.

4. the multilager base plate described in claim 3 is characterized in that:

If above-mentioned the 1st single layer substrate has the 1st adhesive linkage that the heating that is configured on above-mentioned the 1st wiring membrane just shows cementability, the front end of above-mentioned the 1st salient point is outstanding from the surface of above-mentioned the 1st adhesive linkage,

Above-mentioned the 1st single layer substrate utilizes the bonding force of above-mentioned the 1st adhesive linkage to be secured at together mutually each other.

5. the multilager base plate described in claim 1 is characterized in that:

The 2nd wiring membrane that stacked the 2nd single layer substrate, the 2nd single layer substrate have the 2nd resin molding and dispose on above-mentioned the 2nd resin molding does not have through hole at least on the position that has formed above-mentioned accommodation section,

Above-mentioned the 2nd single layer substrate is positioned on the bottom surface of above-mentioned accommodation section.

6. the multilager base plate described in claim 5 is characterized in that:

Above-mentioned the 2nd wiring membrane of above-mentioned the 2nd single layer substrate be connected with at least a portion conductivity ground of above-mentioned the 1st wiring membrane of above-mentioned the 1st single layer substrate of above-mentioned the 2nd single layer substrate adjacency.

7. the multilager base plate described in claim 3 is characterized in that:

The 2nd wiring membrane that stacked the 2nd single layer substrate, the 2nd single layer substrate have the 2nd resin molding and dispose on above-mentioned the 2nd resin molding does not have through hole at least on the position that has formed above-mentioned accommodation section,

Above-mentioned the 2nd single layer substrate is positioned on the bottom surface of above-mentioned accommodation section.

8. the multilager base plate described in claim 7 is characterized in that:

Above-mentioned the 2nd single layer substrate has the 2nd salient point that is connected with above-mentioned the 2nd wiring membrane,

Above-mentioned the 2nd salient point is connected on above-mentioned the 1st wiring membrane that is positioned at the bottom of above-mentioned the 1st connecting hole of above-mentioned the 1st single layer substrate of above-mentioned the 2nd single layer substrate adjacency.

9. the multilager base plate described in claim 8 is characterized in that:

Above-mentioned the 2nd salient point is configured on the bottom surface of above-mentioned accommodation section.

10. the multilager base plate described in claim 7 is characterized in that:

Above-mentioned the 2nd single layer substrate has the 2nd connecting hole, and the 2nd connecting hole is configured on above-mentioned the 2nd resin molding, and above-mentioned the 2nd wiring membrane is positioned at the bottom surface of the 2nd connecting hole,

Be connected on above-mentioned the 2nd wiring membrane of basal surface position of above-mentioned the 2nd connecting hole with above-mentioned the 1st salient point of above-mentioned the 1st single layer substrate of above-mentioned the 2nd single layer substrate adjacency.

11. a multilager base plate is characterized in that:

Above-mentioned multilager base plate is the multilager base plate described in the claim 4, wherein, stacked the 2nd single layer substrate, the 2nd wiring membrane that the 2nd single layer substrate has the 2nd resin molding and disposes on above-mentioned the 2nd resin molding, at least on the position that has formed above-mentioned accommodation section, there is not through hole, above-mentioned the 2nd single layer substrate is positioned on the bottom surface of above-mentioned accommodation section

If above-mentioned the 2nd single layer substrate has the 2nd salient point that is connected with above-mentioned the 2nd wiring membrane and is configured in the 2nd adhesive linkage that heating on above-mentioned the 2nd wiring membrane just shows cementability, the front end of above-mentioned the 2nd salient point is given prominence to from the surface of above-mentioned the 2nd adhesive linkage,

Above-mentioned the 2nd salient point is connected with being positioned at above-mentioned the 1st wiring membrane of the bottom of above-mentioned the 1st connecting hole of above-mentioned the 1st single layer substrate of above-mentioned the 2nd single layer substrate adjacency,

Utilize above-mentioned the 2nd adhesive linkage bonding force, above-mentioned the 1st single layer substrate and the 2nd single layer substrate are fit together mutually.

12. the multilager base plate described in claim 11 is characterized in that:

Above-mentioned the 2nd salient point is configured on the bottom surface of above-mentioned accommodation section.

13. the multilager base plate described in claim 11 is characterized in that:

On above-mentioned the 2nd adhesive linkage of above-mentioned the 2nd single layer substrate, utilize the opening of the residing bottom surface of above-mentioned wiring membrane, formed the bonding welding zone,

Above-mentioned bonding welding zone is configured on the bottom surface of above-mentioned accommodation section.

14. a multilager base plate is characterized in that:

Above-mentioned multilager base plate is the multilager base plate described in the claim 4, wherein, stacked the 2nd single layer substrate, the 2nd wiring membrane that the 2nd single layer substrate has the 2nd resin molding and disposes on above-mentioned the 2nd resin molding, at least on the position that has formed above-mentioned accommodation section, there is not through hole, above-mentioned the 2nd single layer substrate is positioned on the bottom surface of above-mentioned accommodation section

Above-mentioned the 2nd single layer substrate has the 2nd connecting hole, and the 2nd connecting hole forms on above-mentioned the 2nd resin molding, and above-mentioned the 2nd wiring membrane is positioned at the bottom surface of the 2nd connecting hole,

Be connected with above-mentioned the 2nd wiring membrane of the basal surface position of above-mentioned the 2nd connecting hole with above-mentioned the 1st salient point of above-mentioned the 1st single layer substrate of above-mentioned the 2nd single layer substrate adjacency,

Utilize above-mentioned the 1st adhesive linkage bonding force, above-mentioned the 1st single layer substrate and the 2nd single layer substrate are fit together mutually.

15. the multilager base plate described in claim 1 is characterized in that:

Dispose electric component in above-mentioned accommodation section, at least a portion of above-mentioned the 1st wiring membrane is connected with above-mentioned electric component conductivity ground.

16. the multilager base plate described in claim 12 is characterized in that:

Dispose electric component in above-mentioned accommodation section, above-mentioned the 2nd salient point of bottom surface, above-mentioned accommodation section is connected with above-mentioned electric component.

17. the multilager base plate described in claim 12 is characterized in that:

The semiconductor device of configuring chip state in above-mentioned accommodation section, the metal line film of above-mentioned semiconductor device is connected with above-mentioned the 2nd salient point of bottom surface, above-mentioned accommodation section.

18. the multilager base plate described in claim 17 is characterized in that:

The single layer substrate that above-mentioned accommodation section is had the conduct lid use of resin molding at least covers.

19. the multilager base plate described in claim 18 is characterized in that:

On the above-mentioned resin molding of the single layer substrate that uses as lid, be provided with wiring membrane.

20. the multilager base plate described in claim 18 is characterized in that:

On stacked direction, prolonged on the position of the above-mentioned accommodation section in the above-mentioned multilager base plate and disposed its area wiring membrane bigger than the area of above-mentioned semiconductor device.

21. the multilager base plate described in claim 13 is characterized in that:

Dispose electric component in above-mentioned accommodation section, the above-mentioned bonding welding zone of bottom surface, above-mentioned accommodation section is connected with above-mentioned electric component.

22. the multilager base plate described in claim 13 is characterized in that:

The semiconductor device of configuring chip state in above-mentioned accommodation section, the salient point of above-mentioned semiconductor device is connected with the above-mentioned bonding welding zone of bottom surface, above-mentioned accommodation section.

23. the multilager base plate described in claim 22 is characterized in that:

The single layer substrate that above-mentioned accommodation section is had the conduct lid use of resin molding at least covers.

24. the multilager base plate described in claim 23 is characterized in that:

On the above-mentioned resin molding of the single layer substrate that uses as lid, be provided with wiring membrane.

25. the multilager base plate described in claim 23 is characterized in that:

On stacked direction, prolonged on the position of the above-mentioned accommodation section in the above-mentioned multilager base plate and disposed its area wiring membrane bigger than the area of above-mentioned semiconductor device.

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