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CN113811991A - 芯片封装体及其制备方法 - Google Patents

芯片封装体及其制备方法 Download PDF

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Publication number
CN113811991A
CN113811991A CN202080001578.2A CN202080001578A CN113811991A CN 113811991 A CN113811991 A CN 113811991A CN 202080001578 A CN202080001578 A CN 202080001578A CN 113811991 A CN113811991 A CN 113811991A
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CN
China
Prior art keywords
layer
chip
pad
ipd
conductive
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CN202080001578.2A
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English (en)
Inventor
陆斌
沈健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Publication of CN113811991A publication Critical patent/CN113811991A/zh
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    • H10D64/011—
    • H10W72/00—
    • H10W90/00—
    • H10W95/00—

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本申请提供了一种芯片封装体及其制备方法。所述芯片封装体包括：芯片，所述芯片的上表面设置有至少一个第一焊盘和至少一个第二焊盘；器件层，所述器件层包括第一绝缘层、至少一个导电柱和集成无源器件IPD，所述第一绝缘层设置在所述芯片的上方，所述至少一个导电柱贯通所述第一绝缘层并设置在所述至少一个第一焊盘的上方，所述IPD贯通所述第一绝缘层并设置在所述至少一个第二焊盘的上方；布线层，所述布线层设置在所述器件层的上方；至少一个第三焊盘，所述至少一个第三焊盘设置在所述布线层的上方，所述至少一个导电柱通过所述布线层连接至所述至少一个第三焊盘。所述芯片封装体能够在减小寄生电容的基础上保证芯片的良率。

Description

PCT国内申请，说明书已公开。

Claims (29)

  1. PCT国内申请，权利要求书已公开。
CN202080001578.2A 2020-03-31 2020-03-31 芯片封装体及其制备方法 Pending CN113811991A (zh)

Applications Claiming Priority (1)

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PCT/CN2020/082565 WO2021196012A1 (zh) 2020-03-31 2020-03-31 芯片封装体及其制备方法

Publications (1)

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CN113811991A true CN113811991A (zh) 2021-12-17

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CN202080001578.2A Pending CN113811991A (zh) 2020-03-31 2020-03-31 芯片封装体及其制备方法

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CN (1) CN113811991A (zh)
WO (1) WO2021196012A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115547998A (zh) * 2022-10-21 2022-12-30 华进半导体封装先导技术研发中心有限公司 一种六面保护的2.5d模组结构及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005108929A (ja) * 2003-09-29 2005-04-21 Casio Comput Co Ltd 半導体装置及びその製造方法
US20110285007A1 (en) * 2010-05-24 2011-11-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP
US9269595B2 (en) * 2010-01-29 2016-02-23 Stats Chippac, Ltd. Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint
CN106169466A (zh) * 2015-05-19 2016-11-30 联发科技股份有限公司 半导体封装组件及其制造方法
CN108428684A (zh) * 2017-02-14 2018-08-21 南亚科技股份有限公司 半导体结构及其制造方法
CN109037080A (zh) * 2018-06-29 2018-12-18 华进半导体封装先导技术研发中心有限公司 一种集成ipd封装结构及其制造方法
CN110634824A (zh) * 2018-06-22 2019-12-31 何崇文 芯片封装结构及其制作方法
CN211743148U (zh) * 2020-03-31 2020-10-23 深圳市汇顶科技股份有限公司 芯片封装体和电子设备

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005108929A (ja) * 2003-09-29 2005-04-21 Casio Comput Co Ltd 半導体装置及びその製造方法
US9269595B2 (en) * 2010-01-29 2016-02-23 Stats Chippac, Ltd. Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint
US20110285007A1 (en) * 2010-05-24 2011-11-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP
CN106169466A (zh) * 2015-05-19 2016-11-30 联发科技股份有限公司 半导体封装组件及其制造方法
CN108428684A (zh) * 2017-02-14 2018-08-21 南亚科技股份有限公司 半导体结构及其制造方法
CN110634824A (zh) * 2018-06-22 2019-12-31 何崇文 芯片封装结构及其制作方法
CN109037080A (zh) * 2018-06-29 2018-12-18 华进半导体封装先导技术研发中心有限公司 一种集成ipd封装结构及其制造方法
CN211743148U (zh) * 2020-03-31 2020-10-23 深圳市汇顶科技股份有限公司 芯片封装体和电子设备

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