Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein a well region is formed in the semiconductor substrate, and a mask layer is formed on the semiconductor substrate;
etching the mask layer and the semiconductor substrate to form a groove surrounding the well region;
forming a dielectric layer on the side wall of the groove;
forming an injection region in the semiconductor substrate at the bottom of the groove;
and filling a conductive material in the groove to form an isolation structure consisting of the dielectric layer and the conductive material in the semiconductor substrate.
Further, after the etching the mask layer and the semiconductor substrate to form a groove surrounding the well region and before the forming the dielectric layer on the sidewall of the groove, the method further includes:
performing heat treatment to form a sacrificial layer in the groove;
and removing the sacrificial layer by wet etching.
Further, the step of forming the dielectric layer on the sidewall of the groove further includes:
performing heat treatment to form a dielectric layer on the mask layer and the inner wall of the groove;
and performing self-aligned etching, removing the dielectric layers on the mask layer and at the bottom of the groove by anisotropic gas etching, and reserving the dielectric layers on the side wall of the groove, wherein the dielectric layers are gate oxide layers.
Further, filling a conductive material in the groove to form an isolation structure composed of the dielectric layer and the conductive material in the semiconductor substrate, further comprising:
growing a conductive material on the furnace tube, covering the conductive material on the mask layer, and filling the conductive material in the groove;
removing the conductive material on the mask layer and part of the conductive material in the groove, wherein the upper surface of the residual conductive material in the groove is flush with the upper surface of the semiconductor substrate;
and removing the mask layer on the semiconductor substrate and part of the dielectric layer in the groove, wherein the upper surface of the residual dielectric layer in the groove is flush with the upper surface of the residual conductive material in the groove, and the dielectric layer in the groove and the conductive material form the isolation structure.
Further, the depth of the groove is larger than that of the well region.
Further, the depth-to-width ratio of the groove is larger than 5:1, and/or the thickness range of the dielectric layer is 200-1000 angstroms.
Further, deep reactive ion etching is performed to form the groove, and the side wall of the groove is a vertical side wall.
Further, self-aligned ion implantation is performed to form the implantation region, and the implantation region is a self-aligned implantation region.
The present invention also provides a semiconductor device comprising:
the semiconductor device comprises a semiconductor substrate, a first substrate and a second substrate, wherein a well region and a groove arranged around the well region are formed in the semiconductor substrate, and the side wall of the groove is a vertical side wall;
an implantation region located in the semiconductor substrate at the bottom of the groove;
and the isolation structure comprises a conductive material for filling the groove and a dielectric layer positioned between the conductive material and the side wall of the groove.
Further, the depth of the groove is larger than that of the well region.
Further, the depth-to-width ratio of the groove is larger than 5:1, and/or the thickness range of the dielectric layer is 200-1000 angstroms.
Further, the conductivity type of the implanted region is the same as the conductivity type of the semiconductor substrate.
Further, the side wall of the groove is a vertical side wall, and the injection region is a self-aligned injection region.
Further, the conductive material is electrically connected to a substrate electrode on the surface of the semiconductor substrate.
According to the semiconductor device and the manufacturing method thereof provided by the invention, the dielectric layer is formed on the side wall of the groove, and the conductive material is filled in the groove to form the isolation structure, so that a better deep groove filling effect is obtained, and meanwhile, the substrate electrode is led out to the surface of the substrate by utilizing the isolation structure, so that the area of the semiconductor device is reduced.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Referring to fig. 1 and 2A-2F, wherein fig. 1 shows a schematic flow diagram of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention, and fig. 2A-2F show schematic cross-sectional views of devices respectively obtained by sequential steps of the method according to an exemplary embodiment of the present invention.
The invention provides a preparation method of a semiconductor device, as shown in figure 1, the main steps of the preparation method comprise:
step S101: providing a semiconductor substrate, wherein a well region is formed in the semiconductor substrate, and a mask layer is formed on the semiconductor substrate;
step S102: etching the mask layer and the semiconductor substrate to form a groove surrounding the well region;
step S103: forming a dielectric layer on the side wall of the groove;
step S104: forming an injection region in the semiconductor substrate at the bottom of the groove;
step S105: and filling a conductive material in the groove to form an isolation structure consisting of the dielectric layer and the conductive material in the semiconductor substrate.
According to the embodiment of the invention, the manufacturing method of the semiconductor device specifically comprises the following steps:
first, step S101 is performed to obtain a device structure as shown in fig. 2A. Providing a semiconductor substrate 200, wherein a well region 201 is formed in the semiconductor substrate 200, and a mask layer 202 is formed on the semiconductor substrate.
Illustratively, the semiconductor device comprises an LDMOS device.
Illustratively, the semiconductor substrate 200 may be at least one of the following mentioned materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In the embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and the specific doping concentration is not limited by the invention, and the semiconductor substrate 200 may be formed by epitaxial growth, or may be a wafer substrate.
Illustratively, a well region 201 is formed in the semiconductor substrate 200.
Illustratively, a well implantation process is employed to form a well region 201 in the semiconductor substrate 200, the well region 201 having a different doping type than the semiconductor substrate 200. When the substrate is an N-type substrate, specifically, an N-type substrate commonly used in the art may be selected by a person skilled in the art, and then a P-well is formed in the N-type substrate, in an embodiment of the present invention, a P-well window is first formed on the N-type substrate, ion implantation is performed in the P-well window, and then an annealing step is performed to form a P-well. When the substrate is a P-type substrate, specifically, a person skilled in the art may select a P-type substrate commonly used in the art, and then an N-well is formed in the P-type substrate, in an embodiment of the present invention, an N-well window is first formed on the P-type substrate, ion implantation is performed in the N-well window, and then an annealing step is performed to form an N-well. In the present embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and the well 201 is an N-type well.
Illustratively, a mask layer 202 is formed on the semiconductor substrate 200.
Illustratively, the mask layer 202 includes a hard mask layer including a stacked structure of an oxide layer, a nitride layer, or both, to protect the upper surface of the semiconductor substrate 200 during the fabrication of the LDMOS device.
Next, step S102 is performed to obtain the device structure shown in fig. 2A. The mask layer 202 and the semiconductor substrate 200 are etched to form a groove 203 surrounding the well region 201.
Illustratively, the depth of the groove 203 is greater than the depth of the well region 201.
Illustratively, the groove 203 is a groove with a high aspect ratio, the aspect ratio of the groove 203 is greater than 5:1, specifically, the width of the groove 203 ranges from 0.8 μm to 3 μm, and the depth of the groove 203 ranges from 8 μm to 15 μm.
Illustratively, the method for forming the groove 203 may be Deep Reactive Ion Etching (DRIE). Specifically, gaseous silicon hexafluoride (SF) is selected6/C4F8) Applying a radio frequency Power supply as a process gas to enable the reaction gas of silicon hexafluoride to form high ionization, wherein the pressure in the etching step is controlled to be 15 mT-45 mT, the Source Power (Source Power) is controlled to be 400W-600W, the BIAS Power (BIAS Power) is controlled to be-180V-240V, and the etching gas SF is6Controlled at 50-70 cubic centimeter per minute (sccm), O2The control is carried out at 60-85 cubic centimeters per minute (sccm), the HE is controlled at 100-400 cubic centimeters per minute (sccm), and the requirement of anisotropic etching is guaranteed. The deep reactive ion etching system can be selected from equipment commonly used in the field and is not limited to a certain model.
Illustratively, the sidewall of the groove 203 is required to be a vertical sidewall, i.e., the sidewall of the groove 203 is vertical to the plane of the semiconductor substrate 200. The topography of the vertical sidewalls facilitates the subsequent implementation of a self-aligned implant of the implanted region at the bottom of the recess 203.
Next, the steps are performed: a sacrificial layer is formed within the recess 203.
Illustratively, a sacrificial layer is formed within the recess 203 by performing a heat treatment. In this embodiment, a layer of silicon oxide is grown in the recess 203 as a sacrificial layer by a furnace process, and the thickness of the sacrificial layer is in the range of 20 angstroms to 110 angstroms.
Next, the steps are performed: and removing the sacrificial layer by wet etching.
Illustratively, the wet etching method can employ a hydrofluoric acid solution, such as a Buffered Oxide Etchant (BOE) or a buffered hydrofluoric acid (BHF).
By growing a layer of silicon Oxide in the groove as a sacrificial layer and then etching and bleaching the sacrificial layer by a wet method, the surface damage caused by deep groove etching can be weakened, and the Gate Oxide Integrity (GOI) capability of the side wall is improved.
Next, step S103 is performed to obtain the device structure shown in fig. 2C. And forming a dielectric layer 204 on the side wall of the groove 203.
First, referring to fig. 2B, the steps are performed: a thermal treatment is performed to form a dielectric layer 204' on the mask layer 202 and on the inner walls of the recess 203.
Illustratively, a dielectric layer 204 'is formed on the mask layer 202 and on the inner wall of the groove 203 by performing a thermal treatment, wherein the dielectric layer 204' is a gate oxide layer. In this embodiment, a silicon oxide layer is grown on the mask layer 202 and the inner wall of the groove 203 by using a furnace process to serve as a dielectric layer 204 ', and the thickness of the dielectric layer 204' is 200 angstroms to 1000 angstroms. Specifically, the wet oxidation is performed by introducing water vapor into the furnace tube, and compared with the dry oxidation performed without introducing water vapor into the furnace tube, the wet oxidation method has higher oxidation speed and is beneficial to forming a thicker dielectric layer.
Next, referring to fig. 2C, the steps are performed: and performing self-aligned etching, removing the dielectric layers on the mask layer 202 and at the bottom of the groove 203 through anisotropic gas etching, and reserving the dielectric layer 204 on the side wall of the groove 203.
Illustratively, the dielectric layer 204' on the mask layer 202 and at the bottom of the groove 203 may be removed by dry etching. Illustratively, the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used. The source gas for the dry etch may include a chlorine or bromine chemistry gas (e.g., HBr) and/or a fluorine-based gas (e.g., CF)4) Wherein chlorine or bromine chemical gases can produce anisotropic etching and have a good selectivity to silicon oxide.
Next, step S104 is performed to obtain the device structure shown in fig. 2D. An implanted region 205 is formed in the semiconductor substrate at the bottom of the recess 203.
Illustratively, a self-aligned ion implantation is performed into the semiconductor substrate 200 at the bottom of the recess 203 with the mask layer 202 as a mask to form a self-aligned implantation region in the semiconductor substrate 200. In one embodiment, the semiconductor substrate 200 is a P-type substrate and the implanted region 205 is a P-type ion implanted region, i.e., the conductivity type of the implanted region 205 is the same as the conductivity type of the semiconductor substrate 200.
The P-type ion implantation region is formed in the semiconductor substrate at the bottom of the groove only by self-aligned ion implantation, and the other positions of the semiconductor substrate 200 cannot be implanted due to the blocking of the mask layer 202 and the dielectric layer 204, so that a new photoetching plate is not required to be added to define the ion implantation region, the process steps are reduced, and the cost is saved.
Next, step S105 is performed to obtain the device structure shown in fig. 2E. And filling a conductive material 206 in the groove 203 to form an isolation structure consisting of the dielectric layer 204 and the conductive material 206 in the semiconductor substrate 200.
In one embodiment, a furnace tube grows a conductive material 206, the conductive material 206 is covered on the mask layer 202, and the conductive material 206 is filled in the groove 203.
Illustratively, the conductive material comprises polysilicon. The polysilicon is formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process. The process conditions for forming the polysilicon include: the reaction gas is Silane (SiH)4) The flow rate of the silane can be 350-450 cubic centimeters per minute (sccm), such as 400 sccm; the temperature range in the reaction cavity can be 500-600 ℃; the pressure in the reaction chamber can be 300-400 milli-millimeter mercury (mTorr), such as 350 mTorr; the reaction gas can also comprise a buffer gas, the buffer gas can be helium or nitrogen, and the flow range of the helium and the nitrogen can be 5-20 liters per minute (slm), such as 8slm, 10slm or 15 slm.
Compared with the method of directly filling the groove through Chemical Vapor Deposition (CVD), firstly, a dielectric layer is formed on the side wall of the groove, and then polycrystalline silicon is grown through low-pressure chemical vapor deposition (LPCVD) to obtain a better deep groove filling effect. Meanwhile, the bottom of the polycrystalline silicon is connected with the silicon substrate at the bottom of the groove by filling the polycrystalline silicon in the groove, the polycrystalline silicon is used as a conductor to lead out the injection region 205 of the semiconductor substrate, a substrate (sub) electrode is formed on the surface of the semiconductor substrate, the area does not need to be increased as a sub electrode lead-out region, and the area of the semiconductor substrate is reduced. Furthermore, the polysilicon in the groove can also be used as a longitudinal field plate, so that the average electric field of the longitudinal drift region is increased, the electric field peak value is reduced, the purposes of inhibiting the hot carrier effect, improving the breakdown voltage and the like are achieved, and the performance of the LDMOS is further improved. Specifically, the dielectric layer 204 and the conductive material 206 are formed by using a common furnace tube, and no cavity exists in the dielectric layer 204 and the conductive material 206, that is, by using the preparation method of the present application, a good deep trench filling effect can be obtained by using only the common furnace tube.
Next, after filling the conductive material 206 in the groove 203, the following steps are further included to obtain the device structure shown in fig. 2F.
In one embodiment, first, with the mask layer 202 as a barrier layer, the conductive material 206 on the mask layer 202 and a portion of the conductive material 206 in the groove 203 are etched away, so that an upper surface of the remaining conductive material 206 in the groove 203 is flush with an upper surface of the semiconductor substrate 200.
Illustratively, the polysilicon is removed using a dry etch. Dry etching includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Preferably, the dry etching is performed by one or more RIE steps. As an example, plasma etching is used, and the etching gas may be a nitrogen-based gas. Specifically, the dry etching of the polysilicon is realized by using lower radio frequency energy and generating low-pressure and high-density plasma gas. The etching gas used is a nitrogen-based gas, and the flow rate of the etching gas is as follows: 100-200 cubic centimeters per minute (sccm); the pressure in the reaction chamber can be 30-50 mTorr, the etching time is 10-15 seconds, the power is 30-80W, and the bias power is 0W.
Next, the mask layer 202 on the semiconductor substrate 200 and a portion of the dielectric layer 204 in the groove 203 are removed, an upper surface of the remaining dielectric layer 204 in the groove 203 is flush with an upper surface of the remaining conductive material 206 in the groove 203, and the dielectric layer 204 and the conductive material 206 in the groove 203 form the isolation structure. That is, after the mask layer 202 on the semiconductor substrate 200 and a portion of the dielectric layer 204 in the groove 203 are removed, the upper surface of the semiconductor substrate 200, the upper surface of the dielectric layer 204 in the groove 203, and the upper surface of the conductive material 206 in the groove 203 are on the same plane.
Illustratively, the mask layer 202 and a portion of the dielectric layer 204 may be removed by dry etching, wet etching or grinding. Dry etching processes include, but are not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used. The source gas for the dry etch may comprise HBr and/or CF4A gas.
In another embodiment, the mask layer 202, a portion of the conductive material 206, and a portion of the dielectric layer 204 on the semiconductor substrate 200 may be removed by Chemical Mechanical Polishing (CMP) to expose the semiconductor substrate 200 and the isolation structure.
In another embodiment, the method of fabricating a semiconductor device further includes fabricating other structures of the semiconductor device in the well region.
The structure of the semiconductor device provided by the embodiment of the invention is described below with reference to fig. 2F. The semiconductor device includes:
a semiconductor substrate 200, wherein a well region 201 and a groove arranged around the well region 201 are formed in the semiconductor substrate 200;
an implanted region 205, the implanted region 205 being located in the semiconductor substrate 200 at the bottom of the recess;
the isolation structure comprises a conductive material 206 filling the recess and a dielectric layer 204 located between the conductive material 206 and the sidewall of the recess 203.
Illustratively, the semiconductor device comprises an LDMOS device.
Illustratively, the semiconductor substrate 200 may be at least one of the following mentioned materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In this embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and the specific doping concentration is not limited by the present invention, and the semiconductor substrate 200 may be formed by epitaxial growth, or may be a wafer substrate.
Illustratively, the semiconductor substrate 200 has a well region 201 formed therein, and the well region 201 has a different doping type from the semiconductor substrate 200. In the present embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and the well 201 is an N-type well.
Illustratively, a mask layer 202 is formed on the semiconductor substrate 200. The mask layer 202 includes a stacked structure of an oxide layer, a nitride layer, or both.
Illustratively, the depth of the groove 203 is greater than the depth of the well region 201.
Illustratively, the groove 203 is a groove with a high aspect ratio, the aspect ratio of the groove 203 is greater than 5:1, specifically, the width of the groove 203 ranges from 0.8 μm to 3 μm, and the depth of the groove 203 ranges from 8 μm to 15 μm.
Illustratively, the sidewall of the groove 203 is a vertical sidewall, that is, the sidewall of the groove 203 is vertical to the plane of the semiconductor substrate 200. The topography of the vertical sidewalls facilitates the subsequent implementation of a self-aligned implant of the implanted region at the bottom of the recess 203.
Illustratively, the semiconductor substrate 200 at the bottom of the groove 203 is formed with an implanted region 205, the implanted region 205 is a self-aligned implanted region, and the implanted region 205 is a P-type ion implanted region, i.e., the conductivity type of the implanted region 205 is the same as the conductivity type of the semiconductor substrate 200.
Illustratively, an isolation structure is formed in the groove 203. The isolation structure includes a conductive material 206 filling the recess and a dielectric layer 204 between the conductive material 206 and the sidewalls of the recess.
Illustratively, the dielectric layer 204 comprises a silicon oxide layer, and the thickness of the dielectric layer 204 is in the range of 200 angstroms to 1000 angstroms.
Illustratively, the conductive material comprises polysilicon, and the conductive material is electrically connected with a substrate electrode on the surface of the semiconductor substrate.
By filling the polycrystalline silicon in the groove, the connection between the bottom of the polycrystalline silicon and the silicon substrate at the bottom of the groove is realized, the polycrystalline silicon is used as a conductor to lead out the injection region 205 of the semiconductor substrate, a sub electrode is formed on the surface of the semiconductor substrate, no additional area is needed to be used as a sub electrode lead-out region, and the area of the semiconductor substrate is reduced. Furthermore, the polysilicon in the groove can also be used as a longitudinal field plate, so that the average electric field of the longitudinal drift region is increased, the electric field peak value is reduced, the purposes of inhibiting the hot carrier effect, improving the breakdown voltage and the like are achieved, and the performance of the LDMOS is further improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.