CN113485875B - Chip verification system and verification method - Google Patents
Chip verification system and verification method Download PDFInfo
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- CN113485875B CN113485875B CN202110550341.6A CN202110550341A CN113485875B CN 113485875 B CN113485875 B CN 113485875B CN 202110550341 A CN202110550341 A CN 202110550341A CN 113485875 B CN113485875 B CN 113485875B
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
- G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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Abstract
The application provides a chip verification system and a chip verification method, comprising at least one TM chip and at least one SW chip, wherein at least one serial communication link is arranged between each TM chip and each SW chip, each TM chip and each SW chip are obtained by respectively adopting SystemC modeling, and each TM chip and each SW chip are respectively provided with a communication service process corresponding to the serial communication link. Each TM chip transmits the first data to the SW chip through the corresponding serial communication link by utilizing the communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by utilizing the communication service process in the TM chip; each SW chip transmits the second data to the TM chip via the corresponding serial communication link using the communication service process therein, such that the TM chip reads the second data from the corresponding serial communication link using the communication service process therein.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a chip verification system and a verification method.
Background
The frame Switch generally comprises a plurality of flow forwarding (TRAFFIC MANAGEMENT, TM) chips and a plurality of Switching (SW) chips, wherein the TM chips are responsible for the services of message forwarding, queue management, flow management and the like, the SW chips are responsible for the forwarding of cells, and the TM chips and the SW chips belong to the same solution scheme and cooperate to complete the processing of large-scale data messages. In order to complete the design of the ultra-large scale integrated circuit, a simulation verification model of the chip needs to be established in a pre-grinding stage of the chip, namely, the TM chip and the SW chip need to be verified, namely, the architecture, the algorithm and the function of the chip are verified at a higher level of abstraction, and meanwhile, complicated gate-level and RTL-level hardware description is not trapped, so that the normal use of the following TM chip and SW chip is ensured.
At present, when a chip is verified, the verification is generally performed through an established SystemC verification model, wherein SystemC is a system modeling language which is supported and maintained by Open SYSTEMC INITIATIVE (OSIC) and is a group of libraries developed on the basis of C++. By establishing a verification model through SystemC, the functions of message forwarding, queue management, qoS, routing strategy and the like of the switching chip solution and related algorithms can be verified and evaluated for performance, and the verification model is used as a reference for subsequent hardware development. However, the existing modeling scheme based on SystemC generally describes a single chip architecture. The method comprises the steps of describing sequential logic or combinational logic of subsystems in a chip by using a module (module) provided by a system C and a corresponding method and thread (thread), describing input and output signals of the subsystems through a port (port), connecting ports among the subsystems through signals (signal), and defining a clock signal as a trigger signal of each module so as to establish a model of the whole chip. However, the method only meets the verification requirement of a single chip, and cannot meet the requirement of simultaneous verification of a TM chip and an SW chip under the solution of a frame switch. And cannot be applied to various scenes of structural changes when a plurality of TM chips and a plurality of SW chips are included in a frame switch.
Therefore, how to verify both the TM chip and the SW chip simultaneously is one of the technical problems that are worth considering.
Disclosure of Invention
In view of the above, the present application provides a chip verification system and a verification method for implementing simultaneous verification of a TM chip and a SW chip.
Specifically, the application is realized by the following technical scheme:
according to a first aspect of the present application, there is provided a chip authentication system comprising at least one traffic management TM chip and at least one switch SW chip, each TM chip having at least one serial communication link between each SW chip and each TM chip, each TM chip and each SW chip being modeled using a system modeling language SystemC, respectively, each TM chip being provided with a communication service process corresponding to the serial communication link, each SW chip being provided with a communication service process corresponding to the serial communication link, wherein:
Each TM chip transmits first data to the SW chip through a corresponding serial communication link by utilizing a communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by utilizing the communication service process in the TM chip;
each SW chip sends the second data to the TM chip through the corresponding serial communication link by using the communication service process therein, so that the TM chip reads the second data from the corresponding serial communication link by using the communication service process therein.
According to a second aspect of the present application, a chip verification method is provided, which is applied to a traffic management TM chip in a chip verification system, where the chip verification system further includes a switch SW chip, at least one serial communication link is provided between the TM chip and the SW chip, the TM chip and the SW chip are obtained by modeling using a system modeling language SystemC, the TM chip is provided with a communication service process corresponding to the serial communication link, and the SW chip is provided with a communication service process corresponding to the serial communication link; the method comprises the following steps:
The TM chip sends first data to the SW chip through a corresponding serial communication link by utilizing a communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by utilizing the communication service process in the TM chip and executes corresponding verification operation;
The TM chip reads the second data transmitted by the SW chip from the corresponding serial communication link by using a communication service process therein and performs a corresponding verification operation.
According to a third aspect of the present application, a chip verification method is provided, which is applied to a switch SW chip in a chip verification system, where the chip verification system further includes a traffic management TM chip, at least one serial communication link is provided between the SW chip and the TM chip, the SW chip and the TM chip are obtained by modeling using a system modeling language SystemC, the SW chip is provided with a communication service process corresponding to the serial communication link, and the TM chip is provided with a communication service process corresponding to the serial communication link; the method comprises the following steps:
The SW chip reads first data sent by the TM chip from a corresponding serial communication link by utilizing a communication service process in the SW chip, and executes corresponding verification operation by utilizing the first data;
The SW chip sends the second data to the TM chip through the corresponding serial communication link by utilizing the communication service process in the SW chip, so that the TM chip reads the second data from the corresponding serial communication link by utilizing the communication service process in the TM chip and executes the corresponding verification operation.
The embodiment of the application has the beneficial effects that:
According to the chip verification system provided by the embodiment, the TM chip and the SW chip can perform data transmission through the serial communication link between the two chips, namely, the TM chip and the SW chip can perform data interaction through respective communication service processes, so that verification of data transmission functions of the TM chip and the SW chip can be completed, verification of functions (except verification related to data interaction functions) of the TM chip and the SW chip is combined, simultaneous verification of each TM chip and each SW chip can be realized, and the problems of poor verification efficiency and poor networking flexibility caused by single chip verification in the prior art are solved.
Drawings
Fig. 1 is a schematic structural diagram of a chip verification system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another chip verification system according to an embodiment of the present application;
Fig. 3 is a schematic diagram of a link between TM chip 1 and TM chip 2 according to an embodiment of the present application;
Fig. 4 is a schematic flow chart of a chip verification method according to an embodiment of the present application;
fig. 5 is a flowchart of another chip verification method according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the corresponding listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.
The chip verification system provided by the application is described in detail below.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip verification system provided by the present application, where the chip verification system includes at least one TM chip and at least one SW chip, at least one serial communication link is provided between each TM chip and each SW chip, each TM chip and each SW chip are obtained by modeling using a system modeling language SystemC, each TM chip is provided with a communication service process corresponding to the serial communication link, and each SW chip is provided with a communication service process corresponding to the serial communication link, where:
Each TM chip transmits first data to the SW chip through a corresponding serial communication link by utilizing a communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by utilizing the communication service process in the TM chip;
each SW chip sends the second data to the TM chip through the corresponding serial communication link by using the communication service process therein, so that the TM chip reads the second data from the corresponding serial communication link by using the communication service process therein.
Specifically, each TM chip and each SW chip are independent SystemC models that can run on hosts with different IP addresses to enable verification of each TM chip and each SW chip. It should be noted that, different numbers of TM chips and different numbers of SW chips are formed in different switch structures, but verification of TM chips and SW chips in switches with different structures may all employ the chip verification system provided by the present application. When the chip verification system provided by the embodiment is utilized for verification, the functions of the TM chip and the SW chip can be verified through interaction between the modules. For example, in TM chip authentication, the functions that need to be authenticated may be, but are not limited to, authentication for a scheduling algorithm, authentication for a traffic shaping function, authentication for an assigned flow proportion function, authentication for a queue scheduling function, and so on; when the SW chip performs verification, the functions required to be verified may be, but are not limited to, verification including a message forwarding function, where the message forwarding function may involve functions such as table lookup and forwarding. And the verification of the interactive function related between the TM chip and the SW can be performed through the communication service process in the two chips and the serial communication link between the two chips so as to complete the verification of the related function.
The first data may be test data, such as a test message, etc., and the second data may be, but is not limited to, response data of the first data, such as a response message, etc. It should be noted that, in the verification process of the TM chip and the SW chip, the data related to the interaction between the two chips may be interacted through the serial communication link between the TM chip and the SW chip, but the specific verification process of the chips please refer to the verification method provided at present, and will not be described in detail here. For ease of understanding, a simple example is given here to describe the test procedure of the related functions of the TM chip and the SW chip. For example, when the TM chip needs to test the traffic scheduling capability, the first data to be scheduled in the TM chip may be transmitted to the serial communication link corresponding to the communication service process through the communication service process in the TM chip, then the communication service process corresponding to the serial communication link in the SM chip may read the first data from the serial communication link, and then the SW chip may find, by looking up a routing table, a forwarding table, etc., the destination address of the first data, and forward the first data to the network device corresponding to the destination address, and if the forwarding is successful, it may indicate that the forwarding function of the SW chip is normal, and may confirm that the traffic scheduling capability of the TM chip is also normal.
It should be noted that, the number of TM chips and SW chips included in the chip verification system provided in this embodiment may be determined according to an actual networking environment, and may be changed according to the number of chips in the actual networking environment, so as to adapt to flexible changes of networking.
According to the chip verification system provided by the embodiment, the TM chip and the SW chip can perform data transmission through the serial communication link between the two chips, namely, the TM chip and the SW chip can perform data interaction through respective communication service processes, so that verification of data transmission functions of the TM chip and the SW chip can be completed, verification of functions (except verification related to data interaction functions) of the TM chip and the SW chip is combined, simultaneous verification of each TM chip and each SW chip can be realized, and the problems of poor verification efficiency and poor networking flexibility caused by single chip verification in the prior art are solved.
Optionally, the communication service process corresponding to each serial communication link includes a client process and a server process; each TM chip sends the first data to the SW chip through the corresponding serial communication link by using the client process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by using the server process in the TM chip; each SW chip sends the second data to the TM chip through the corresponding serial communication link by using the client process in the SW chip, so that the TM chip reads the second data from the corresponding serial communication link by using the server process in the TM chip.
Specifically, the serial communication link provided by the application is a bidirectional serial communication link, on the basis, each TM chip is provided with a communication service process corresponding to the serial communication link, which comprises a client process and a server process, and similarly, each SW chip is provided with a communication service process corresponding to the serial communication link, which comprises a client process and a server process. On the basis, one bidirectional serial communication link in the embodiment comprises a unidirectional communication link in which the TM chip points to the direction of the SW chip and a unidirectional communication link in which the SW chip points to the direction of the TM chip. In order to realize a serial communication link between the TM chip and the SW chip, a client process and a server process need to be set on the TM chip side, and similarly, a client process and a server process need to be set on the SW chip side, that is, a serial communication link corresponds to a client process and a server process on the TM chip side, and corresponds to a client process and a server process on the SW chip side. Then the client process at the TM chip side and the service process at the SW chip side simulate forming a unidirectional communication link of the TM chip pointing to the direction of the SW chip, and the client process at the SW chip side and the service process at the TM chip side simulate forming a unidirectional communication link of the SW chip pointing to the direction of the TM chip, so that a serial communication link between the TM chip and the SW chip can be formed, and one client process and one service process form a pair of client process and service process, which can be called a pair of communication service process, so that one serial communication link needs 2 pairs of client process and service process, namely 2 pairs of communication service process; and when a plurality of serial communication links are included between the TM chip and the SW chip, a plurality of pairs of communication service processes are arranged in the TM chip and the SW chip.
Further, the client process in each pair of communication service processes is used for performing data sending operation, and the server process is used for performing data reading operation. That is, when the TM chip sends the first data, the client process in the TM chip may be called to send the first data to the serial communication link corresponding to the client, so that the server process in the SW chip corresponding to the serial communication link may read the first data from the serial communication link and perform the related verification operation. Similarly, when the SW chip sends the second data to the TM chip, the SW chip may call the client process therein to send the second data to the corresponding serial communication link, and then the server process in the TM chip may call the server process thereon to read the second data from the serial communication link, and then perform the related verification operation.
Alternatively, the serial communication link provided in this embodiment may be a SerDes link (bidirectional SerDes link), where each SerDes link is simulated by a communication service process located in the TM chip and the SW chip, for example, a client process located in the TM chip and a server process located in the SW chip simulate a unidirectional SerDes link where the TM chip points to the SW chip, and similarly, a client process located in the SW chip and a server process located in the TM chip simulate a unidirectional SerDes link where the SW chip points to the TM chip, and these two unidirectional SerDes links form the bidirectional SerDes link described above. Accordingly, the communication service process in any of the above embodiments of the present application may be, but is not limited to, a Socket process, on the basis of which a Socket process corresponding to a SerDes link includes 2 Socket client processes and 2 Socket server processes, that is, 2 pairs of Socket processes, where 1 Socket client process and 1 Socket server process are set in the TM chip, and 1 Socket client process and 1 Socket server process are set in the SW chip.
For better understanding of the chip authentication system provided in the present embodiment, a chip authentication system including 2 TM chips and 2 SW chips shown in fig. 2 will be described as an example. Each of the chips (TM chip, SW chip) in fig. 2 is an independent SystemC model, and then uses 2 pairs of Socket processes to simulate a bidirectional SerDes link between TM chip and SW chip to support full duplex operation mode. The system C model of each chip (TM chip, SW chip) maintains a plurality of Socket processes, for each TM chip and SW chip, each Socket process in the chip only processes one operation of sending data or reading data, for example, TM chip (TM chip 1 and TM chip 2) in fig. 2 includes a plurality of Socket processes, SW chip (SW chip 1 and SW chip 2) includes a plurality of Socket processes, socket Ai in TM chip (TM chip 1 and TM chip 2) is a Socket client process, socket Bi is a server process, socket Ci in SW chip (SW chip 1 and SW chip 2) is a Socket client process, socket Di is a server process, i.e. Socket A1 in TM chip 1 and Socket D1 in SW chip 1 in fig. 2 form a unidirectional SerDes link in which TM chip points to SW chip, socket C1 in SW chip 1 and Socket B1 in SW chip 1 form a unidirectional link in which Socket D1 points to SW chip, and so on. On the basis, the TM chip only uses Socket Ai for transmitting operation and only uses Socket Bi for reading operation; accordingly, only Socket Ci is used in the SW chip for transmission operation, and only Socket Di is used for reading operation.
On this basis, when the TM chip 1 interacts with the SW chip 1, the TM chip 1 may use Socket A1 therein to send the first data to a SerDes link corresponding to Socket A1, where the SerDes link is connected to the SW chip 1 side by Socket D1, and the SW chip 1 may use Socket D1 to read the first data sent by the TM chip 1 from the SerDes link. Similarly, when the SW chip 1 needs to send the second data to the TM chip 1, the SW chip 1 may send the second data to the SerDes link corresponding to the Socket C1 by using the Socket C1 therein, and the SerDes link corresponding to the Socket C1 is connected to the TM chip 1 by the Socket B1, so that the TM chip 1 may read the second data from the SerDes link by using the Socket B1, thereby implementing verification of the related exchange function between the TM chip 1 and the SW chip 1.
Based on any of the above embodiments, each TM chip and each SW chip respectively includes an interface module for maintaining the communication service process.
Specifically, further referring to fig. 2, the interface module of the SystemC model of each chip (TM chip or SW chip) is responsible for maintaining Socket processes and processing Socket events, including sending data, receiving data, and Socket listening. For example, a Socket process responsible for sending data is implemented by a Socket client process, and a Socket process responsible for reading data is implemented by a Socket server process. For easy understanding, please refer to fig. 3, in which a Socket server process and a Socket client process are maintained in an interface module of a SystemC model of a chip (TM chip or SW chip) to simulate a SerDes link, and in fig. 3, a Socket server process and a Socket client simulate 2 full duplex SerDes links, namely a SerDes link 1 and a SerDes link 2, respectively, between a TM chip 1 and a SW chip 1, specifically: the SerDes link 1is formed by a unidirectional SerDes link of which the TM chip 1 points to the SW chip 1 and which is formed by a Socket Client process 1 (marked as Client 1) in the TM chip 1 and a Socket Server process 1 (marked as Server 1) in the SW chip 1, and a unidirectional SerDes link of which the TM chip 1 points to the TM chip 1 and which is formed by a Socket Client process 2 (marked as Client 2) in the SW chip 1 and a Socket Server process 2 (marked as Server 2) in the TM chip 1; whereas the SerDes link 2 is constituted by one unidirectional SerDes link in which TM chip 1is directed to SW chip 1, constituted by Socket Client process 3 (denoted as Client 3) in TM chip 1 and Socket Server process 3 (denoted as Server 3) in SW chip 1, and one unidirectional SerDes link in which SW chip 1is directed to TM chip 1, constituted by Socket Client process 4 (denoted as Client 4) in SW chip 1 and Socket Server process 4 (denoted as Server 4) in TM chip 1. Based on the SerDes link shown in fig. 3, data interaction between the TM chip 1 and the SW chip 1 can be performed, so as to realize chip verification of the TM chip 1 and the SW chip 1 at the same time.
In an actual environment, for modeling of multiple chips, it is generally assumed that a SerDes link between the chips does not lose packets, for a SystemC model of one chip, a packet to be sent is sent to a corresponding server process by a Socket client process every clock cycle on a Socket client process side, and data outside the SystemC model (chip) is received by the Socket server process on the Socket server side, so that the number of Socket events to be processed is not necessarily required (including receiving data and restarting a listening port after closing a Socket connection) in each clock cycle, but the time consumed for processing different Socket events should be different in simulation (for example, the time consumed for receiving data should be less than the time consumed for restarting the listening port after closing the Socket connection), and therefore, operations for reading data should be decoupled from the listening events. Specifically, the present application proposes to perform the above decoupling operation by means of a global Quantum Keeper of SYSTEMC TLM.
On the basis, the interface module adjusts the counter based on the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
Specifically, for each chip (TM chip and SW chip), the global quantum time may be configured according to the simulation cycle to advance the chip to the next simulation clock cycle, that is, the global quantum time is the time for advancing the simulation to the next simulation clock cycle. The global quantum time may be configured with set global quanta in the initialization phase. It should be noted that the above-mentioned simulation clock period should be the same as the clock period of the chip. And then setting a counter for the communication service process in the interface module, and controlling the time of the communication service process entering the next simulation clock period by adjusting the value of the counter to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in each simulation clock period.
Optionally, the communication service process maintained by the interface module in each chip (TM chip and SW chip) is a server process, and the interface module may determine whether the server process is disconnected; if the counter is disconnected, the counter is adjusted to a first value; if not, the server process is adjusted to a second value; then the interface module judges whether the numerical value of the counter is not less than the global quantum time; if not, monitoring the server process; and continuing to execute the step of judging whether the server process is disconnected.
Specifically, the interface module may determine whether a communication connection established by the server process is disconnected, and if the connection is disconnected, it indicates that a disconnection event occurs, and adjust the counter to a first value; if not, continuing to read the data by using the server process, continuing to monitor the server process, and adjusting the counter to a second value; then the interface module judges whether the numerical value of the counter is not less than the set global quantum time, if so, the simulation period is not finished, and monitoring is needed to be carried out on the server process continuously, namely the server process continuously executes the operation of reading data; if the value of the counter is smaller than the global quantum time, the end of the current simulation clock cycle is indicated, and the next simulation clock cycle needs to be advanced.
It should be noted that, the numerical value of the counter in this embodiment is used to characterize the simulation progress of the interface module in this simulation clock period.
It should be noted that, when the communication connection established by the server process is determined to be disconnected, the server process continues to monitor the server, because the server process may reestablish the communication connection at any time, and then continues to execute the step of determining whether the communication connection established by the server process is disconnected.
After the interface module executes the numerical value adjustment of the counter, the numerical value of the counter can be pushed by calling the inc method of the Keeper, then the numerical value of the counter is compared with the global quantum time, different values are given to the counter according to different Socket events, the simulation time can be pushed to different degrees until the global quantum time is reached, at the moment, the Sync of the Keeper is called for synchronization, then the process of the interface module is jumped out, and the next simulation clock period is entered.
It should be noted that, before executing the step of determining whether the server process is disconnected, the interface module may initialize the global quantum time, then create the server process, bind the server process with the port after the server process is created, so that the server process establishes a communication connection through the bound port, and the communication connection established by the server process and the communication connection established by the client process in the opposite chip form the unidirectional serial communication connection. Then the interface module can monitor the port of the binding port, and then execute the step of judging whether the process of the server is disconnected.
For better understanding of the above procedure, the Server process is a Socket Server process (denoted as Socket Server process), and the following examples are described, where the first value may be, but not limited to, 10, and the second value may be, but not limited to, 4, to describe monitoring of the Server process by the interface module:
step 1: initializing global quantum time, in this example configured as 20;
Step 2: creating a Socket Server process;
Step 3: socket Server process binding Port;
step 4: the Socket Server process monitors the Port of the binding;
Step 5: invoking a Select function of a Socket to trigger a Socket monitoring event;
step 6: judging whether Socket connection established by a Socket Server process is closed, if the Socket connection is closed, jumping to Step 7, and if the Socket connection is not closed, jumping to Step 10;
step 7: the value of the counter advances by 10, namely the value of the counter is increased by 10;
Step 8: comparing the value of the counter with the set global quantum time, if the value is not smaller than the global quantum time, jumping to Step 9, and if the value is smaller than the global quantum time, jumping to Step 5;
step 9: executing Keeper synchronization, simulating to enter the next period, and jumping to Step 5;
step 10: reading data by using a Socket Server process;
Step 11: the value of the counter advances forward by 4;
Step 12: comparing the value of the counter with the set global quantum time, jumping to Step 13 if the value is not smaller than the global quantum time, and jumping to Step 5 if the value is smaller than the global quantum time;
Step 13: executing Keeper synchronization, simulating to enter the next period, and jumping to Step 5;
By implementing the chip verification system provided by the application, a multi-chip distributed simulation model which is difficult to construct by a single SystemC model is constructed, and due to the use of a SerDes link between Socket process simulation chips (TM chip and SW chip), a chip network has good expandability, and development efficiency is improved. The Socket processing and the model clock are decoupled through the Keeper, so that the simulation time can be advanced to different degrees for processing different Socket events, and the time sequence logic of hardware is simulated more accurately.
Based on the same inventive concept, the application also provides a chip verification method, which is applied to a Traffic Management (TM) chip in a chip verification system, wherein the chip verification system also comprises a Switching (SW) chip, at least one serial communication link is arranged between the TM chip and the SW chip, the TM chip and the SW chip are obtained by modeling by adopting a system modeling language (SystemC) respectively, the TM chip is provided with a communication service process corresponding to the serial communication link, and the SW chip is provided with a communication service process corresponding to the serial communication link; when the TM chip implements the chip verification method, the method may be implemented according to a flow shown in fig. 4:
s401, the TM chip sends first data to the SW chip through a corresponding serial communication link by utilizing a communication service process in the SW chip, so that the SW chip reads the first data from the corresponding serial communication link by utilizing the communication service process in the SW chip and performs a corresponding verification operation.
S402, the TM chip reads the second data sent by the SW chip from the corresponding serial communication link by utilizing the communication service process in the TM chip and executes the corresponding verification operation.
It should be noted that, the implementation of steps S401 to S402 may refer to the related description about the TM chip in the above-mentioned chip verification system, and are not listed in detail here.
By adopting the chip verification method, the TM chip and the SW chip can perform data transmission through the serial communication link between the two chips, namely, the TM chip and the SW chip can perform data interaction through respective communication service processes, so that verification of the data transmission functions of the TM chip and the SW chip can be completed, and verification of the functions (except verification related to the data interaction functions) of the TM chip and the SW chip is combined, so that simultaneous verification of each TM chip and each SW chip can be realized, and the problems of poor verification efficiency and poor networking flexibility caused by the fact that only single chip verification can be realized in the prior art are solved.
Optionally, the communication service process corresponding to each serial communication link includes a client process and a server process; on this basis, step S401 may be performed according to the following procedure: the first data is sent to the SW chip via the corresponding serial communication link using the client process therein. On this basis, step S402 may be performed as follows: and reading the second data sent by the SW chip from the corresponding serial communication link by utilizing a service end process in the SW chip.
In particular, the implementation of the above procedure may refer to the description of the client process and the server process by the TM chip, which is not specifically mentioned herein.
Optionally, the TM chip includes an interface module configured to maintain the communication service process; the chip verification method provided in this embodiment further includes:
The TM chip uses the interface module to adjust the counter through the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
In particular, the implementation of the above-described process may refer to the relevant description of the interface module in the chip verification system, which is not specifically enumerated herein.
Based on the same inventive concept, the application also provides a chip verification method, which is applied to an exchange SW chip in a chip verification system, wherein the chip verification system also comprises a flow management TM chip, at least one serial communication link is arranged between the SW chip and the TM chip, the SW chip and the TM chip are obtained by modeling by adopting a system modeling language SystemC respectively, the SW chip is provided with a communication service process corresponding to the serial communication link, and the TM chip is provided with a communication service process corresponding to the serial communication link; when the SW implements the chip verification method, the SW may be implemented according to the procedure shown in fig. 5:
S501, the SW chip reads first data sent by the TM chip from a corresponding serial communication link by utilizing a communication service process in the SW chip, and performs corresponding verification operation by utilizing the first data.
S502, the SW chip sends the second data to the TM chip through the corresponding serial communication link by utilizing the communication service process in the SW chip, so that the TM chip reads the second data from the corresponding serial communication link by utilizing the communication service process in the TM chip and executes the corresponding verification operation.
It should be noted that, the implementation of steps S501 to S502 may refer to the description related to the SW chip in the above-mentioned chip verification system, and are not listed in detail here.
By adopting the chip verification method, the TM chip and the SW chip can perform data transmission through the serial communication link between the two chips, namely, the TM chip and the SW chip can perform data interaction through respective communication service processes, so that verification of the data transmission functions of the TM chip and the SW chip can be completed, and verification of the functions (except verification related to the data interaction functions) of the TM chip and the SW chip is combined, so that simultaneous verification of each TM chip and each SW chip can be realized, and the problems of poor verification efficiency and poor networking flexibility caused by the fact that only single chip verification can be realized in the prior art are solved.
Optionally, the communication service process corresponding to each serial communication link includes a client process and a server process; step S501 may be performed as follows: reading first data sent by the TM chip from a corresponding serial communication link by utilizing a server process in the TM chip; step S502 may be performed as follows: and sending the second data to the TM chip through the corresponding serial communication link by utilizing the client process in the TM chip.
In particular, the implementation of the above procedure may refer to the relevant descriptions of the above SW chip on the client process and the server process, which are not listed in detail here.
Optionally, the SW chip includes an interface module for maintaining the communication service process; on the basis, the chip verification method provided by the embodiment further comprises the following steps: the SW chip uses the interface module to adjust the counter through the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
In particular, the implementation of the above-described process may refer to the relevant description of the interface module in the chip verification system, which is not specifically enumerated herein.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The implementation process of the functions and roles of each unit/module in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be repeated here.
For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The above described apparatus embodiments are merely illustrative, wherein the units/modules illustrated as separate components may or may not be physically separate, and the components shown as units/modules may or may not be physical units/modules, i.e. may be located in one place, or may be distributed over a plurality of network units/modules. Some or all of the units/modules may be selected according to actual needs to achieve the purposes of the present solution. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (11)
1. The chip verification system is characterized by comprising at least one Traffic Management (TM) chip and at least one Switching (SW) chip, wherein at least one serial communication link is arranged between each TM chip and each SW chip, each TM chip and each SW chip are obtained by modeling by using a system modeling language (SystemC), each TM chip is provided with a communication service process corresponding to the serial communication link, and each SW chip is provided with a communication service process corresponding to the serial communication link, and the chip verification system comprises the following steps:
Each TM chip transmits first data to the SW chip through a corresponding serial communication link by utilizing a communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by utilizing the communication service process in the TM chip and executes a corresponding verification operation;
Each SW chip transmits the second data to the TM chip through the corresponding serial communication link by utilizing the communication service process therein, so that the TM chip reads the second data from the corresponding serial communication link by utilizing the communication service process therein and performs the corresponding verification operation.
2. The system of claim 1, wherein the communication service process corresponding to each serial communication link comprises a client process and a server process; then
Each TM chip utilizes a client process therein to send first data to the SW chip through a corresponding serial communication link, so that the SW chip utilizes a server process therein to read the first data from the corresponding serial communication link;
each SW chip sends the second data to the TM chip through the corresponding serial communication link by using the client process in the SW chip, so that the TM chip reads the second data from the corresponding serial communication link by using the server process in the TM chip.
3. The system of claim 1, wherein each TM chip and each SW chip includes an interface module for maintaining the communication service process, respectively;
The interface module adjusts the counter based on the set global quantum time to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
4. A system according to claim 3, wherein the communication service process maintained by the interface module is a server process; then
The interface module judges whether the process of the server side is disconnected; if the counter is disconnected, the counter is adjusted to a first value; if not, the counter is adjusted to a second value;
The interface module judges whether the numerical value of the counter is not less than the global quantum time; if the number is smaller than the preset number, monitoring the server process; and continuing to execute the step of judging whether the server process is disconnected.
5. The system of claim 4, wherein the system further comprises a controller configured to control the controller,
And the interface module monitors the server process by triggering a monitoring event.
6. The chip verification method is characterized by being applied to a Traffic Management (TM) chip in a chip verification system, wherein the chip verification system further comprises a Switching (SW) chip, at least one serial communication link is arranged between the TM chip and the SW chip, the TM chip and the SW chip are obtained by modeling through a system modeling language (SystemC) respectively, the TM chip is provided with a communication service process corresponding to the serial communication link, and the SW chip is provided with a communication service process corresponding to the serial communication link; the method comprises the following steps:
The TM chip sends first data to the SW chip through a corresponding serial communication link by utilizing a communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by utilizing the communication service process in the TM chip and executes corresponding verification operation;
The TM chip reads the second data transmitted by the SW chip from the corresponding serial communication link by using a communication service process therein and performs a corresponding verification operation.
7. The method of claim 6, wherein the communication service process corresponding to each serial communication link comprises a client process and a server process;
Transmitting first data to the SW chip through a corresponding serial communication link using a communication service process therein, including:
Transmitting the first data to the SW chip through a corresponding serial communication link by utilizing a client process therein;
Reading second data transmitted by the SW chip from a corresponding serial communication link by using a communication service process therein, including:
And reading the second data sent by the SW chip from the corresponding serial communication link by utilizing a service end process in the SW chip.
8. The method of claim 6, wherein the TM chip includes an interface module for maintaining the communication service process; the method further comprises the steps of:
the TM chip utilizes the interface module to adjust a counter through the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
9. The chip verification method is characterized by being applied to a switching SW chip in a chip verification system, wherein the chip verification system further comprises a Traffic Management (TM) chip, at least one serial communication link is arranged between the SW chip and the TM chip, the SW chip and the TM chip are obtained by modeling through a system modeling language (SystemC) respectively, the SW chip is provided with a communication service process corresponding to the serial communication link, and the TM chip is provided with a communication service process corresponding to the serial communication link; the method comprises the following steps:
The SW chip reads first data sent by the TM chip from a corresponding serial communication link by utilizing a communication service process in the SW chip, and executes corresponding verification operation by utilizing the first data;
The SW chip sends the second data to the TM chip through the corresponding serial communication link by utilizing the communication service process in the SW chip, so that the TM chip reads the second data from the corresponding serial communication link by utilizing the communication service process in the TM chip and executes the corresponding verification operation.
10. The method of claim 9, wherein the communication service process corresponding to each serial communication link comprises a client process and a server process; then
Reading first data sent by the TM chip from a corresponding serial communication link by utilizing a communication service process therein, including:
reading first data sent by the TM chip from a corresponding serial communication link by utilizing a server process in the TM chip;
transmitting the second data to the TM chip through a corresponding serial communication link by utilizing a communication service process therein, comprising:
And sending the second data to the TM chip through the corresponding serial communication link by utilizing the client process in the TM chip.
11. The method of claim 9, wherein the SW chip includes an interface module for maintaining the communication service process; the method further comprises the steps of:
The SW chip uses the interface module to adjust the counter through the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
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