CN113471138B - Method for preparing semiconductor substrate and semiconductor device - Google Patents

Abstract

The invention provides a method for preparing a semiconductor substrate and a semiconductor device. The method includes: forming an active area and an isolation trench on a semiconductor substrate; depositing an insulating oxide in the isolation trench and on the surface of the active area, wherein the insulating oxide located in the isolation trench is an isolation structure, located The insulating oxide on the surface of the isolation structure and the surface of the active area is an isolation layer; the isolation layer is removed to make the surface of the isolation structure flush with the surface of the active area; the active area is etched to a preset depth to form an active recess Groove; epitaxially growing a semiconductor substrate in an active groove so that the surface of the active region is flush with the surface of the isolation structure. The preparation method of the present invention can eliminate the stress of the isolation structure and the isolation trench, ensure that the active area will not be damaged by stress and cause defects or cracks, and at the same time avoid affecting the mobility of carriers in the channel of the device and affecting the device performance. Improved yield of semiconductor devices.

Description

Preparation method of semiconductor substrate and semiconductor device

Technical field

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a preparation method of a semiconductor substrate and a semiconductor device.

Background technique

During the preparation process of a semiconductor device, an active area and an isolation area between the active areas are usually formed in the semiconductor substrate. To form the isolation area, a shallow trench isolation process is generally used to form a shallow trench, and the shallow trench is filled with insulation. Materials form shallow trench isolation (STI).

Since the material of the shallow trench isolation is different from the semiconductor substrate material, and their thermal expansion coefficients are different, a certain amount of stress will be generated during the STI process. This stress usually damages the structure of the semiconductor substrate, such as forming defects or cracks in the active area, or affecting the mobility of carriers in the channel of the device, thereby affecting device performance, etc., and affecting the yield of semiconductor devices.

The above information disclosed in the Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Contents of the invention

A main object of the present invention is to provide a method for preparing a semiconductor substrate, which can eliminate stress after forming an isolation structure, avoid damage to the semiconductor substrate, and improve the yield of the semiconductor substrate.

Another object of the present invention is to provide a semiconductor device that can eliminate the stress of the isolation structure on the semiconductor device, improve the performance of the semiconductor device, and improve the yield of the semiconductor device.

In order to achieve the above object, the present invention provides a method for preparing a semiconductor substrate, which includes: forming an active area and an isolation trench on a semiconductor substrate; depositing insulation in the isolation trench and on the surface of the active area Oxide, wherein the insulating oxide located in the isolation trench is an isolation structure, and the insulating oxide located on the surface of the isolation structure and the surface of the active area is an isolation layer; remove the isolation layer, so that The surface of the isolation structure is flush with the surface of the active region; etching the active region to a preset depth to form an active groove; epitaxially growing the semiconductor substrate in the active groove , making the surface of the active area flush with the surface of the isolation structure.

According to an exemplary embodiment of the present invention, the preset depth is 0.03˜0.3 μm.

According to an exemplary embodiment of the present invention, the preset depth is 0.15 μm.

According to an exemplary embodiment of the present invention, the insulating oxide is silicon oxide or silicon oxynitride.

According to an exemplary embodiment of the present invention, the process used to deposit the insulating oxide is at least one of atomic layer deposition, chemical vapor deposition, and spin coating.

According to an exemplary embodiment of the present invention, the thickness of the isolation layer is 8-15 nm.

According to an exemplary embodiment of the present invention, a process used to remove the isolation layer is chemical mechanical polishing or wet etching.

According to an exemplary embodiment of the present invention, the epitaxial growth process adopts molecular beam epitaxy or ultra-high vacuum chemical vapor deposition.

According to an exemplary embodiment of the present invention, the semiconductor substrate is single crystal silicon, and the single crystal silicon is epitaxially grown in the active groove.

According to an exemplary embodiment of the present invention, a process used to etch the active region to the predetermined depth is wet etching or dry etching.

According to an exemplary embodiment of the present invention, forming an active region and an isolation trench on the semiconductor substrate includes: forming a photoresist mask on the semiconductor substrate; using the photoresist mask Film etching the semiconductor substrate to form the isolation trench and the active area; and removing the photoresist mask located above the active area.

According to an exemplary embodiment of the present invention, the method further includes: depositing an ion implantation blocking layer on the surface of the semiconductor substrate after epitaxial growth.

According to an exemplary embodiment of the present invention, the thickness of the ion implantation barrier layer is 8-12 nm.

According to an exemplary embodiment of the present invention, the material of the ion implantation blocking layer is silicon dioxide or silicon nitride.

According to another aspect of the present invention, a semiconductor device is provided, including a semiconductor substrate and a functional device located in the semiconductor substrate, wherein the semiconductor substrate is prepared by the method described in any of the above embodiments.

It can be seen from the above technical solutions that the present invention has at least one of the following advantages and positive effects:

After the isolation structure is formed on the semiconductor substrate, the active area between the isolation structures is etched to a preset depth to form an active groove, which can remove the stress of the isolation structure and the isolation trench. Further, by etching the active area in the active groove The epitaxial growth of the semiconductor substrate allows the epitaxially grown semiconductor substrate to adapt to the isolation structure. Therefore, in the semiconductor substrate forming the isolation structure, the above-mentioned stress can be eliminated or minimized, ensuring that the active area will not be affected by Stress damage causes defects or cracks, and at the same time, it avoids affecting the mobility of carriers in the channel of the device and affecting device performance, etc., thereby improving the yield of semiconductor devices.

Description of the drawings

The above and other features and advantages of the present invention will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

FIG. 1 is a flow chart of a method for preparing a semiconductor substrate according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic diagram of using photolithography to form active regions and isolation trenches on a semiconductor substrate according to an exemplary embodiment of the present invention;

FIG. 3 is a schematic diagram showing the formation of active areas and isolation trenches after removing the photoresist according to an exemplary embodiment of the present invention;

Figure 4 is a schematic diagram of depositing an insulating oxide on a semiconductor substrate according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic diagram of a semiconductor substrate with an isolation layer removed according to an exemplary embodiment of the present invention;

6 is a schematic diagram of a semiconductor substrate forming active grooves according to an exemplary embodiment of the present invention;

Figure 7 is a schematic diagram of epitaxial growth of a semiconductor substrate in an edged groove according to an exemplary embodiment of the present invention;

8 is a schematic structural diagram of a semiconductor substrate forming an ion implantation barrier layer according to an exemplary embodiment of the present invention;

FIG. 9 is a one-dimensional stress distribution diagram of a channel surface of a semiconductor device according to an exemplary embodiment of the present invention.

Explanation of reference symbols:

1. Semiconductor substrate; 2. Active area; 3. Isolation trench; 4. Isolation structure; 5. Isolation layer; 6. Active groove; 7. Photoresist mask; 8. Ion implantation blocking layer; d. Preset depth.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art. The same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.

In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part hereof and which show by way of example various exemplary structures in which aspects of the present disclosure may be implemented. It is to be understood that other specific arrangements of components, structures, exemplary devices, systems and steps may be utilized, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, although the terms "on," "between," "within," etc. may be used in this specification to describe various exemplary features and elements of the present disclosure, these terms are used herein for convenience only, such as in accordance with Orientation of the example in the attached figure. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of a structure to fall within the scope of this disclosure. In addition, the terms "first", "second", etc. in the claims are only used as labels and are not numerical limitations of their objects.

The flowcharts shown in the drawings are only illustrative, and do not necessarily include all contents and operations/steps, nor must they be performed in the order described. For example, some operations/steps can be decomposed, and some operations/steps can be merged or partially merged, so the actual order of execution may change according to the actual situation.

In addition, in the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically limited.

The semiconductor substrate includes a semiconductor substrate 1. Isolation structures 4 (shallow trench isolation STI) are usually formed on the semiconductor substrate 1. Active areas 2 are provided between the isolation structures 4, that is, adjacent active areas 2 are separated by Structure 4 is insulatingly separated (see Figure 5).

Shallow trench isolation generally uses insulating materials, such as silicon dioxide, silicon oxynitride, etc., and the semiconductor substrate 1 forming the shallow trench can usually use silicon, silicon carbide, silicon on insulator, stacked silicon on insulator, stacked on insulator Silicon germanium, silicon germanium on insulator or germanium on insulator, etc. Before forming the isolation structure 4 , an isolation trench 3 (shallow trench) is first formed on the semiconductor substrate 1 , and then an insulating material is deposited into the isolation trench 3 to form the isolation structure 4 . However, since the material of the isolation structure 4 is different from the material of the semiconductor substrate 1 , and their thermal expansion coefficients and lattice constants are different, during the deposition process of the isolation structure 4 , there will be a certain stress on the isolation structure 4 and the isolation trench 3 .

This stress can be divided into two types, namely tensile stress and compressive stress. During the preparation process of semiconductor devices, some functional devices will be formed in the semiconductor substrate, such as MOS (field effect transistor) devices formed in the substrate, and conductive channels will be formed between the source and drain regions of the MOS devices. For different types of MOS devices, these stresses can affect the stress distribution on the surface of the conductive channel of the MOS device, which in turn will have a bad effect on the performance of the semiconductor device. For example, for PMOS, tensile stress will affect and reduce The mobility of hole carriers, thereby reducing the on-state current of the device; for NMOS, compressive stress will affect and reduce the mobility of electron carriers, thereby reducing the on-state current of the device. At the same time, this stress will also have an impact on the structure of the semiconductor substrate. When the stress is large enough, it may cause cracks and deformation in the active area 2 of the semiconductor substrate 1, eventually leading to a decline in the performance of the semiconductor device and affecting the quality of the semiconductor device. Rate. Therefore, in the design of integrated circuit structures, it is necessary to effectively remove the influence of this stress.

In order to effectively remove the stress, according to one aspect of the present invention, a method for preparing a semiconductor substrate is provided. As shown in FIGS. 1 to 8 , FIG. 1 shows a flow chart of the preparation method of a semiconductor substrate of the present invention; FIGS. 2 to 8 shows schematic cross-sectional views of the semiconductor substrate in each step of the preparation method of the semiconductor substrate. . As shown in Figure 1, the preparation method of the semiconductor substrate of the present invention includes:

Step S200: Form active region 2 and isolation trench 3 on semiconductor substrate 1.

Step S400: Deposit an insulating oxide in the isolation trench 3 and on the surface of the active area 2, where the insulating oxide located in the isolation trench 3 is the isolation structure 4, and is located on the surface of the isolation structure 4 and the active area 2. The insulating oxide on the surface is the isolation layer 5.

Step S600: Remove the isolation layer 5 to make the surface of the isolation structure 4 flush with the surface of the active area 2 .

Step S800: Etch the active area 2 to a preset depth d to form an active groove 6.

Step S1000: Epitaxially grow the semiconductor substrate 1 in the active groove 6 so that the surface of the active region 2 is flush with the surface of the isolation structure 4 .

In the preparation method of the semiconductor substrate of the present invention, after the isolation structure 4 is formed, the active area 2 between the isolation structures 4 is etched to a predetermined depth d to form an active groove 6, which can remove the isolation structure 4 and the isolation structure 4. The portion of the semiconductor substrate affected by the stress between the trenches 3 is further adapted to the isolation structure 4 by epitaxially growing the semiconductor substrate 1 in the active trench 6, thus forming the isolation structure. In the semiconductor substrate 1 of 4, the above-mentioned stress can be eliminated or minimized, ensuring that the active area 2 will not be damaged by stress and causing defects or cracks, while avoiding stress from affecting the electrical performance of the device, and improving the performance of the semiconductor device. Yield.

The preparation method of the semiconductor substrate of the present invention will be described in detail below.

Step S200: Form active region 2 and isolation trench 3 on semiconductor substrate 1.

A semiconductor substrate 1 is provided, isolation trenches 3 are etched on the semiconductor substrate 1 , and the area between the isolation trenches 3 on the semiconductor substrate 1 forms an active region 2 .

As shown in Figure 2, forming the active region 2 and the isolation trench 3 on the semiconductor substrate 1 specifically includes: forming a photoresist mask 7 on the semiconductor substrate 1, and using the photoresist mask 7 to etch the semiconductor. After the etching of the substrate 1 is completed, the active area 2 is formed on the portion of the semiconductor substrate 1 that is blocked by the photoresist mask 7 , and the unshielded portion is etched into an isolation trench 3 . After that, as shown in FIG. 3 , the photoresist mask 7 located above the active area 2 is removed to form the semiconductor substrate 1 with the isolation trench 3 .

Wherein, dry etching or wet etching process may be used to etch the semiconductor substrate 1 to form the isolation trench 3 . Dry etching can be plasma etching, and the etching gas used in the plasma process can be chlorine. By controlling the amount of etching gas, the degree of etching can be controlled. Wet etching can use concentrated sulfuric acid and hydrogen peroxide as etchants. By adjusting the concentration of the etchant, the degree of etching can also be controlled, thereby controlling the depth of the isolation trench 3 . In some embodiments, the depth of the isolation trench 3 can be 0.2-0.3 μm, for example, 0.22 μm, 0.25 μm or 0.28 μm. Those skilled in the art can control the etching degree according to the actual situation, and then control the depth of the isolation trench 3 Depth is not specifically limited here.

Step S400: Deposit an insulating oxide in the isolation trench 3 and on the surface of the active area 2, where the insulating oxide located in the isolation trench 3 is the isolation structure 4, and is located on the surface of the isolation structure 4 and the active area 2. The insulating oxide on the surface is the isolation layer 5.

The insulating oxide may be silicon oxide (SiO ₂ ) or silicon oxynitride (SiON), and the process for depositing the insulating oxide may be at least one of atomic layer deposition, chemical vapor deposition, and spin coating. In one embodiment, two processes, atomic layer deposition and spin coating, can be used for deposition, so that the insulating oxide can be deposited more uniformly.

As shown in Figure 4, the isolation structure 4 is a shallow trench isolation (STI) located in the isolation trench 3. In order to enable the isolation structure 4 to fill the isolation trench 3, the insulating oxide is deposited into the isolation trench 3. On top of the active area 2 and the isolation structure 4, the deposition is continued to form an isolation layer 5 on the top of the active area 2 and the isolation structure 4. The thickness of the isolation layer 5 may be 8-15 nm, specifically, it may be 10 nm, 12 nm or 13 nm, and is not specifically limited here.

Step S600: Remove the isolation layer 5 to make the surface of the isolation structure 4 flush with the surface of the active area 2 .

As shown in FIG. 5 , the isolation layer 5 is removed to expose the active region 2 and the isolation structure 4 , forming a semiconductor substrate 1 with the isolation structure 4 . The process used to remove the isolation layer 5 may be chemical mechanical polishing (CMP) or wet etching. When using chemical mechanical polishing, the semiconductor substrate 1 can be used as a stop layer. In one embodiment, the semiconductor substrate 1 is silicon, and silicon is used as the stop layer to control the polishing to stop in time and form a layer in the active area 2 Smooth surface. When wet etching is used, the ratio of the etching liquid can be adjusted to adjust the selectivity ratio between the semiconductor substrate 1 and the isolation structure 4 to etch and remove the isolation layer 5 .

Step S800: Etch the active area 2 to a preset depth d to form an active groove 6.

As shown in FIG. 6 , after the isolation layer 5 is removed from the semiconductor substrate 1 , the active region 2 is etched. The etching process can be wet etching or dry etching. The etching gas used in dry etching can be chlorine. By controlling the amount and concentration of the etching gas, the degree of etching can be controlled. Wet etching can use concentrated sulfuric acid and hydrogen peroxide as etchants. By controlling the ratio and concentration of the etchant, the etchant can have a very high selectivity for the semiconductor substrate 1. For example, if the semiconductor substrate 1 is made of silicon, then The adjustable etchant has a high selectivity to silicon, and thus can quickly etch the active region 2 during etching.

As shown in Figure 6, the preset depth d is the depth of the active groove 6, and the preset depth d can be 0.03~0.3μm, for example, it can be 0.05μm, 0.1μm, 0.15μm, 0.2μm, 0.25μm . In one embodiment, the preset depth d is preferably 0.15 μm. The value of the preset depth d can be set according to the depth of the isolation trench 3 and the stress condition. For example, after analysis, the stress mainly exists on the bottom of the isolation trench 3, then the depth of the active trench 6 is smaller than the isolation trench. As for the depth of the trench 3, if stress exists at the bottom of the isolation trench 3 or throughout the isolation trench 3, the depth of the active groove 6 formed by etching the active area 2 can be controlled to be the same as the depth of the isolation trench 3. That is, the preset depth d is not greater than the depth of the isolation trench 3 .

Step S1000: Epitaxially grow the semiconductor substrate 1 in the active groove 6 so that the surface of the active region 2 is flush with the surface of the isolation structure 4 .

As shown in FIG. 7 , after the active groove 6 with the preset depth d is formed, since the material of the semiconductor substrate 1 here has been separated from the isolation structure 4 , the stress in this part is relieved. After that, the semiconductor substrate 1 is epitaxially grown in the active groove 6. During the epitaxial growth process, the material of this part of the semiconductor substrate 1 will adapt to the growth of the isolation structure 4 and will not generate new stress. Therefore, after There will be no stress between the semiconductor substrate 1 formed after epitaxial growth and the isolation structure 4 or only extremely slight stress at the contact interface, ensuring that the active area 2 will not be damaged by stress and causing defects or cracks, while avoiding the isolation structure. 4 creates a gap with the isolation trench 3. In addition, the epitaxial growth process is controlled so that the surface of the active region 2 is flush with the surface of the isolation structure 4. In this way, a stress-relieved semiconductor substrate 1 with the isolation structure 4 is formed.

Among them, the process used for epitaxial growth can be molecular beam epitaxy or ultra-high vacuum chemical vapor deposition. In some embodiments, the material of the semiconductor substrate 1 can be selected to be single crystal silicon, and the single crystal silicon is epitaxially grown in the active groove 6, that is, homoepitaxial growth is used, which can ensure the uniformity of the semiconductor substrate 1. This avoids the generation of new stress and improves the stability of the semiconductor substrate 1 .

Regarding the specific parameters of the epitaxial growth process, those skilled in the art can adjust them according to actual conditions, and will not be described again here.

In some embodiments, as shown in FIG. 8 , the method for preparing a semiconductor substrate according to the embodiment of the present invention further includes: depositing an ion implantation blocking layer 8 on the surface of the semiconductor substrate 1 after epitaxial growth.

The ion implantation blocking layer 8 is an insulating dielectric layer to block ion implantation in subsequent processes. In some embodiments, the thickness of the ion implantation barrier layer 8 can be 8-12 nm, for example, 9 nm, 10 nm or 11 nm. Those skilled in the art can adjust it according to process conditions and actual conditions, and there is no special limitation here. The material of the ion implantation blocking layer 8 can be silicon dioxide or silicon nitride, and the deposition process can be atomic layer deposition or chemical vapor deposition.

In summary, in the preparation method of a semiconductor substrate of the present invention, after forming the isolation structure 4 in the semiconductor substrate 1, the active area 2 between the isolation structures 4 is etched to a predetermined depth d to form the active groove 6. The stress of the isolation structure 4 and the isolation trench 3 can be removed, and the semiconductor substrate 1 is epitaxially grown in the active groove 6 so that the epitaxially grown semiconductor substrate 1 adapts to the isolation structure 4. Therefore, after forming the isolation structure 4 In the semiconductor substrate 1, the above-mentioned stress can be eliminated or minimized, ensuring that the active area 2 will not affect the electrical performance of the device due to the presence of stress, while avoiding gaps between the isolation structure 4 and the isolation trench 3, improving improve the yield of semiconductor devices.

According to another aspect of the present invention, an embodiment of the present invention provides a semiconductor device, which includes a semiconductor substrate and a functional device, such as a MOS device, formed in the semiconductor substrate. The semiconductor substrate is prepared by the method described in any of the above embodiments, and will not be described again here.

As shown in Figure 9, the one-dimensional stress distribution diagram of the conductive channel surface at the bottom of the functional device in the semiconductor device is shown. The abscissa in Figure 9 represents the distance between the channel center of the functional device formed on the semiconductor substrate and the left and right sides. The distance between the isolation structures, the channel center is located at X 0μm, and the ordinate represents the stress value. As can be seen from Figure 9, in the semiconductor substrate manufactured by the method of the present invention, since the stress between the isolation structure and the semiconductor substrate is eliminated or greatly weakened, the stress on the channel surface of the semiconductor device finally formed on the substrate is compared with The existing technology has been greatly improved, and the channel surface stress has been greatly reduced. Therefore, the stability of the semiconductor device according to the embodiment of the present invention has been improved, and the production yield of the finished product has also been greatly improved.

It should be understood that the present invention is not limited in its application to the detailed structure and arrangement of components set forth in this specification. The invention is capable of other embodiments and of being practiced and carried out in various ways. The aforementioned variations and modifications fall within the scope of the present invention. It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or apparent in the text and/or drawings. All these different combinations constitute alternative aspects of the invention. The embodiments described in this specification illustrate the best mode known for carrying out the invention, and will enable any person skilled in the art to utilize the invention.

Claims (15)

1. A method of manufacturing a semiconductor substrate, comprising:

forming an active region and an isolation trench on a semiconductor substrate;

depositing insulating oxide in the isolation trench and on the surface of the active region, wherein the insulating oxide in the isolation trench is an isolation structure, and the insulating oxide on the surface of the isolation structure and the surface of the active region is an isolation layer;

removing the isolation layer to enable the surface of the isolation structure to be flush with the surface of the active area;

etching the active region to a preset depth to form an active groove;

and epitaxially growing the semiconductor substrate in the active groove so that the surface of the active region is flush with the surface of the isolation structure.

2. The method of claim 1, wherein the predetermined depth is 0.03-0.3 μm.

3. The method of claim 2, wherein the predetermined depth is 0.15 μm.

4. The method of claim 1, wherein the insulating oxide is silicon oxide or silicon oxynitride.

5. The method of claim 1, wherein the process used to deposit the insulating oxide is at least one of atomic layer deposition, chemical vapor deposition, and spin-on.

6. The method of claim 1, wherein the thickness of the isolation layer is 8-15 nm.

7. The method of claim 1, wherein the process used to remove the isolation layer is chemical mechanical polishing or wet etching.

8. The method of claim 1, wherein the epitaxial growth is performed by molecular beam epitaxy or ultra-high vacuum chemical vapor deposition.

9. The method of claim 1, wherein the semiconductor substrate is monocrystalline silicon, and the monocrystalline silicon is epitaxially grown in the active recess.

10. The method of claim 1, wherein the process employed to etch the active region to the predetermined depth is wet etching or dry etching.

11. The method of claim 1, wherein forming an active region and an isolation trench on the semiconductor substrate comprises:

forming a photoresist mask on the semiconductor substrate;

etching the semiconductor substrate by using the photoresist mask to form the isolation trench and the active region;

and removing the photoresist mask above the active region.

12. The method as recited in claim 1, further comprising:

and depositing an ion implantation barrier layer on the surface of the semiconductor substrate after epitaxial growth.

13. The method of claim 12, wherein the thickness of the ion implantation barrier layer is 8-12 nm.

14. The method of claim 12, wherein the material of the ion implantation barrier layer is silicon dioxide or silicon nitride.

15. A semiconductor device, comprising: a semiconductor substrate and a functional device in the semiconductor substrate, wherein the semiconductor substrate is prepared by the method of any one of claims 1 to 14.