CN113419991A

CN113419991A - Radar anti-interference measure dynamic configuration method based on CPU and FPGA

Info

Publication number: CN113419991A
Application number: CN202110769182.9A
Authority: CN
Inventors: 翟刚毅; 张海龙; 蔡文彬; 张宁
Original assignee: Nanjing University of Aeronautics and Astronautics; 724th Research Institute of CSIC
Current assignee: Nanjing University of Aeronautics and Astronautics; 724th Research Institute of CSIC
Priority date: 2021-07-07
Filing date: 2021-07-07
Publication date: 2021-09-21
Anticipated expiration: 2041-07-07
Also published as: CN113419991B

Abstract

The invention relates to a method for dynamically configuring radar anti-jamming measures based on CPU and FPGA, belonging to the technical field of radar signal processing, and in particular to solving the needs of radar information processing with strong real-time performance, large amount of data and quick response, and can effectively real-time online dynamic Configure and switch anti-jamming waveforms arbitrarily according to the battlefield situation to improve the agility of radar response. First, build CPU and FPGA for heterogeneous platforms, then solidify different countermeasures and map them to onboard registers according to interference strategies; then evaluate and optimize confirmation according to environmental perception; Configure anti-jamming measures to effectively improve the radar's perception ability in complex electromagnetic environments, which is conducive to reducing the probability of target false alarms.

Description

Radar anti-interference measure dynamic configuration method based on CPU and FPGA

Technical Field

The invention belongs to the technical field of radar signal processing.

Background

With the increasing prevalence of modern electronic warfare trends, phased array radars have been unable to meet the requirements of real-time background-based self-configuration radar information processing according to the traditional radar signal processing hardware platform architecture in order to meet the requirements of interference-resistant devices and the increasing number of array elements of phased array radars. In the field of radar information countermeasure processing, effective countermeasure is made according to the situation perception of the battlefield environment, and the importance of the effective countermeasure in the fields of radar countermeasure anti-interference and the like is more and more highlighted. All the requirements urgently need a brand-new hardware architecture platform, and corresponding changes and adjustments can be made according to the radar background information perception situation, so that the hardware resource consumption is reduced, and the aim of improving the target detection probability is finally achieved.

The problem of delay, throughput and the like of a platform which is solved by using a heterogeneous platform processing method of domestic CPU + FPGA is proposed in the document 'design and performance research of a reconfigurable computing system facing domestic CPU' (computer engineering and application, 2018, Vol.54, No.23pp: 36-41). The above article mainly solves the problem of computing resource density of a CPU in performing vector operations, but cannot be used in an online configuration of anti-interference measures. In the document "high-precision scientific computation accelerator research based on FPGA" (computer science and newspaper, 2012, Vol.35, No.1pp:112-122), it is proposed to use the combination of FPGA and CPU to accelerate the computation based on the full-flow four-precision floating-point multiply-accumulate unit ". The traditional heterogeneous platform CPU + FPGA framework method is utilized, calculation of an algorithm can be effectively accelerated, redundancy and transmission pressure are reduced, and dynamic adjustment cannot be made according to radar situation perception to achieve certain anti-interference performance. In addition, a hardware processing framework which cannot effectively meet the requirements of high real-time performance, low power consumption and no extra overhead is rarely reported for the processing of the intermediate frequency data of the phased array radar. The above document is also a general overview of implementing accelerated operations between a CPU and an FPGA.

Disclosure of Invention

The invention provides a dynamic configuration method of radar anti-interference measures based on a CPU and an FPGA (field programmable gate array), aiming at the problems that the implementation complexity of large-scale phased array radar hardware is high, the real-time dynamic reconfiguration cannot be realized, the radar anti-interference flexible configuration cannot be realized, and the like, the method fully utilizes the heterogeneous hardware platform design of the CPU and the FPGA, combines the relevant characteristics of the CPU and the FPGA, automatically switches the required waveform design for anti-interference according to the environment situation of the radar, simultaneously feeds parameter information back to an optical fiber packet header to trigger the FPGA to switch different waveform files according to different scheduling states to perform multi-beam strong real-time flow processing, and fully utilizes the flexible computing function of the CPU and a large number of DSP48E and memory resources in the FPGA.

The program of the multi-beam pulse pressure function module sets different file bit streams in advance according to the parameters of the radar engineering system and stores the different file bit streams into FLASH. The FPGA judges the specific waveform to be reconstructed in real time according to the drive of the optical fiber data stream to perform the multi-beam pulse pressure function, and then switches and selectively loads different bit streams according to the IP core in the FPGA, so that the function of real-time dynamic reconstruction is achieved.

The implementation process of the invention comprises the following steps:

1) adopting a CPU + FPGA heterogeneous hardware platform to carry out software and hardware collaborative development based on OpenCl specification; the FPGA plug-in FLASH memory stores different bit streams; the CPU establishes a kernel handle and performs data communication interaction with the FPGA through a PCIE bus; the FPGA calls different Kernels Kernels through an AXI bus to compile programs so as to realize the multi-beam anti-interference waveform measure curing function;

2) the CPU is used as a main control device and is used for performing resource scheduling and logic judgment task processing; the FPGA is responsible for intensive operation tasks, a static storage area and a dynamic storage area are set, and a corresponding file system is configured;

3) judging whether the packet header needs to be reconstructed by an anti-interference strategy, acquiring data corresponding to different functions of external storage equipment through an internal packet processor, and reconfiguring functional modules with different waveforms, pulse pressures and the like through an internal configuration access port ICAP (independent component analysis platform);

4) and judging whether the reconstruction information is successful according to the message feedback information, if the reconstruction information is successful, finishing the operation, waiting for the corresponding of the next repetition period, and if not, continuously accessing the bus information repeatedly for reconfiguration.

Further, the anti-interference strategy reconstruction in the step 3) is to perform correlation analysis according to the message header information, judge whether there is interference, judge whether to switch the waveform after the interference exists, and switch to A if necessary¹MHz four-phase code signal, otherwise switching to A²And processing the linear frequency modulation signal of MHz. Advancing simultaneouslyJudging whether the radar fine tracking scanning is needed or not in one step, and switching to B if the radar fine tracking scanning is needed¹Tracking the MHz fine tracking waveform, otherwise keeping, further judging whether wideband identification is needed, if so, switching to B²And carrying out broadband identification on the MHz signal, otherwise, keeping the signal until the end.

Further, in step 4), continuous indexing is performed according to the pulse repetition period, and if acceleration is finished, the bus is accessed for reconfiguration.

The invention is described in further detail below with reference to fig. 1.

Drawings

FIG. 1 is a process flow diagram of the present invention.

FIG. 2 is a diagram of the hardware logic connection of the FPGA and the CPU of the present invention.

FIG. 3 is a logic diagram of the dynamic and static memory functional areas of the FPGA of the present invention.

Fig. 4 is an amplitude diagram of 10 beams after constant false alarm detection after a radar anti-interference measure dynamic configuration method based on a CPU and an FPGA is adopted in the embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but the present invention is not limited thereto. The invention provides a dynamic configuration method of radar anti-interference measures based on a CPU and an FPGA, a schematic diagram is shown in figure 1, and the specific process is as follows:

the method comprises the following steps: the method comprises the steps of firstly, building a hardware platform in a heterogeneous mode, fully utilizing a CPU (Central processing Unit) processor suitable for flexible scheduling as a main control, and utilizing an FPGA (field programmable Gate array) suitable for intensive calculation as a co-control module for realizing different multi-beam pulse pressures. The main coprocessors are connected through an X8 bus of PCIE3.0 with large bandwidth to exchange data with each other. And establishing a line rate optical interface of 1.25Gbps for mutual transmission of configuration information.

Step two: the CPU serves as a main control device and performs resource scheduling and logic judgment task processing. The FPGA is mainly responsible for tasks with high intensive operation, a static storage area and a dynamic storage area are set, a corresponding file system is configured, and health management parameters such as the temperature, the core voltage, the pin voltage and the like of the FPGA are transmitted to a CPU (central processing unit) end by an I2C bus to be collected and reported in a unified manner. And carrying out self-defined storage on the pulse compression file by using an FPGA (field programmable gate array) external memory FLASH, dividing the pulse compression file into a radar search waveform, a radar fine tracking waveform and a broadband identification waveform according to an anti-interference strategy, respectively and correspondingly storing the radar search waveform, the radar fine tracking waveform and the broadband identification waveform, and marking a related address.

Step three: judging whether anti-interference strategy reconstruction is needed according to packet header information, if so, acquiring data corresponding to different functions of external storage equipment through an internal packet processor, further reconfiguring functional modules such as different waveform pulse pressures and the like through an internal configuration access port ICAP, judging whether waveform switching is needed after interference, and if so, switching to A¹MHz four-phase code signal, otherwise switching to A²And processing the linear frequency modulation signal of MHz. Further judging whether the radar is required to be precisely scanned, and switching to B if the radar is required to be precisely scanned¹Tracking the MHz fine tracking waveform, otherwise keeping, further judging whether wideband identification is needed, if so, switching to B²And carrying out broadband identification on the MHz signal, otherwise, keeping the signal until the end.

Step four: and continuously indexing according to the pulse repetition period, and accessing the bus to reconfigure if acceleration is finished according to the feedback result of the step three. Otherwise, different pulse compression waveforms are continuously reconstructed.

The feasibility of the process of the invention is further verified by the following specific examples.

Referring specifically to fig. 2, a logic diagram of the hardware connection between the CPU and the FPGA is shown. The CPU and the FPGA carry out high-capacity and high-bandwidth transmission between the CPUs through a high-speed serial PCIE 3.0X 8 bus, and meanwhile, an ROCKETIO bus with the line rate of 1.25Gbps is used for transmitting data configuration and control information and an I2C bus is used for transmitting health management related information. The CPU end is mainly based on the development and configuration of an application layer of OpenCl specification. And necessary software drivers such as PCIE are configured, and a Runtime library is adopted to carry out internal bottom layer space calling.

Fig. 3 is a logic diagram of dynamic and static storage functional areas of an FPGA, in which a BLOCK RAM storage BLOCK inside the FPGA is divided into a static storage area and a dynamic storage area, and corresponding file configuration is performed, so that functional modules with different waveforms and pulse pressures are reconfigured through an internal configuration access port ICAP when it is determined that an interference measure is needed to be reconfigured.

Fig. 4 shows the actual radar intermediate frequency echo playback test result of the specific phased array radar designed by the dynamic reconstruction anti-interference measure configuration method based on the CPU and the FPGA assuming that 10 beams are simultaneously used, and it can be seen from the figure that the radar intermediate frequency echo can be correctly processed on the hardware architecture platform, which also fully verifies the effectiveness and feasibility of the method of the present invention.

Claims

1. based on the radar anti-jamming measure dynamic configuration method of CPU and FPGA, it is characterized in that:

1) The CPU+FPGA heterogeneous hardware platform is used to carry out the software and hardware collaborative development based on the OpenCl specification; the FPGA is attached to the FLASH memory to store different bit streams; the CPU establishes a kernel handle and communicates with the FPGA through the PCIE bus; FPGA uses AXI The bus calls different Kernels to compile the program to realize the curing function of multi-beam anti-interference waveform measures;

2) As the main control device, the CPU is responsible for the processing of resource scheduling and logical judgment tasks; the FPGA is responsible for the tasks with higher intensive computing, setting the static storage area and dynamic storage area and configuring the corresponding file system;

3) judging whether the packet header needs to be reconstructed by the anti-interference strategy, obtaining data corresponding to different functions of the external storage device through the internal packet processor, and then reconfiguring different functional modules through the internal configuration access port ICAP;

4) Determine whether the reconstruction information is successful according to the message feedback information. If the operation is successfully ended, wait for the response of the next repetition cycle, otherwise, continue to repeatedly access the bus information for reconfiguration.

2. the radar anti-jamming measure dynamic configuration method based on CPU and FPGA according to claim 1, is characterized in that: the anti-jamming strategy reconstruction in described step 3) comprises: carry out correlation analysis according to message header information, judge Whether there is interference, judge whether the waveform needs to be switched after there is interference, if necessary, switch to A1MHz four-phase code signal, otherwise switch to A2MHz chirp signal for processing; at the same time, it is further judged whether it is necessary to perform radar fine-following scanning, and if it is necessary to switch Follow the waveform into B1MHz, otherwise keep it, and then further judge whether broadband identification is required, if it is necessary to switch to B2MHz signal for broadband identification, otherwise keep until the end.

3. the radar anti-jamming measure dynamic configuration method based on CPU and FPGA according to claim 2, is characterized in that: in described step 4), carry out continuous indexing according to pulse repetition cycle, if acceleration ends then access bus is reconfigured.