CN113314546A - Array substrate, array substrate testing method and display panel - Google Patents
Array substrate, array substrate testing method and display panel Download PDFInfo
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- 238000000059 patterning Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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Abstract
The embodiment of the application discloses an array substrate, an array substrate testing method and a display panel, wherein the array substrate comprises: the array is arranged on the substrate, the sub-pixels comprise main pixel areas and sub-pixel areas, the main pixel areas are electrically connected with the first transistors, and the sub-pixel areas are electrically connected with the second transistors and the shared transistors; the shared electrode and the data line are arranged on the same layer and extend parallel to the data line; and the lapping electrode is arranged in a different layer with the data line and is positioned on the surface of one side of the data line far away from the substrate, and the lapping electrode is electrically connected with the sharing transistor and the sharing electrode. The array substrate can realize the independent test of the performance of a certain row of sub-pixels or signal lines, detect the defects on the array substrate in advance and avoid the defective products from flowing into the subsequent processing technology, thereby saving resources and cost.
Description
Technical Field
The application relates to the field of display, in particular to an array substrate, an array substrate testing method and a display panel.
Background
Liquid crystal display panels (LCDs) have been widely used in daily life and work. The liquid crystal display panel has developed a 3T pixel circuit (3 thin film transistors) to realize multi-domain display to reduce large viewing angle color shift. The liquid crystal display panel comprises a plurality of sub-pixels arranged in an array, each sub-pixel comprises a main pixel area and a sub-pixel area, the main pixel area is electrically connected with a first transistor, the sub-pixel area is electrically connected with a second transistor and a shared transistor, and the sub-pixel area is electrically connected with a shared electrode (sharebar) through the shared transistor. However, the 3T pixel circuit and the pixel design have the following defects, especially when metal oxide (IGZO) is used as an active layer of a thin film transistor, after the thin film transistor is manufactured, an electrical test needs to be performed on the array substrate, and since each shared electrode (sharebar) is electrically connected in a non-display area, when a test electrical signal test is applied to two ends of a single data line, the test electrical signal flows to all the shared electrodes (sharebar) of the array substrate through the shared electrodes, so that the performance of a certain column of sub-pixels or signal lines cannot be tested independently.
Disclosure of Invention
The embodiment of the application provides an array substrate, an array substrate testing method and a display panel, wherein the array substrate comprises: a substrate; the scanning line is arranged on the substrate; the data line is arranged to intersect with the scanning line; the array is arranged on the substrate, the sub-pixels comprise main pixel areas and sub-pixel areas, the main pixel areas are electrically connected with the first transistors, and the sub-pixel areas are electrically connected with the second transistors and the shared transistors; the shared electrode and the data line are arranged on the same layer and extend parallel to the data line; and the lapping electrode is arranged in a different layer with the data line and is positioned on the surface of one side of the data line far away from the substrate, and the lapping electrode is electrically connected with the sharing transistor and the sharing electrode. The lapping electrode CL is positioned on the data line DL, so the lapping electrode is manufactured later than the first transistor, the second transistor and the shared transistor, the shared transistor is not electrically connected with the shared electrode before the lapping electrode is manufactured, the array substrate test is carried out at the moment, a test electric signal can be prevented from flowing to all the shared electrodes of the array substrate through the shared transistor, and the performance of independently testing a certain column of sub-pixels or signal lines is realized.
The embodiment of the application provides an array substrate, includes:
a substrate;
the scanning line is arranged on the substrate;
the data line is arranged to intersect with the scanning line;
the array is arranged on the substrate, the sub-pixels comprise main pixel areas and sub-pixel areas, the main pixel areas are electrically connected with the first transistors, and the sub-pixel areas are electrically connected with the second transistors and the shared transistors;
the shared electrode and the data line are arranged on the same layer and extend parallel to the data line; and the number of the first and second groups,
and the lapping electrode is arranged in a different layer with the data line and is positioned on the surface of one side of the data line far away from the substrate, and the lapping electrode is electrically connected with the sharing transistor and the sharing electrode.
Optionally, in some embodiments of the present application, an insulating layer is disposed between the shared electrode and the landing electrode, and the landing electrode electrically connects the shared transistor and the shared electrode through a through hole in the insulating layer.
Optionally, in some embodiments of the present application, the main pixel region includes a main pixel electrode, the sub-pixel region includes a sub-pixel electrode, and the main pixel electrode, the sub-pixel electrode, and the shared electrode are disposed in the same layer.
Optionally, in some embodiments of the present application, a drain of the first transistor is electrically connected to the main pixel electrode, a source of the second transistor is connected to a source of the second transistor, a drain of the second transistor is electrically connected to the sub-pixel electrode, a drain of the second transistor is connected to a drain of the sharing transistor, and a source of the sharing transistor is electrically connected to the sharing electrode through the overlapping electrode.
Optionally, in some embodiments of the present application, the array substrate includes a non-display area and a display area, and the common electrodes between adjacent sub-pixels extend from the display area to the non-display area and are electrically connected to each other in the non-display area.
Optionally, in some embodiments of the present application, a common electrode disposed in the same layer as the scan line is further included.
Optionally, in some embodiments of the present application, the main pixel electrode and the sub pixel electrode are in one of a two-domain structure, a four-domain structure, and an eight-domain structure.
The embodiment of the application also provides an array substrate testing method, which comprises the following steps:
s100: providing an array substrate, wherein the array substrate comprises a display area and a non-display area, the display area comprises data lines and scanning lines which are arranged in a crossed mode, a plurality of sub-pixels arranged in an array mode, and a shared electrode extending parallel to the data lines, each sub-pixel comprises a main pixel area and a sub-pixel area, the main pixel area is electrically connected with a first transistor, the sub-pixel area is electrically connected with a second transistor and a shared transistor, the array substrate is not provided with a pixel electrode, the shared transistor is arranged in an insulated mode with the shared electrode, the non-display area comprises a test transmitting terminal and a test receiving terminal, one end of each data line is electrically connected with the test transmitting terminal, and the other end of each data line is electrically connected with the test receiving terminal;
s200: providing a test device comprising a first terminal for issuing a test signal and a second terminal for receiving the test signal;
s300: electrically connecting the test equipment with the array substrate, electrically connecting the first terminal of the test equipment with the test transmitting terminal of the array substrate, and electrically connecting the second terminal of the test equipment with the test receiving terminal of the array substrate;
s400: and electrifying the test equipment, wherein the first terminal of the test equipment sends out an electric signal, and the second terminal of the test equipment receives the electric signal.
Optionally, in some embodiments of the present application, the method further includes the following steps:
s500: and forming a lapping electrode and the pixel electrode, wherein the pixel electrode and the lapping electrode are arranged on the same layer, the pixel electrode comprises a main pixel electrode positioned in the main pixel area and a sub-pixel electrode positioned in the sub-pixel area, an insulating layer is arranged between the sharing electrode and the lapping electrode, and the lapping electrode is electrically connected with the sharing transistor and the sharing electrode through a through hole in the insulating layer.
Correspondingly, the embodiment of the application also provides a display panel, which comprises the array substrate.
The application embodiment provides an array substrate, an array substrate testing method and a display panel. The lapping electrode CL is positioned on the data line DL, so the lapping electrode is manufactured later than the first transistor, the second transistor and the shared transistor, the shared transistor is not electrically connected with the shared electrode before the lapping electrode is manufactured, the array substrate test is carried out at the moment, a test electric signal can be prevented from flowing to all the shared electrodes of the array substrate through the shared transistor, and the performance of independently testing a certain column of sub-pixels or signal lines is realized. Meanwhile, the array substrate of the embodiment of the application is not added with an additional manufacturing process, the manufacturing method is simple, the performance of a certain column of sub-pixels or signal lines can be independently tested, the defects on the array substrate can be detected in advance, the defective products are prevented from flowing into the subsequent manufacturing process, and therefore resources and cost are saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a first schematic plan view of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a second schematic plan view of an array substrate according to an embodiment of the present application;
fig. 3 is a third schematic plan view of an array substrate according to an embodiment of the present application;
fig. 4 is a fourth schematic plan view of an array substrate according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a test apparatus provided in an embodiment of the present application;
fig. 6 is a schematic step diagram of a testing method for an array substrate according to an embodiment of the present application;
fig. 7 is a schematic plan view of a fifth embodiment of an array substrate.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides an array substrate, an array substrate testing method and a display panel. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The first embodiment,
Referring to fig. 1 and fig. 2, fig. 1 is a schematic plan view of a first planar structure of an array substrate (not illustrating a landing electrode) provided in an embodiment of the present application, and fig. 2 is a schematic plan view of a second planar structure of the array substrate provided in the embodiment of the present application.
Referring to fig. 2, an embodiment of the present invention provides an array substrate 10, including: a substrate (not shown); the scanning line SL is arranged on the substrate; the data lines DL are arranged in a crossing way with the scanning lines SL; a plurality of sub-pixels arranged on the substrate in an array, wherein each sub-pixel comprises a main pixel region P1 and a sub-pixel region P2, the main pixel region P1 is electrically connected with a first transistor T1, and the sub-pixel region P2 is electrically connected with a second transistor T2 and a shared transistor T3; a shared electrode 100(sharebar), the shared electrode 100 being disposed on the same layer as the data line DL and extending parallel to the data line DL; and a bonding electrode CL disposed in a different layer from the data line DL and located on a surface of the data line DL away from the substrate, the bonding electrode CL electrically connecting the common transistor T3 and the common electrode 100.
Specifically, the common electrode 100 and the data line DL are disposed on the same layer, the common electrode 100 and the data line DL are made of the same material, and the common electrode 100 and the data line DL are formed by etching and patterning through the same process in the manufacturing process of the array substrate.
Specifically, the array substrate 10 includes: the array substrate 10 further includes an active layer (not shown), a substrate (not shown), a scan line SL, a data line DL, a plurality of sub-pixels, a common electrode 100, and a landing electrode CL. The scanning lines SL and the data lines DL are arranged on the substrate in different layers, and the scanning lines SL and the data lines DL are intersected to define a plurality of sub-pixels. Each sub-pixel includes a main pixel region P1 and a sub-pixel region P2, the main pixel region P1 is electrically connected to the first transistor T1, the sub-pixel region P2 is electrically connected to the second transistor T2 and the shared transistor T3, and more specifically, the main pixel electrode P11 of the main pixel region P1 is electrically connected to the first transistor T1, and the sub-pixel electrode P12 of the sub-pixel region P2 is electrically connected to the second transistor T2 and the shared transistor T3.
Specifically, the overlap electrode CL and the data line DL are arranged in different layers and located on the surface of the data line DL away from the base, which means that the overlap electrode CL is arranged above the data line DL, and in the manufacturing process of the array substrate, the overlap electrode CL is manufactured after the data line DL is manufactured on the base.
Specifically, the strap electrode CL electrically connects the sharing transistor T3 and the sharing electrode 100, which means that the sharing electrode 100 is electrically connected to the sharing transistor T3 through the strap electrode CL.
In some embodiments, an insulating layer is disposed between the common electrode 100 and the landing electrode CL, and the landing electrode CL electrically connects the common transistor T3 and the common electrode 100 through a via hole in the insulating layer.
Specifically, an insulating layer is disposed between the common electrode 100 and the overlap electrode CL, so as to prevent the common electrode 100 from being directly short-circuited with other electrodes or wires. The insulating layer may be an inorganic material, such as silicon nitride or silicon oxide, and the insulating layer may be an organic material Planarization Layer (PLN), a color resistance layer (RGB color resistance), or the like, which is not limited herein. In the manufacturing process of the array substrate, the data line DL is firstly manufactured, then the insulating layer is manufactured, and then the landing electrode CL is manufactured. As shown in fig. 2, the via holes in the insulating layer include a first via hole 201 and a second via hole 202, the landing electrode CL is connected to the shared electrode 100 through the first via hole 201, and the landing electrode CL is connected to the shared transistor T3 through the second via hole 202.
In some embodiments, the main pixel region P1 includes a main pixel electrode P11, the sub pixel region P2 includes a sub pixel electrode P12, and the main pixel electrode P11, the sub pixel electrode P12 and the common electrode 100 are disposed at the same layer.
Specifically, the main pixel electrode P11, the sub pixel electrode P12 and the shared electrode 100 are arranged in the same layer, the main pixel electrode P11, the sub pixel electrode P12 and the shared electrode 100 are made of the same material, and in the manufacturing process of the array substrate, the main pixel electrode P11, the sub pixel electrode P12 and the shared electrode 100 are formed by etching and patterning through the same process. The material of the main pixel electrode P11, the sub pixel electrode P12, and the common electrode 100 may be ITO, but is not limited thereto.
In some embodiments, the drain 12 of the first transistor T1 is electrically connected to the main pixel electrode P11, the source 11 of the first transistor T1 is connected to the source 21 of the second transistor T2, the drain 22 of the second transistor T2 is electrically connected to the sub pixel electrode P12, the drain 22 of the second transistor T2 is connected to the drain 32 of the sharing transistor T3, and the source 31 of the sharing transistor T3 is electrically connected to the shared electrode 100 through the overlap electrode CL.
Specifically, the landing electrode CL is connected to the common electrode 100 through the first via 201, and the landing electrode CL is connected to the source electrode 31 of the common transistor T3 through the second via 202.
In some embodiments, the array substrate 10 includes a non-display area and a display area AA, and the common electrode 100 between adjacent sub-pixels extends from the display area AA to the non-display area and is electrically connected to each other in the non-display area.
Specifically, the non-display area includes a first frame portion BB1, the common electrode 100 between adjacent sub-pixels extends from the display area AA to the first frame portion BB1 of the non-display area, and is electrically connected to each other at the first frame portion BB 1.
In some embodiments, referring to fig. 3, the array substrate 10 further includes a common electrode Com disposed on the same layer as the scan line SL. Fig. 3 is a schematic plan view of a third planar structure of the array substrate according to the embodiment of the present disclosure, and the array substrate 10 further includes a common electrode Com disposed in the same layer as the scan line SL.
Specifically, the common electrode Com and the pixel electrode form a storage capacitor.
Specifically, in some embodiments, in the array substrate 10, the array substrate 10 may include a scan line SL, a gate insulating layer, an active layer, a data line DL, an insulating layer, and a pixel electrode. The array substrate may also be a COA array substrate (color filter array), a BOA array substrate (bmarray), etc., and the array substrate 10 may include scan lines SL, a gate insulating layer, an active layer, data lines DL, a color resist layer, and pixel electrodes, for example.
The first transistor T1, the second transistor T2, and the shared transistor T3 may be top gate thin film transistors or bottom gate thin film transistors, which is not limited herein.
In some embodiments, the main pixel electrode P11 and the sub pixel electrode P12 in the array substrate 10 are in one of a two-domain structure, a four-domain structure and an eight-domain structure. For example, the main pixel electrode P11 and the sub pixel electrode P12 are both four-domain structures, and the main pixel electrode P11 and the sub pixel electrode P12 may include a main stem and multi-domain branches extending from the main stem. The pixel electrodes of the two-domain structure, the four-domain structure and the eight-domain structure are not described herein again.
In this embodiment, the strap electrode CL is formed later than the first transistor T1, the second transistor T2, and the sharing transistor T3, the strap electrode CL is located on the data line DL, and the sharing transistor T3 is not electrically connected to the sharing electrode 100 before the strap electrode CL is formed, so that the array substrate test is performed, and the test electrical signal can be prevented from flowing to all the sharing electrodes 100 on the array substrate through the sharing transistor T3, thereby realizing the performance of individually testing a certain column of sub-pixels or signal lines. The defects on the array substrate can be detected in advance, and the defective products are prevented from flowing into the subsequent processing technology, so that the resources and the cost are saved.
Example II,
Referring to fig. 4 to 7, an embodiment of the present application provides a method for testing an array substrate, which includes the following steps S100, S200, S300, and S400. Fig. 6 illustrates steps of an array substrate testing method.
S100: an array substrate is provided, the array substrate includes a display area AA and a non-display area, the display area AA includes data lines DL and scan lines SL arranged in a crossing manner, a plurality of sub-pixels arranged in an array, and a shared electrode 100 extending parallel to the data lines DL, each sub-pixel includes a main pixel area P1 and a sub-pixel area P2, the main pixel area P1 is electrically connected to a first transistor T1, the sub-pixel area P2 is electrically connected to a second transistor T2 and a shared transistor T3, wherein the array substrate is not provided with a pixel electrode, the shared transistor T3 is insulated from the shared electrode 100, the non-display area includes a test transmitting terminal 301 and a test receiving terminal 302, one end of the data lines DL is electrically connected to the test transmitting terminal 301, and the other end of the data lines DL is electrically connected to the test receiving terminal 302.
Specifically, referring to fig. 4, the array substrate is not provided with a pixel electrode, that is, the main pixel electrode P11 of the main pixel region P1, the sub pixel electrode P12 of the sub pixel region P2, and the connection electrode CL are not provided, so that the sharing transistor T3 is insulated from the sharing electrode 100 and is not electrically connected. The non-display area includes a first frame portion BB1 and a second frame portion BB2, the test transmitter terminal 301 is located at the first frame portion BB1, and the test receiver terminal 302 is located at the second frame portion BB 2.
S200: a test device 500 is provided, the test device 500 comprising a first terminal 501 for issuing a test signal and a second terminal 502 for receiving the test signal.
Specifically, referring to FIG. 5, a test apparatus 500 is illustrated.
S300: the test device 500 is electrically connected to the array substrate, the first terminal 501 of the test device is electrically connected to the test transmission terminal 301 of the array substrate, and the second terminal 502 of the test device 500 is electrically connected to the test reception terminal 302 of the array substrate.
S400: a test is performed by energizing the test device 500, the first terminal 501 of the test device 500 emitting an electrical signal, and the second terminal 502 of the test device 500 receiving the electrical signal.
Referring to fig. 6, the method for testing an array substrate further includes the following step S500.
S500: and forming a lap electrode CL and a pixel electrode, wherein the pixel electrode and the lap electrode CL are arranged at the same layer, the pixel electrode comprises a main pixel electrode P11 positioned in the main pixel area P1 and a sub pixel electrode P12 positioned in the sub pixel area P2, an insulating layer is arranged between the shared electrode 100 and the lap electrode CL, and the lap electrode CL electrically connects the shared transistor T3 and the shared electrode 100 through a through hole in the insulating layer.
Specifically, referring to fig. 7, the landing electrode CL is connected to the common electrode 100 through the first via 201, and the landing electrode CL is connected to the source 31 of the common transistor T3 through the second via 202. An insulating layer is disposed between the common electrode 100 and the landing electrode CL to prevent the common electrode 100 from being directly short-circuited with other electrodes or wires. The insulating layer may be an inorganic material such as silicon nitride, silicon oxide, or the like, and the insulating layer may be an organic material Planarization Layer (PLN), a color resist layer (RGB color resist), or the like, which is not limited herein.
The arrangement of other electrodes or traces such as the bonding electrode CL is the same as that of the first embodiment, and is not described herein again.
In this embodiment, the landing electrode CL is located on the data line DL, the landing electrode CL is formed later than the first transistor T1, the second transistor T2 and the sharing transistor T3, and before the landing electrode CL is formed, the sharing transistor T3 is not electrically connected to the sharing electrode 100, at this time, the array substrate test is performed, so that the test electrical signal can be prevented from flowing to all the sharing electrodes 100 on the array substrate through the sharing transistor T3, and the performance of individually testing a certain column of sub-pixels or signal lines can be realized. Meanwhile, the array substrate of the embodiment of the application has a simple structure, is not added with an additional manufacturing process, is simple in manufacturing method, can realize independent testing of the performance of a certain column of sub-pixels or signal lines, can detect defects on the array substrate in advance, and avoids defective products from flowing into a subsequent manufacturing process, so that resources and cost are saved.
Example III,
The embodiment of the application also provides a display panel, which comprises the array substrate. The display panel further comprises a counter substrate arranged opposite to any one of the array substrates, and a liquid crystal layer clamped between the counter substrate and the array substrate.
The array substrate, the array substrate testing method and the display panel provided by the embodiment of the application are described in detail, a specific example is applied in the description to explain the principle and the implementation of the application, and the description of the embodiment is only used to help understand the method and the core idea of the application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
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