CN1132885A - Parameterized multi-level image display device - Google Patents

Abstract

A parameterized multi-level image display device comprises an address generator, a vertical position detector, a register, a horizontal position counter and an effect processor. The parameterized image data is processed by the devices in a way of image grid division, and then the color codes are sent to a digital/analog converter for conversion and output. The processing capability of the display device for images can be improved and the performance requirements for the central processing unit can be reduced.

Description

Parameterized multi-level image display device

The invention relates to a display system, in particular to a parameterized multi-level image display device.

Multi-level image display technology has been widely used in display systems such as video game consoles, and among them Nintendo and Sega are the most popular. The display system after multi-level image processing can produce various visual effects, which can make the game machine more entertaining and provide consumers with more leisure ways. However, although the display systems used today have multi-layer effects, they have restrictions on the size, color number, layers, and even the number of images in the same screen, so that the visual effects of the display system are still limited and cannot provide the best choose.

Of course, using software programs and the processing of the computer central processing unit can improve the limitations of the above-mentioned image processing technology, but it needs to rely on the time and cost of software program design, and it needs to cooperate with better execution computing capabilities The central processing unit of the computer has made the practice of improving visual effects quite expensive, which has discouraged the general industry and the consumer public.

However, if the visual effect is directly improved by using the hardware structure to make the image display more lively, the size of the screen display is different and the graphic data is complicated, which will inevitably cause a lot of waste of hardware resources, and the design of the image display device is complicated and does not meet the actual needs.

Therefore, the main purpose of the present invention is to provide a parameterized multi-level image display device, which uses parameter data to assist graphic data, so as to improve the image processing capability of the display device and make the image more variable.

Another object of the present invention is to provide a parameterized multi-level image display device, which cooperates with an appropriate hardware structure and reduces performance requirements for a central processing unit.

Another object of the present invention is to provide a parameterized multi-level image display device, which establishes a parameter data structure in a grid division manner, reduces the complexity of hardware requirements, and reduces the waste of hardware resources.

The present invention is a parameterized multi-level image display device, which is applicable to a display system with a graphic memory, a digital/analog converter connected with the graphic memory and a bus device, and the display system is to The image data is stored in the graphic memory in the form of parameter data, and these parameter data are processed through the image display device according to the instructions of the display system to output color codes to the digital/analog converter; Image display devices include:

An address generator, connected to the bus, generates an address signal on the bus to address the graphics memory, so that the parameter data can be read;

A vertical position detector, connected between the bus and the address generator, detects the vertical position of the image data, and an address signal for controlling parameter data is output from the address generator to the bus;

a register, connected to the bus, used to read and store the parameter data addressed by the address generator;

A horizontal position counter connected to the bus for detecting the horizontal position of the image data; and

An effect processor device, connected between the register and the digital/analog converter, and controlled by the horizontal position counter, is used to carry out hierarchical processing of the image data through its complementary parameter data, and in the The above digital/analog converter outputs multi-layer images.

In the present invention, after the parameterized image data is processed by the above-mentioned devices in the manner of grid division, the color code is sent to the digital/analog converter for conversion and output. The above device can improve the image processing capability of the display device and reduce the performance requirements for the central processing unit.

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, a preferred embodiment is specifically cited in this paper, and is described in detail as follows in conjunction with the accompanying drawings:

Brief description of the drawings:

Fig. 1 is a block diagram of a preferred embodiment of the present invention.

FIG. 2 is a circuit diagram designed according to the block diagram of FIG. 1 .

Fig. 3 is a schematic diagram of a graphic address structure.

Fig. 4 is a schematic diagram of screen parameter definition and detection according to a preferred embodiment of the present invention.

FIG. 5 is a signal timing diagram in the circuit of FIG. 2 .

FIG. 6A to FIG. 6C are structural diagrams of addressing signals formed on the bus according to the circuit of FIG. 2 .

Fig. 7 is a schematic diagram of the data structure of the graphics memory in this preferred embodiment.

Fig. 8 is a schematic diagram of the data structure of the graphics memory in this preferred embodiment.

FIG. 9A and FIG. 9B are timing diagrams of various signals in this preferred embodiment.

FIG. 10 is a circuit diagram of the effect processor of the preferred embodiment of FIG. 2 .

First, please refer to FIG. 1, which is a block diagram of a preferred embodiment of the present invention. According to the parametric multi-level image display device of the present invention, the graphic data is stored in the graphic memory 60 in the form of parameters. When the data start signal DB is sent to the address generator 20, the graphic data output action is started. The address generator 20 then generates an address signal for the graphics data, addresses the graphics memory 60 via the bus 50, and reads the parameter data therefrom. After vertical position detector 12 interprets the vertical position parameter contained in this parameter data, when necessary, request address generator 20 sends out parameter address signal in addition, addresses graphics memory 60 through bus 50, makes color code and other parameters The data is sent to the register 40 via the bus 50 for storage. At the same time, the horizontal position counter 14 also judges the horizontal position of the scanning line according to its counted horizontal value, so that the effect processor 30 can timely read the color code and other data stored in the register 40 for effect processing, such as color mixing, layering and transparency Wait for action. Then, the color code signal is sent to the screen for output via a digital/analog converter (RAM DAC) 70.

Due to the wide display range of the screen, if each pixel (Pixel) of the corresponding parameters is to be recorded in detail, it will inevitably cause a burden on the memory capacity, which is not suitable for economical benefits. Therefore, the parametric structure according to the invention has the properties of image segmentation. It divides the screen display image into small blocks of the same size, called grids, for example, into small grids of 8 pixels×8 pixels. If the color code in each grid is represented by 4 bits, then the color code of each grid occupies the same memory space, that is, 16 words (Words). Wherein, each pixel is arranged in order to form a color code array, as listed in Table 1A, which is the corresponding position of the color code value DOT of each pixel in the graphics memory:

Table 1A Color code array

address VRAM data bus [15:0] +0 DOT11[4:0] DOT12 [4:0] DOT13 [4:0] DOT14 [4:0] +2 DOT15[4:0] DOT16 [4:0] DOT17 [4:0] DOT18 [4:0] +4 DOT21[4:0] DOT22 [4:0] DOT23 [4:0] DOT24 [4:0] … ... ... ... ... … ... ... ... ... +28 DOT81[4:0] DOT82 [4:0] DOT83 [4:0] DOT84 [4:0] +30 DOT85[4:0] DOT86[4:0] DOT87 [4:0] DOT88 [4:0]

Through the arrangement of the cells, the corresponding parameters can be greatly simplified. Therefore, the parameters corresponding to each dynamic image object, that is, the parameters of the image to be displayed on the screen, only need to be formed in the structure listed in Table 1B.

Table 1B dynamic image object (DIO) parameter array

address VRAM data bus VDATA[15:0] +0 SCV[2:0] NVF[3:0] VPS[8:0] +2 FBK[2:0] -- HMR VMR SCC CCA -- MSC[2:0] NHF[2:0] +4 SCH[4:0] LY[1:0] HPS[8:0] +6 TPR[15:0]

Wherein, the NVF and NHF parameters respectively represent the vertical size (Number of Vertical Fonts) and the horizontal size (Number of Horizontal Fonts) of the image object, and are used to control the size of each image. Then the image corresponding to such a group of parameter structures has the number of pixels of (NVF+1)×2 ^NHF . That is, the image defined by this parameter structure needs to be composed of (NVF+1)×2 ^NHF pixels as shown in Table 1A. As a result, it is necessary to use (NVF+1)×2 ^NHF parameters to address the grid array part in the graphics memory. These parameters used for addressing form an array, which is the index array shown in Table 1C.

     Table 1C Index array

address VRAM data bus VDATA[15:0] +0 CPT[3:0] HMR VMR FNT[9:0] +2 CPT[3:0] HMR VMR FNT[9:0] +4 CPT[3:0] HMR VMR FNT[9:0] … ... ... +2n CPT[3:0] HMR VMR FNT[9:0]

The index array size shown in Table 1C is exactly (NVF+1)×2 ^NHF words. Each word contains a pointer FNT pointing to the used color code array and 4-bit color code value, making each pixel color code 8 bits. The sequence of each element in the index array is determined according to the pixel sequence in the image. The address of the pointer array is defined by the parameter TPR×2 in the image parameter array. Regarding the various parameters of the image, that is, the parameters provided in Table 1A to Table 1C, the description in Table 2 can be compared.

Therefore, according to the above parameter structure design, the circuit diagram according to the preferred embodiment of the present invention is shown in FIG. 2 . In this circuit device, in order to control the more complex timing relationship, a state timing controller 10 is provided, which uses its own logic operation to generate various control signals driven by the input clock pulse signal, so as to form an orderly image processing flow.

In FIG. 1 , the address generator 20 as the graphics and parameter address sending unit is then replaced by four units of the graphics address generator 22 , FIFO register 24 , parameter address generator 26 and horizontal length counter 28 . Graphics address generator 22 accepts the data start signal DB control, and is driven by the clock pulse signal sclk from state timing controller 10, generates graphics address on bus 50, in order to address graphics memory 60, selects a group as shown in the table 1B shows the parameter array. After the vertical position detector 12 reads the relevant parameters of this figure, it judges its vertical position by its vertical parameters, to confirm whether this data is displayed on the next screen scan line. If so, then the first-in-first-out register 24 will send the parameter data stored therein to the parameter address generator 26, after the parameter data is processed, send the addressing signal of the index array to the bus 50, to obtain the data stored in the graphics memory 60. The value in the desired color code array.

Table 2 Control parameter table of image object

mark number of digits illustrate Screen positioning class: VPS [8:0] 9 Control the upper left corner of the image object, displayed on the screen line position, that is, the screen vertical position of the scan line of the screen (Vertical Position) HPS [8:0] 9 Control the upper left corner of the image object, which is displayed at the scanned image position, that is, the horizontal position of the screen (HorizontalPosition) LY[1:0] 2 Control the weight of image objects (Layer Level). Data structure schema class: NVF [3:0] 4 Control the vertical size unit of the image object (Number ofvertical Fonts), the actual value is shown in the scale table NHF[2:0] 3 Control the horizontal size unit of the image object (Number ofHorizontal Fonts), the actual value is 2 ^NHF

Table 2 Control parameter table of image object (continued)

mark number of digits illustrate CPT [3:0] 4 Palette DOTxx [3:0] 4 Color data Indicator class: FBK [2:0] 3 The area for storing pixel data, each area is 32K bytes. FNT [9:0] 10 Pointer to the cell data (Font Pointer). TPR [15:0] 16 Pointer to the array of cell data pointers (Table Pointer) Special effects class: VMR 1 vertical reflection switch HMR 1 Horizontal inversion switch

Table 2 Control parameter table of image object (continued)

mark number of digits illustrate CCA 1 Translucent Action Switch (Color Mixing Action) SCC 1 Monochrome Saturation Action Switch MSC[2:0] 3 Mosaic effect switch SCV[2:0] 3 Controls the ratio of image objects to shrink in the vertical direction, the actual value is 22-SCV SCH [4:0] 5 Control the scaling value of the image object in the horizontal direction. The actual value is shown in the scaling table.

The effect processor 30 of FIG. 1 can be replaced by a detector 32, an SRAM 34 and a color code register 36 for special effect processing. After the detector 32 obtains parameters, indicators and color codes from the register 42, it performs various effect processing, and then stores the processing results in the static random access memory 34. The capacity of SRAM 34 can store the parameter data of a screen scan line, and the color code to be output and its additional layer parameters are taken out by color code register 36 and sent back to the detector 32, and continuously input The new color codes are compared with the additional parameter values to update the graphics data stored in the SRAM 34. The above process occurs when the screen control signal is in the horizontal synchronous period. When the horizontal synchronous period is suspended, the data stored in the static random access memory is sequentially output to the digital/analog converter 70 for conversion, and then from the screen display.

In the display device designed according to the preferred embodiment above, several important parameter signals are described as follows:

First, the signal DB from the outside of the system is the only signal sent by the central processing unit (not shown in the drawings) to control the display device. After DB is sent from the central processing unit, it is stored in the graphics register 18 . When the graphics address generator 22 enters the screen scanning period, it fetches the DB signal in the graphics register 18 to generate continuous jumping addresses. This address is composed of DB signal and a 4-bit count value, and its structure is shown in Figure 3.

Then the vertical position detector 12 utilizes this address and the first word of the parameter array read from the graphics memory 60 to refer to Table 1B, ie, SCV, NVF and VPS values for detection. For the detection method, please refer to FIG. 4 for an example of an image on the screen. Among them, HPC and VPC are the horizontal and vertical positions of TV scan lines; HPS and VPS are the positions of the upper left corner of the image on the screen. Then after calculation: VDIFF=(VPC+1)-VPS and

edif=VDIFF×2 ² -SCV If 0≤edif<NVF×8 holds true, it means that this image will be displayed in the next scanning line. Then the vertical position detector 12 will generate a push signal to the FIFO register 24, and send the output value of the graphics address generator 22 and the edif value into it. VDIFF is the distance from the top of the image to the scanning line, and the operation of edif is to make the image appear enlarged or reduced, because if the correct distance VDIFF is enlarged, the read image will be closer to its bottom, so the image will be reduced. vice versa.

Simultaneously when the scanning period begins, the horizontal position counter 44 is set to "0", and superimposition is produced with the sending of the output color code clock pulse (dot-clk), and the SRAM 34 is addressed by the output signal 1add-er , to sequentially output the color code signal CC. FIG. 5 is a diagram showing the timing relationship among the various signals in the above description.

When the scan cycle ends and the horizontal sync cycle is entered, the state timing controller 10 sends a pop signal to the FIFO register 24, so that the parameter address generator 26 can read the parameter data stored in the FIFO register 24, and then generate an index Array address and color code array address.

Regarding the address signal VADDR generated by the graphic address generator 22 and the parameter address generator 26, its structure in this preferred embodiment is as shown in FIG. 6A to FIG. 6C, and both have a word length of 16 bits. 6A is the address signal sent by the graphic address generator, using the 6-bit signal DB as the header, followed by the 9-bit count value, and the last two bits of the 4-bit mantissa array. The index address signal generated by the parameter address generator 26 is considered to have different sizes for different images, and the number of corresponding index arrays is not fixed, so that the index address structure as shown in FIG. 6B has an indefinite number of sample bits ( Font-CNT).

The above-mentioned various VADDR signals circulating on the bus 50 are transmitted to the graphics memory 60, that is, addressed. Please refer to Figure 7 and Figure 8 for the addressing mode in the graphics memory. In Fig. 7, for example, the dynamic image object (DIO) in the memory area from 01260h to 01266h has been selected by the address signal sent by figure address generator 22, namely by address 01260h to 01266h4 groups of 16-bit parameter array DIO[76 ]. Then, if you compare the parameter structure in Table 1B, you can know that TPR is 1000h, NHF is 2h, and NVF is 4h. Then, when the Font-cnt valid bit is only 2, that is, the horizontal width of the image is only 4 grids, whenever the horizontal length counter 28 counts to 3, its next counting action will start from zero and send out an overflow simultaneously. The signal over is sent to the state timing controller 10 to make it send a pop signal to start another image processing.

And among Fig. 7, the value of pointing to the index (Table Pointer) TPR of grid data index array is 1000h, so according to the addressing mode of Fig. 6B, the index address that it points to in the graphics memory is 04000h. Furthermore, please compare the address value contained in the index array of the first group, please compare Fig. 8 and Table 1A, it has the relationship that FNT is 30fh, so its corresponding color code array is row 8, so that the calculated The address is the last two words of the color code array.

After various address generation and data reading operations, that is, the work mainly controlled by the slightly complicated timing relationship between the various signals in Figure 9A and Figure 9B, the color code signal still needs to be processed by transparency detection, level comparison and color mixing. to send out. These effect processing is performed in the effect processor 30 . Please refer to Figure 10 for the structure of the effect processor. Wherein, the input signal [LY1D, CC1D] is the level code and 8-bit color code of the same address stored in the color code register 36 . The AND gate 101 is used as a color mixing switch, that is, when the color mixing enable signal CCA is activated, CCID can pass through, and the color code is input, and the color mixing is completed by the adder 102; The color code value is not changed. In addition, in order to distinguish the transparent color code, the zero-value color code is defined as the transparent color code. Therefore, the OR gate 104 can judge the transparent color code and make the output signal 1rw "1", that is, control the static random access memory 34 It is in non-writing state. And when the input is a non-zero color code, that is, a non-transparent color code, the levels must be compared. Because in this preferred embodiment, the level code is 2 bits, 4 levels, and the level code input in the comparator 103 must be absolutely greater than the level code in the color code register 36 to write into the color code register 36, the old level code instead. Therefore, only images with larger layer codes can be displayed, and images with the same layer code are determined by the order of the parameter array. Therefore, according to the design of this preferred embodiment, if the capacity of the FIFO register 24 is 32, the device can process 32 levels of images.

After the color code is through the above-mentioned processing steps, it is written into the static random access memory 34 through the control of the horizontal position counter 44, and then sent to the digital/analog converter 70 in the scanning cycle for conversion. output.

Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention, any skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, therefore The scope of protection of the present invention should be defined by the appended claims.

Claims (7)

1. A parameterized multi-level image display device, suitable for use in a display system with a graphics memory, a digital/analog converter connected to the graphics memory and a bus device; The data is stored in the graphic memory in the form of parameter data, and these parameter data are processed according to the instructions of the display system through the image display device to output color codes to the digital/analog converter; the image Display units include: An address generator, connected to the bus, generates an address signal on the bus to address the graphics memory, so that the parameter data can be read; A vertical position detector, connected between the bus and the address generator, detects the vertical position of the image data, and an address signal for controlling parameter data is output from the address generator to the bus; a register, connected to the bus, used to read and store the parameter data addressed by the address generator; A horizontal position counter connected to the bus for detecting the horizontal position of the image data; and An effect processor device, connected between the register and the digital/analog converter, and controlled by the horizontal position counter, is used to carry out hierarchical processing of the image data through its complementary parameter data, and in the The above digital/analog converter outputs multi-layer images. 2. The device according to claim 1, wherein said address generator comprises: A graphics address generator, connected to the bus, generates a first address signal to address the graphics memory; A FIFO register, connected to the bus and the vertical position detector, is used to store the parameter data addressed by the first address; the FIFO register is controlled by the vertical position detector to timely output said parameter data; and A parameter address generator, connected with the FIFO register and the bus, accepts the parameter data output by the FIFO register to generate a second address signal on the bus. 3. The apparatus of claim 2, wherein said first address signal is used to address a parameter array in said graphics memory, and said parameter array is provided for said vertical position detector to detect The vertical position is used to control the sending of the second address signal to address the color code array in the graphics memory. 4. The device according to claim 1, wherein said effect processor device comprises: a detector device, connected to said registers, for performing transparency, color mixing and gradation detection and processing; a memory device, connected between the detector device and the digital/analog converter, controlled by the horizontal position counter, for storing the color code and parameter data; and A color code register device, connected between the memory device and the detector device, is used to supply the color code and parameter data stored in the same image position in the memory device to the detector device for detection with processing. 5. The apparatus of claim 4, wherein said detector means comprises: An AND gate has two input terminals and an output terminal, and its input terminals are connected to the color code register and the register respectively, so as to obtain different color codes at the same image position for logical operation; An adder has two input terminals and an output terminal, and its input terminals are respectively connected to the register and the color code register for comparing the levels of the same image position; A comparator has two input terminals and an output terminal, and its input terminals are respectively connected to the register and the color code register for comparing the levels of the same image position; An OR gate has an input terminal and an output terminal, the input terminal of which is connected to the register for judging the transparent color code; and A logic gate combination, connected to the output terminals of the adder, the comparator and the OR gate, is used to generate an output to control whether the memory device is written into the color code and parameter data. 6. A device as claimed in claim 5, wherein said memory means is a static random access memory having a capacity just sufficient to store the amount of data for one screen scan line. 7. The device according to any one of claims 1, 2, 3, 4, 5 or 6, further comprising a state timing controller for generating timing signals for each device in the display device according to a predetermined Timing works.

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