CN113284802B - A high electron mobility transistor and a method for manufacturing the same - Google Patents
A high electron mobility transistor and a method for manufacturing the same Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title claims description 8
- 238000005530 etching Methods 0.000 claims abstract description 127
- 230000004888 barrier function Effects 0.000 claims abstract description 107
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 57
- 230000005641 tunneling Effects 0.000 claims abstract description 37
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims abstract description 34
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 19
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 18
- KDYFGRWQOYBRFD-UHFFFAOYSA-N succinic acid Chemical compound OC(=O)CCC(O)=O KDYFGRWQOYBRFD-UHFFFAOYSA-N 0.000 claims description 13
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- 239000001384 succinic acid Substances 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- KDYFGRWQOYBRFD-NUQCWPJISA-N butanedioic acid Chemical compound O[14C](=O)CC[14C](O)=O KDYFGRWQOYBRFD-NUQCWPJISA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
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- 238000001704 evaporation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
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- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
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Abstract
本发明提供一种高电子迁移率晶体管及其制备方法，涉及半导体技术领域，包括在第二N+型掺杂层上沉积金属以分别形成源极和漏极。在第二N+型掺杂层上形成第一凹槽。在砷化铟镓刻蚀阻挡层和第一N型掺杂层上形成第二凹槽。在砷化铝刻蚀阻挡层上形成第三凹槽，其中，第一凹槽、第二凹槽和第三凹槽连通以作为栅极凹槽。在栅极凹槽内沉积金属以形成与低能隙遂穿层接触的栅极。由于在栅极和势垒层之间插入了低能隙遂穿层，在第一N型掺杂层和第二N+型掺杂层之间设置有砷化铟镓刻蚀阻挡层，故，可以有效降低源极和漏极的欧姆接触的电阻，进而进一步的降低器件导通电阻，便于提高器件性能。
The present invention provides a high electron mobility transistor and a preparation method thereof, which relates to the field of semiconductor technology, including depositing metal on a second N+ type doped layer to form a source and a drain respectively. A first groove is formed on the second N+ type doped layer. A second groove is formed on an indium gallium arsenide etching barrier layer and a first N-type doped layer. A third groove is formed on an aluminum arsenide etching barrier layer, wherein the first groove, the second groove and the third groove are connected to serve as a gate groove. Metal is deposited in the gate groove to form a gate in contact with a low energy gap tunneling layer. Since a low energy gap tunneling layer is inserted between the gate and the barrier layer, and an indium gallium arsenide etching barrier layer is provided between the first N-type doped layer and the second N+ type doped layer, the resistance of the ohmic contact of the source and the drain can be effectively reduced, thereby further reducing the on-resistance of the device, which is convenient for improving the performance of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high electron mobility transistor and a preparation method thereof.
Background
High electron mobility transistors (High electron mobility transistor, HEMT), also known as modulation doped field effect transistors, use two materials with different energy gaps to form a heterojunction that provides a channel for carriers. High electron mobility transistors can operate at extremely high frequencies and are therefore widely used in mobile phones, satellite televisions and radar.
When the conventional high electron mobility transistor is used as a power device, a double-groove structure is generally adopted, namely, after a first etching barrier layer, an N-doped layer, a second etching barrier layer and an N+ doped layer are sequentially formed on a barrier layer, two communicated grooves are formed on the first etching barrier layer, the N-doped layer, the second etching barrier layer and the N+ doped layer, and an ohmic contact source electrode and an ohmic contact drain electrode are further arranged on the N+ doped layer, but the first etching barrier layer and the second etching barrier layer are both high-energy band gap layers, so that ohmic contact resistance is large, and device performance is affected.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a high electron mobility transistor and a preparation method thereof so as to reduce the on-resistance of the device.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the invention is as follows:
In one aspect of the embodiment of the invention, a method for preparing a high electron mobility transistor is provided, which comprises the steps of sequentially forming a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low-energy-gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N+ type doping layer on a substrate, depositing metal on the second N+ type doping layer to form a source electrode and a drain electrode respectively, etching the second N+ type doping layer in a region between the source electrode and the drain electrode and terminating at the indium gallium arsenide etching barrier layer to form a first groove, sequentially etching the indium gallium arsenide etching barrier layer and the first N-type doping layer in the first groove and terminating at the aluminum arsenide etching barrier layer to form a second groove, etching the aluminum arsenide etching barrier layer in the second groove and terminating at the low-energy-gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are communicated to form a gate groove, and depositing metal in the gate groove to form a gate electrode in contact with the low-energy-gap tunneling layer.
Optionally, a buffer layer is also formed between the substrate and the channel layer.
Optionally, a second doping layer and a second isolation layer are sequentially formed between the buffer layer and the channel layer.
Optionally, the low-energy gap tunneling layer is a gallium arsenide layer or an indium gallium arsenide layer.
Optionally, etching the second N+ doped layer in the region between the source and the drain and terminating in the InGaAs etch stop layer to form the first recess includes etching the second N+ doped layer in the region between the source and the drain by citric acid and terminating in the InGaAs etch stop layer to form the first recess.
Optionally, sequentially etching the InGaAs etch stop layer and the first N-doped layer in the first recess and terminating in the AlAs etch stop layer to form a second recess includes sequentially etching the InGaAs etch stop layer and the first N-doped layer in the first recess with succinic acid and terminating in the AlAs etch stop layer to form a second recess.
Optionally, the thickness of the aluminum arsenide etching barrier layer and the indium gallium arsenide etching barrier layer is 1nm to 5nm.
Optionally, the thickness of the channel layer is 5-15 nm, the thickness of the first isolation layer is 3-8 nm, the thickness of the barrier layer is 12-20 nm, the thickness of the low-energy-gap tunneling layer is 1-5 nm, the thickness of the first N-type doped layer is 10-40 nm, and the thickness of the second N+ type doped layer is 30-80 nm;
Optionally, the first doped layer and the second doped layer are planar doped layers.
In another aspect of the embodiment of the invention, a high electron mobility transistor is provided, which comprises a substrate, a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low-energy-gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N+ type doping layer which are sequentially arranged on the substrate, wherein a grid groove is formed on the surface of the first N-type doping layer, penetrates through the second N+ type doping layer, the indium gallium arsenide etching barrier layer, the first N-type doping layer and the aluminum arsenide etching barrier layer in sequence to expose the low-energy-gap tunneling layer, a source electrode and a drain electrode which are in contact with the second N+ type doping layer are arranged on two sides of the grid groove, and a grid electrode which is in contact with the low-energy-gap tunneling layer is arranged in the grid groove.
The beneficial effects of the invention include:
The invention provides a high electron mobility transistor and a preparation method thereof, the method comprises the steps of sequentially forming a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low-energy-gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N+ type doping layer on a substrate. Metal is deposited on the second n+ doped layer to form a source and a drain, respectively. And forming a first groove on the second N+ type doped layer. And forming a second groove on the InGaAs etching barrier layer and the first N-type doped layer. And forming a third groove on the aluminum arsenide etching barrier layer, wherein the first groove, the second groove and the third groove are communicated to serve as a grid groove. Metal is deposited in the gate recess to form a gate electrode in contact with the low energy gap tunneling layer. Thereby forming a schottky contact with the barrier layer below the low-bandgap tunneling layer. Since the low-bandgap tunneling layer is interposed between the gate electrode and the barrier layer, on-resistance between the source electrode and the drain electrode can be reduced. On the basis, the level between the first N-type doped layer and the second N+ type doped layer is set as the InGaAs etching barrier layer, so that the InGaAs etching barrier layer not only can play a role in blocking when etching the second N+ type doped layer, but also can effectively reduce the resistance of ohmic contact of the source electrode and the drain electrode after the device structure is formed because the InGaAs etching barrier layer is made of a low-energy-gap material, and further reduce the on-resistance of the device, thereby being convenient for improving the device performance.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for preparing a high electron mobility transistor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a state of a high electron mobility transistor according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing a second state of a HEMT according to an embodiment of the present invention;
FIG. 4 is a third schematic diagram illustrating a state of a HEMT according to an embodiment of the invention;
FIG. 5 is a schematic diagram showing a state of a high electron mobility transistor according to an embodiment of the present invention;
FIG. 6 is a schematic diagram showing a state of a high electron mobility transistor according to an embodiment of the present invention;
FIG. 7 is a schematic diagram showing a state of a high electron mobility transistor according to an embodiment of the present invention;
Fig. 8 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention.
The icons are 100-substrate, 210-buffer layer, 220-second doped layer, 230-second isolation layer, 240-channel layer, 250-first isolation layer, 260-first doped layer, 270-barrier layer, 280-low energy gap tunneling layer, 290-aluminum arsenide etch stop layer, 310-first N-doped layer, 320-indium gallium arsenide etch stop layer, 330-second N+ doped layer, 340-source electrode, 350-drain electrode, 360-gate recess, 361-first recess, 362-second recess, 370-gate electrode, 410-first patterned photoresist layer, 420-second patterned photoresist layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. It should be noted that, under the condition of no conflict, the features of the embodiments of the present invention may be combined with each other, and the combined embodiments still fall within the protection scope of the present invention.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In order to have better device performance, the existing high electron mobility transistor generally adopts two etching barrier layers to realize a double-groove structure, but because the two etching barrier layers are high-energy band gap layers, the formed ohmic contact resistance is larger, and the device performance is influenced. Therefore, in one aspect of the embodiments of the present application, by providing a method for manufacturing a High Electron Mobility Transistor (HEMT), the on-resistance of the device is reduced, and the performance of the device is improved. As shown in fig. 1, the steps of the preparation method are schematically shown, including:
and S010, sequentially forming a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low-energy-gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N+ type doping layer on the substrate.
As shown in fig. 2, a substrate 100 is provided, and the substrate 100 may be a substrate for carrying semiconductor integrated circuit devices, such as gallium arsenide, silicon carbide, and the like. To form an epitaxial layer of a pseudomorphic doped heterojunction field effect transistor (pHEMT), a channel layer 240, a first isolation layer 250, a first doped layer 260, a barrier layer 270, a low-bandgap tunneling layer 280, an aluminum arsenide etch stop layer 290, a first N-doped layer 310, an indium gallium arsenide etch stop layer 320, and a second n+ -doped layer 330 may also be formed sequentially on the substrate 100 described above. The formation of each epitaxial layer can be performed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or the like, which is not limited by the present application, and can be reasonably selected according to practical requirements.
And S020, depositing metal on the second N+ type doped layer to form a source electrode and a drain electrode respectively.
When forming the epitaxial layer of the pHEMT device in S010, as shown in fig. 2, metal may be continuously deposited on the uppermost layer of the epitaxial layer, i.e., the second n+ type doped layer 330 to form the source electrode 340 and the drain electrode 350, respectively, so that ohmic contact of the device is formed by the contact of the source electrode 340 with the second n+ type doped layer 330 and the contact of the drain electrode 350 with the second n+ type doped layer 330, and the source electrode 340 and the drain electrode 350 may be spaced apart in order to ensure the performance of the device.
And S030, etching a second N+ type doped layer in the region between the source electrode and the drain electrode and stopping at the InGaAs etching barrier layer to form a first groove.
As shown in fig. 3, the etching manner may be to coat a photoresist layer on the upper surfaces of the second n+ type doped layer 330 and the source electrode 340 and the drain electrode 350, and form a patterned photoresist layer with a window region after exposing, developing and hard baking, wherein the window region is located in a region between the source electrode 340 and the drain electrode 350, and the second n+ type doped layer 330 exposed in the window region is removed by etching solution or physical etching until the second n+ type doped layer is terminated in the indium gallium arsenide etching barrier layer 320, wherein during etching, a relatively high etching solution may be selected according to the second n+ type doped layer 330 and the indium gallium arsenide etching barrier layer 320, so that the etching depth can be controlled during etching the second n+ type doped layer 330, thereby forming the first groove 361 structure on the second n+ type doped layer 330. After forming the first recess 361, the patterned photoresist layer may be stripped and removed, forming the structure shown in fig. 3.
And S040, sequentially etching the InGaAs etching barrier layer and the first N-type doping layer in the first groove and ending at the AlAs etching barrier layer to form a second groove.
As shown in fig. 4, a photoresist layer is continuously coated on the structure formed in S030, and then a first patterned photoresist layer 410 is formed through processes such as exposure and development, and a window region of the first patterned photoresist layer is located in the first groove 361, so that the indium gallium arsenide etching barrier layer 320 is exposed in the window region. The etching solution and other methods remove the gallium arsenide etching barrier layer 320 exposed in the window area in the first groove 361, then expose the first N-type doped layer 310 below, and then continue to etch the exposed first N-type doped layer 310 until the etching is stopped at the aluminum arsenide etching barrier layer 290, so as to form the second groove 362 on the gallium arsenide etching barrier layer 320 and the first N-type doped layer 310, as shown in fig. 6, wherein when the gallium arsenide etching barrier layer 320 and the first N-type doped layer 310 are etched sequentially, the etching can be performed by the same etching solution, or by two etching solutions, but when the first N-type doped layer 310 is etched, the etching solution with a relatively high etching selection should be selected according to the first N-type doped layer 310 and the aluminum arsenide etching barrier layer 290 to etch the first N-type doped layer 310, so that the etching depth of the first N-type doped layer 310 can be controlled by the aluminum arsenide etching barrier layer 290.
And S050, etching the aluminum arsenide etching barrier layer in the second groove and ending at the low-energy-gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are communicated to serve as a grid groove.
After the structure shown in fig. 6 is formed in S040, the aluminum arsenide barrier layer is continuously removed in the second groove 362 by etching until the low-bandgap tunneling layer 280 under the aluminum arsenide barrier layer is exposed, so as to form the structure shown in fig. 7, and the etching may refer to the above-mentioned manner of forming the first groove 361 and the second groove 362 by etching, which is not repeated here. In this way, the third groove can be formed on the aluminum arsenide barrier layer, and since the second groove 362 is formed in the first groove 361 and the third groove is formed in the second groove 362, the three grooves are sequentially communicated along the forming sequence, and the whole communicated groove can be used as the gate groove 360. In this way, by sequentially etching the second n+ type doped layer 330, the indium gallium arsenide etching barrier layer 320, the first N type doped layer 310 and the aluminum arsenide etching barrier layer 290, a double-groove device structure can be formed, so that the breakdown voltage is improved, and the device has better performance. It should be noted that, when etching the first N-doped layer 310 and the aluminum arsenide etching barrier layer 290, the etching should be performed in two steps, so that the barrier effect can be achieved by the aluminum arsenide etching barrier layer 290 when etching the first N-doped layer 310, and similarly, the etching should be performed in two steps when etching the second n+ doped layer 330 and the indium gallium arsenide etching barrier layer 320.
And S060, depositing metal in the gate groove to form a gate electrode contacted with the low-energy-gap tunneling layer.
After forming the gate recess 360 in S050, metal may be deposited within the gate recess 360 to form the gate 370 of the pHEMT device, and the gate 370 is in contact with the low-bandgap tunneling layer 280 to form a schottky contact with the barrier layer 270 under the low-bandgap tunneling layer 280. Since the low-bandgap tunneling layer 280 is interposed between the gate electrode 370 and the barrier layer 270, on-resistance between the source electrode 340 and the drain electrode 350 may be reduced. On the basis, the level between the first N-type doped layer 310 and the second n+ type doped layer 330 is set as the InGaAs etching barrier layer 320, so that the InGaAs etching barrier layer 320 not only can play a role in blocking when the second n+ type doped layer 330 is etched, but also can effectively reduce the ohmic contact resistance of the source electrode 340 and the drain electrode 350 after the device structure is formed because the InGaAs etching barrier layer 320 is made of a low-energy-gap material, thereby further reducing the on resistance of the device and facilitating the improvement of the device performance.
In an embodiment of the present application, low-bandgap tunneling layer 280 may be a gallium arsenide layer or an indium gallium arsenide layer, such that the resistance of source 340 and drain 350 forming an ohmic contact is reduced. The aluminum arsenide etch stop layer 290 is a high energy gap material that can effectively increase the breakdown voltage of the device. The first N-doped layer 310 may be an N-doped layer.
As shown in fig. 5, in order to form the T-shaped gate 370 in the gate recess 360, the second patterned photoresist layer 420 may be further formed on the first patterned photoresist layer 410, so that the second patterned photoresist layer 420 may be trimmed to form a concave shape, so that the T-shaped region in fig. 5 is formed, and after the gate recess 360 is formed as shown in fig. 7, the second patterned photoresist layer 420 and the first patterned photoresist layer are stripped by evaporation of gate metal, so that the T-shaped gate 370 is formed, and thus the performance of the device is further improved.
Optionally, as shown in fig. 2, in order to improve performance of the pHEMT device, a buffer layer 210 may be further formed between the substrate 100 and the channel layer 240, so that a subsequent second doped layer 220 or second isolation layer 230 may be better formed on the substrate 100.
Optionally, a second doped layer 220 and a second isolation layer 230 are sequentially formed between the buffer layer 210 and the channel layer 240, where the second doped layer 220 and the channel layer 240 are separated by the first isolation layer 250, and the second isolation layer 230 is used to separate the second doped layer 240 from the channel layer 240, so as to further ensure the performance of the device. The first isolation layer 250 and the second isolation layer 230 are undoped layers.
Alternatively, since the second N+ type doped layer 330 may be etched by the citric acid and the InGaAs etch stop layer 320 has a good etch stop for the citric acid, when the second N+ type doped layer 330 is etched and terminated at the InGaAs etch stop layer 320 in the region between the source electrode 340 and the drain electrode 350 to form the first recess 361, the second N+ type doped layer 330 may be etched and terminated at the InGaAs etch stop layer 320 by the citric acid to form the first recess 361 on the second N+ type doped layer 330.
Alternatively, in a similar manner, since succinic acid can etch the gallium indium arsenide etching barrier layer 320, and simultaneously, can also etch the first N-type doped layer 310, and the succinic acid can have good etching stopping property through the aluminum arsenide layer, the gallium indium arsenide etching barrier layer 320 and the first N-type doped layer 310 can be sequentially etched in the first groove 361 and terminated in the aluminum arsenide etching barrier layer 290 to form the second groove 362, and the gallium indium arsenide etching barrier layer 320 and the first N-type doped layer 310 can be sequentially etched through succinic acid and terminated in the aluminum arsenide etching barrier layer 290 to form the second groove 362. Thus, the gallium indium arsenide etching barrier layer 320 and the first N-type doped layer 310 can be etched by one step through the succinic acid, and etching steps are saved.
By using the combination of citric acid and succinic acid at different stages, the gate recess 360 can be effectively formed when the etching barrier layer between the first N-type doped layer 310 and the second n+ -type doped layer 330 is the InGaAs etching barrier layer 320.
Alternatively, setting the thickness of the aluminum arsenide etching barrier layer 290 to be 1nm to 5nm, such as 2, 3, 4nm, etc., and setting the thickness of the indium gallium arsenide etching barrier layer 320 to be 1nm to 5nm, such as 2, 3, 4nm, etc., can effectively improve the performance of the device.
Alternatively, the thickness of the channel layer 240 of the pHEMT device may be set to 5nm to 15nm, for example, 8, 11, 13nm, etc., the thickness of the first isolation layer 250 is 3nm to 8nm, for example, 5nm, 7nm, etc., the thickness of the barrier layer 270 is 12nm to 20nm, for example, 15, 18nm, etc., the thickness of the low-bandgap tunneling layer 280 is 1nm to 5nm, for example, 2,3, 4nm, etc., the thickness of the first N-type doped layer 310 is 10nm to 40nm, and the thickness of the second n+ type doped layer 330 is 30nm to 80nm, so that the performance of the device may be effectively improved, enabling the pHEMT device to have a lower on-resistance.
Optionally, the first doped layer 260 and the second doped layer 220 are planar doped layers, which can effectively reduce the trap effect, and at the same time facilitate the pinch-off voltage control, improve the breakdown voltage of the gate 370, and increase the carrier concentration in the channel layer 240.
In another aspect of the embodiment of the present invention, as shown in fig. 8, a high electron mobility transistor is provided, including a substrate 100, and a channel layer 240, a first isolation layer 250, a first doped layer 260, a barrier layer 270, a low-bandgap tunneling layer 280, an aluminum arsenide etching barrier layer 290, a first N-type doped layer 310, an indium gallium arsenide etching barrier layer 320 and a second n+ type doped layer 330 sequentially disposed on the substrate 100, wherein a gate groove 360 is formed on a surface of the first N-type doped layer 310, the gate groove 360 penetrates through the second n+ type doped layer 330, the indium gallium arsenide etching barrier layer 320, the first N-type doped layer 310 and the aluminum arsenide etching barrier layer 290 in order to expose the low-bandgap tunneling layer 280, a source 340 and a drain 350 contacting the second n+ type doped layer 330 are disposed on two sides of the gate groove 360, and a gate 370 contacting the low-bandgap tunneling layer 280 is disposed in the gate groove 360. Since the low-bandgap tunneling layer 280 is interposed between the gate electrode 370 and the barrier layer 270, on-resistance between the source electrode 340 and the drain electrode 350 may be reduced. On the basis, the level between the first N-type doped layer 310 and the second n+ type doped layer 330 is set as the InGaAs etching barrier layer 320, so that the InGaAs etching barrier layer 320 not only can play a role in blocking when the second n+ type doped layer 330 is etched, but also can effectively reduce the ohmic contact resistance of the source electrode 340 and the drain electrode 350 after the device structure is formed because the InGaAs etching barrier layer 320 is made of a low-energy-gap material, thereby further reducing the on resistance of the device and facilitating the improvement of the device performance.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method of manufacturing a high electron mobility transistor, the method comprising:
sequentially forming a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low-energy-gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N+ type doping layer on a substrate;
Depositing metal on the second N+ type doped layer to form a source electrode and a drain electrode respectively;
Etching the second N+ type doped layer in a region between the source electrode and the drain electrode and terminating in the InGaAs etching barrier layer to form a first groove;
Sequentially etching the InGaAs etching barrier layer and the first N-type doping layer in the first groove and terminating at the AlAs etching barrier layer to form a second groove;
Etching the aluminum arsenide etching barrier layer in the second groove and ending at the low-energy-gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are communicated to serve as a grid groove;
metal is deposited in the gate recess to form a gate electrode in contact with the low-bandgap tunneling layer.
2. The method of manufacturing a high electron mobility transistor according to claim 1, wherein a buffer layer is further formed between the substrate and the channel layer.
3. The method of manufacturing a high electron mobility transistor according to claim 2, wherein a second doping layer and a second isolation layer are sequentially formed between the buffer layer and the channel layer.
4. A method of fabricating a high electron mobility transistor according to any one of claims 1 to 3, wherein the low bandgap tunneling layer is a gallium arsenide layer or an indium gallium arsenide layer.
5. A method of fabricating a high electron mobility transistor according to any one of claims 1 to 3, wherein said etching the second n+ -doped layer in the region between the source and the drain and terminating in the indium gallium arsenide etch stop layer to form a first recess comprises:
And etching the second N+ type doped layer in the region between the source electrode and the drain electrode through citric acid and ending at the InGaAs etching barrier layer to form a first groove.
6. The method of manufacturing a high electron mobility transistor of any one of claims 1 to 3, wherein sequentially etching the indium gallium arsenide etch stop layer and the first N-doped layer within the first recess and terminating in the aluminum arsenide etch stop layer to form a second recess comprises:
and etching the InGaAs etching barrier layer and the first N-type doped layer in the first groove in sequence through succinic acid and ending at the AlAs etching barrier layer to form a second groove.
7. A method of fabricating a high electron mobility transistor according to any one of claims 1 to 3, wherein the thickness of the aluminum arsenide etch barrier layer and the indium gallium arsenide etch barrier layer are each 1nm to 5nm.
8. The method of manufacturing a high electron mobility transistor according to claim 7, wherein the thickness of the channel layer is 5nm to 15nm, the thickness of the first isolation layer is 3nm to 8nm, the thickness of the barrier layer is 12nm to 20nm, the thickness of the low-bandgap tunneling layer is 1nm to 5nm, the thickness of the first N-type doped layer is 10nm to 40nm, and the thickness of the second n+ -type doped layer is 30nm to 80nm.
9. The method of manufacturing a high electron mobility transistor according to claim 3, wherein the first doped layer and the second doped layer are planar doped layers.
10. A high electron mobility transistor is characterized by comprising a substrate, a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low-energy-gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N+ type doping layer which are sequentially arranged on the substrate, wherein a grid groove is formed in the surface of the first N-type doping layer, the grid groove penetrates through the second N+ type doping layer, the indium gallium arsenide etching barrier layer, the first N-type doping layer and the aluminum arsenide etching barrier layer in sequence to expose the low-energy-gap tunneling layer, a source electrode and a drain electrode which are in contact with the second N+ type doping layer are arranged on two sides of the grid groove, a grid electrode which is in contact with the low-energy-gap tunneling layer is arranged in the grid groove, and the grid electrode is a T-shaped grid electrode.
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