CN113242188B - Microwave channel full-switching network construction method, control method and coding and decoding method - Google Patents

Abstract

The invention discloses a microwave channel full-switching network construction method, a control method and a coding and decoding method, which comprise the following steps: s1, designing an input network, carrying out binary tree mesh expansion on each port in the ports on the input side, and ending the expansion until a plurality of terminal nodes are generated; s2, designing an output network, performing binary tree mesh expansion on each port of the output side port by using a switch, and ending the expansion until a plurality of terminal nodes are generated; s3, designing a cross network, wherein the input network completes cross interconnection between sub-nodes of the input and output networks in the step; the invention realizes a microwave channel full-switching network which can be expanded at will and has no pre-stored code table, and provides a regular input control coding and decoding method.

Description

Microwave channel full switching network construction method, control method, coding and decoding method

technical field

The present invention relates to the fields of microwave, control, coding and decoding, and more particularly, to a method for constructing a microwave channel full switching network, a control method, and a coding and decoding method.

Background technique

In order to meet the needs of complex beam switching and digital processing reconstruction in modern multi-channel receiving systems, it is necessary to construct a microwave channel switching network that can be switched arbitrarily between the antenna array and the digital processor. The current complex switching network mainly adopts the following methods: (1) The control is implemented in the form of a storage lookup table. Generally, due to the arbitrary path selection of the full switching network, the coding and decoding process for the switch control is cumbersome and irregular, so it is not suitable for the implementation of embedded software with limited logic resources, and the scalability is poor; (2 ) complex low-frequency control network and microwave switching network, the signals are arranged vertically and horizontally, but too much cross-coupling will reduce the quality of signal transmission, such as increasing the probability of crosstalk.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies of the prior art, provide a method for constructing a microwave channel full-switching network, a control method, and a coding and decoding method, and realizes a microwave channel full-switching network that can be expanded arbitrarily and has no pre-stored code table. A coding and decoding method that can be regularized and controlled by input, which can be connected in series to expand the serial-to-parallel conversion chip to control the switching action to realize arbitrary signal routing. In the embodiment, the construction of the control circuit unit can be programmed, and the network scale is easy to expand, which is beneficial to improve the signal exchange transmission quality and the electromagnetic compatibility.

The purpose of this invention is to realize through the following scheme:

A method for constructing a microwave channel full switching network, comprising the steps of:

S1, design the input network, perform binary tree mesh expansion on each port in the input side port, and expand to generate multiple terminal nodes;

S2, design an output network, use a switch to perform binary tree mesh expansion on each port on the output side, and expand to generate multiple terminal nodes;

S3, design a cross network, in this step, the input network completes the cross interconnection between the child nodes of the input and output networks.

Further, in step S3, including steps:

S31, the xxxth node in the tree-type expansion network of the nth input port in the input side port is numbered as RFn_xxx; n is a positive integer;

S32, convert the binary-coded node serial number xxx into a decimal number X, and the node is the mth=X+1th node of the nth input port;

S33, the yyyth node in the tree-type expansion network of the mth output port in the output side port, and its node number is RFm_yyy;

S34, convert the binary-coded node serial number yyy into a decimal number Y, and the node is the n=Y+1 node of the mth output port;

S35, interconnect the mth node of the nth input port to the nth node of the mth output port through a high-frequency transmission line.

Further, the crossover network can be physically implemented using microwave multilayer boards or cables.

A control method based on any one of the above-mentioned microwave channel full-switching networks, comprising the steps of:

A1, design the control unit, use the serial shift register circuit to control the switch of the switching network, and carry out coding control by means of serial control code bit input and parallel control code bit output. When the network scale expansion leads to the need to increase the parallel bit , which is extended by connecting multiple registers in series;

A2, based on the control unit in step A1, implement the control code bit mapping process corresponding to the input and output network control lines.

Further, in step A2, it specifically includes steps:

A21, perform code bit mapping on the switch control line of the tree network formed on the nth input port side, the control line mapping code bit of the first column of switches is (n-1)*r+1, and the control line of the second column of switches controls The line mapping code bits are (n-1)*r+2, increasing in turn, and the control line code bits of the switch in the rth column are mapped to n*r; in this way, the N tree-shaped networks formed by N input ports need The code points are numbered from 1 to Nr;

A22, according to the same process as in step A21, perform code bit mapping on the switch control lines of the tree network formed on the M output port sides to obtain code bit numbers Nr+1 to Nr+Mc.

A coding and decoding method based on the control method of any one of the above-mentioned microwave channel full-switching networks, comprising the steps of:

B1, write out the code point number corresponding to each input port according to the control code point mapping process corresponding to the input and output network control lines; the code point number of network input port number 1 is 1~r, and the code point number of network input port number 2 is r+1～2r, and so on, the code point number of the network input port number N is (N-1)*r+1～N*r;

B2, starting from the input port number 1, according to the number of the connected output port of its routing selection, the code value of the first input port corresponding to the code positions 1 to r is given; the code value is the output port number -1 corresponding to the connected output port number of the routing selection the binary value of ;

B3, according to the output port number routed from the input port number 2 to the input port number N, the code value of the corresponding remaining code bits is given; that is, after the code bits from the input port number 2 to the input port number N are obtained from step B1 , according to the number of the connected output ports of the routing selection of the input ports, the code values of the code bits r+1～N*r corresponding to these ports are given, and the code value is the binary value corresponding to the number of the connected output ports of the routing selection -1;

B4, according to the input port number selected by the output port number routing, the code value of the corresponding code position of all output ports is given; that is, the code position corresponding to the first output port number is N*r+1～N*r+c, in order By analogy, the code bit corresponding to the output port number M is N*r+(M-1)*c+1～N*r+M*c, and the code value is the binary value corresponding to the input port number-1 connected by routing;

B5, when the hardware description language is used to describe the circuit, it is described in sequence according to the priority of the logic selection; the code value process of the input port network code bit corresponding to the input port number 1 is preferentially described, and in this process, the input port 1 selection is given. The network code bits of the output port of , so as to obtain the code bits 1～r, and the values of c code bits among N*r+1～Nr+Mc under the condition that the code values of the 1～r code bits are determined;

B6, describe the decoding process of the input port number 1 with the highest priority, and then describe the decoding process of the input port number 2 to obtain the code bits r+1～2*r, and the code bits at r+1～2*r The value of c code bits among N*r+1～Nr+Mc under the condition of value selection; through the above compilation process, the code value of N*r code bits is input each time to complete all the switches involved in one exchange switch control.

The beneficial effects of the present invention include:

The invention realizes a microwave channel full-switching network that can be expanded arbitrarily and has no pre-stored code table, and at the same time provides a coding and decoding method that can be regularized input control, and controls the switching action through a serial-parallel conversion chip that can be connected in series and expandable. , to achieve arbitrary signal routing. In the embodiment, the construction of the control circuit unit can be programmed, and the network scale is easy to expand, which is beneficial to improve the signal exchange transmission quality and improve the electromagnetic compatibility.

In the embodiment of the present invention, the complex switching network is decoupled into functionally independent units, and the design and implementation process is simplified;

In the embodiment of the present invention, the network scale is easy to expand, and a switching network of any scale can be completed through the expansion of the tree-shaped network;

In the embodiment of the present invention, the design process is stylized, the circuit interconnection of the input and output distribution network, the control bit coding method, etc. are parameterized, and the semi-automatic design can be carried out according to the design parameters through automatic wiring assistance, etc.;

In the embodiment of the present invention, there is no need to pre-store the control code table, which saves the storage resources of the logic device, and is suitable for field programmable logic device (FPGA, etc.) implementation;

In the embodiment of the present invention, the control of switching routing, etc. is accomplished using a limited serial code value (N*r bits).

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic diagram of an input network formation method in an embodiment of the present invention;

FIG. 2 is a schematic diagram of a method of forming an output network in an embodiment of the present invention;

FIG. 3 is a schematic diagram of a method for forming a cross network in an embodiment of the present invention;

4 is a schematic diagram of a hardware circuit composition of a control unit in an embodiment of the present invention;

5 is a schematic diagram of an input network code bit numbering of an nth input port in an embodiment of the present invention;

6 is a schematic diagram of the output network code bit numbering of the mth output port in the embodiment of the present invention;

FIG. 7 is a schematic diagram of a 2*4 switching network relationship in an embodiment of the present invention.

Detailed ways

All features disclosed in all embodiments in this specification, or steps in all methods or processes that are implicitly disclosed, except mutually exclusive features and/or steps, may be combined and/or expanded or replaced in any manner.

Example 1

As shown in Figures 1 to 7, in this embodiment, a specific implementation of a switching network in a scale of N*M (parameter N, M is an integer power of 2, for example, N=2 ^c , M=2 ^r ) Detailed description.

The design method of the embodiment of the present invention includes the following implementation steps:

In the input network design, a single-pole double-throw switch (SPDT) is used for each of the N ports on the input side to perform a binary tree mesh expansion, and the expansion ends with the generation of M terminal nodes. The expansion diagram of the nth port is shown in Figure 1. The tree node is represented by RFn_xxx, which represents the xxx node of the nth input port. (Note: Optionally, when the SPDT switch used selects the upper branch, the binary switch logic control value of the control line is "0", and when the lower branch is selected, the switch logic control value is "1".)

In the design of the output network, a single-pole double-throw switch is used for each port of the M ports on the output side to perform a binary tree mesh expansion, and the expansion ends with the generation of N terminal nodes. The expansion diagram of the mth port is shown in Figure 2. The tree node is represented by RFm_xxx, which represents the xxx node of the mth output port.

Cross-network design, in this step, the input network completes the cross-interconnection between the sub-nodes of the input and output networks, and the interconnection method specifically includes:

The xxxth node in the tree-type expansion network of the nth input port in the input side ports (N input ports in total) is numbered as RFn_xxx;

Convert the binary-coded node serial number xxx into a decimal number X, and the node is the m=X+1th node of the nth input port. For example, the node number RF5_010 represents the third node of the fifth input port;

Extend the yyyth node in the tree-type expansion network of the mth output port among the ports on the output side (total M output ports), and its node number is RFm_yyy;

Convert the binary-coded node serial number yyy to a decimal number Y, and the node is the n=Y+1th node of the mth output port. For example, the node number RF2_100 represents the fifth node of the second output port;

Interconnect the mth node of the nth input port to the nth node of the mth output port through a high-frequency transmission line;

To complete the entire cross-connection, M*N interconnection lines are required;

The crossover network can be physically implemented using microwave multilayer boards or cables.

The design of the control unit, as shown in Figure 4, because the network scale is generally large, the control of the switch of the switching network adopts the serial shift register circuit, which is coded by serial control code bit input and parallel control code bit output. Control, when the network scale expansion leads to the need to increase the parallel bits, the expansion can be carried out by connecting multiple registers in series.

The control code bit mapping process corresponding to the input and output network control lines includes the steps:

Code bit mapping is performed on the SPDT switch control line of the tree network formed on the nth input port side. As shown in Figure 5, the control line mapping code bits of the switches in the first column are (n-1)*r+1, and the second column

The control line mapping code bit of the column switch is (n-1)*r+2, which increases in turn, and the control line code bit of the rth column switch is mapped to n*r. In this way, the code bit numbers required for the N tree-shaped networks formed by the N input ports are 1˜Nr.

According to the same method, as shown in FIG. 6 , code bit mapping is performed on the SPDT switch control lines of the tree network formed by the M output ports, and the code bits are numbered from Nr+1 to Nr+Mc.

The code value encoding process of each code bit requires 8 for an 8*8 network due to the arbitrary connectivity of the switching network! Therefore, using the traditional pre-stored look-up table method to form code values requires a lot of storage resources. The embodiment of the present invention proposes a code bit encoding method suitable for the realization of a field programmable logic device (FPGA or CPLD, etc.) in combination with the specific implementation process of the constructed network. The steps are as follows:

First, write out the code bit number corresponding to each input port according to the control code bit mapping process corresponding to the input and output network control lines. The code point number of the first input port of the network is 1~r, the code point number of the second input port is r+1~2r, and so on, the code point number of the Nth port is (N-1)*r +1～N*r;

Then, starting from the input port number 1, the connected output port number is selected according to its routing, and the code value of the first input port corresponding to the code bits 1 to r is given. The code value is the binary value corresponding to "Route selection connected output port number -1", and the mapping table is shown in the following table.

Table 1 The code value table of the corresponding code bit of the input port number

Input port number 1 corresponding code point code point 1 code point 2 code point 3 … code point r-1 code point r Input port number 2 corresponding code point Code point r+1 Code point r+2 Code point r+3 … Code point 2r-1 Code point 2r … … … … … … … Input port number N corresponds to the code point Code point (N-1)*r+1 Code point (N-1)*r+2 Code point (N-1)*r+3 … Code point N*r-1 Code point N*r output port number 1 0 0 0 … 0 0 output port number 2 0 0 0 … 0 1 output port number 3 … 1 0 … … … … … … … output port number M 1 1 1 … 1 1

In the same way, according to the input port number 2 to the input port number N "routed output port number", the code value of the corresponding remaining code bits is given.

In the same way, according to the output port number "routed input port number", the code values of the corresponding code bits of all output ports are given, and the mapping table is as follows.

Table 2 The code value table of the corresponding code bit of the output port number

When the hardware description language is used to describe the circuit, the description is carried out according to the priority of the logic selection, so as to avoid the logic conflict caused by the circuit synthesis. First describe the code value process of the input port network code bit corresponding to the input port number 1. In this process, the output port network code bit selected by the input port 1 should be given, so that the code bits 1 to r can be obtained, and between 1 to 1 The value of c code bits among N*r+1～Nr+Mc under certain conditions;

Taking the decoding process of the input port number 1 with the highest priority as an example, the description table of the decoding is as follows.

Table 3 The value table of the code point according to the destination of the input port number

Describe the decoding process of the input port number 2 again, the code bits r+1～2*r can be obtained, and among N*r+1～Nr+Mc under the condition of r+1～2*r code bit code value The value of the c code points of .

Through the above compiling process, each time a code value of N*r code bits is input, the control of all switches involved in one exchange switching can be completed.

Example 2

Taking a 2*4 switching network as an example, the design process is as follows:

The input network, output network, and crossover network are implemented as shown in Figure 7, and the design parameter values are N=2, M=4, c=1, and r=2.

The code point code value table defined according to the destination of the input port:

Table 4. The value table of the code point according to the destination of the input port number

For network control, it is necessary to select the route according to the input port number, and input the code value of N*r=4 code bits. For example, it is necessary to switch input port 1 to output port 3, input port 2 to output port 4, and need to input 4 Code point value [1,0,1,1], according to Table 3, the value of [code point 1: code point 8] is [1, 0, 1, 1, x, x, 0, 1] (x represents 0 or 1, any value), the above functions can be correctly realized through the signal flow relationship test of the network in Figure 7.

The parts not involved in the present invention are the same as the prior art or can be implemented by using the prior art.

The above technical solution is only an embodiment of the present invention. For those skilled in the art, on the basis of the application methods and principles disclosed in the present invention, it is easy to make various types of improvements or deformations, not limited to The methods described in the above-mentioned specific embodiments of the present invention, therefore, the methods described above are only preferred, and have no restrictive meaning.

In addition to the above examples, those skilled in the art can obtain enlightenment from the above disclosure or use knowledge or technology in the relevant field to make changes to obtain other embodiments, the features of each embodiment can be interchanged or replaced, and the changes and changes made by those skilled in the art Without departing from the spirit and scope of the present invention, all should fall within the protection scope of the appended claims of the present invention.

If the functions of the present invention are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, and the A computer device (which may be a personal computer, a server, or a network device, etc.) and corresponding software execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, or optical disk and other media that can store program codes, and the test or actual data exists in a read-only memory (Random Access Memory, RAM), random storage memory in the program implementation. Access memory (Random Access Memory, RAM) and so on.

Claims (2)

1. A control method for a microwave channel full-switching network is characterized by comprising the following steps:

a1, designing a control unit, performing coding control on the switch of a switching network by adopting a serial shift register circuit in a mode of inputting serial control code bits and outputting parallel control code bits, and when the parallel bits need to be increased due to network scale expansion, performing expansion by adopting a mode of connecting a plurality of registers in series;

a2, based on the control unit in the step A1, realizing the mapping process of the control code bit corresponding to the input/output network control line; in step a2, the method specifically includes the steps of:

a21, performing code bit mapping on a switch control line of the tree network formed on the nth input port side, wherein the control line mapping code bit of the first row of switches is (n-1) × r +1, the control line mapping code bit of the second row of switches is (n-1) × r +2, the control line mapping code bits are sequentially increased in number, and the control line code bit of the nth row of switches is mapped into n × r; according to the mode, code bits required by N tree networks formed by N input ports are numbered from 1 to Nr; n is an integer power of 2, N is an integer, r is an integer, and Nr is the product of N and r;

a22, performing code bit mapping on the switch control lines of the tree network formed on the M output port sides according to the same processing as the step a21 to obtain code bit numbers Nr +1 to Nr + Mc; m is an integer power of 2, c is an integer, and Mc is the product of M and c.

2. A coding and decoding method for a microwave channel full-switching network, comprising the method for controlling the microwave channel full-switching network according to claim 1, further comprising the steps of:

b1, writing out the code bit number corresponding to each input port according to the control code bit mapping process corresponding to the input/output network control line; the code bit number of the network input port number 1 is 1-r, the code bit number of the network input port number 2 is r + 1-2 r, and the analogy is repeated, and the code bit number of the network input port number N is (N-1) × r + 1-Nxr;

b2, starting from the input port number 1, selecting a communicated output port number according to the routing of the input port number, and giving a code value of code bits 1-r corresponding to the 1 st input port; the code value is a binary value corresponding to the output port number-1 communicated by the routing;

b3, according to the output port number from the input port number 2 to the input port number N, giving the code value of the corresponding residual code bit; after the code bits from the input port number 2 to the input port number N are obtained in the step B1, according to the input port routing selection communicated output port numbers, code values of the code bits r + 1-N × r corresponding to the ports are given, and the code values are binary values corresponding to the routing communicated output port number-1;

b4, according to the input port number selected by the output port number route, giving the code value of the code bit corresponding to all the output ports; the code bit corresponding to the 1 st output port number is N x r + 1-N x r + c, and the rest is done in sequence, the code bit corresponding to the output port number M is N x r + (M-1) c + 1-N x r + M, and the code value is a binary value corresponding to the input port number-1 communicated with the routing;

b5, when the circuit description is carried out by adopting the hardware description language, the circuit description is carried out in sequence according to the priority of the logic selection; preferentially describing a code value process of an input port network code bit corresponding to an input port number 1, wherein in the process, an output port network code bit selected by an input port 1 is given, so that code bits 1-r are obtained, and values of c code bits in Nr + 1-Nr + Mc are obtained under the condition that the code values of the code bits 1-r are obtained;

b6, describing a decoding process of the input port number 1 with the highest priority, then describing a decoding process of the input port number 2, obtaining code bits r + 1-2 r, and values of c code bits in the code bits N + 1-Nr + Mc under the condition that the code bits of the r + 1-2 r are determined; through the compiling process, the code values of the N x r code bits are input each time, and the control of all switches involved in one-time exchange switching is completed.

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