CN113241107B - Method and device for reducing data refreshing operation of three-dimensional memory - Google Patents

Abstract

The present application provides a method and device for reducing data refresh operations of a three-dimensional memory. When it is detected that the bit error rate of data in a storage block is greater than or equal to a first preset threshold, the storage block is used as a target storage block, and it is determined that the For the target storage layer in the target storage block, data refresh is performed on the adjacent layers of the target storage layer, and a programming voltage is applied to the storage pages of the adjacent layers of the target storage layer, so as to utilize the word line crosstalk effect to the storage pages in the target storage layer. Electrons are injected, and the programming voltage makes the threshold voltage of the storage page of the adjacent layer higher than the highest threshold voltage of the storage page of the memory. When it is detected that the bit error rate of the data in the target storage layer is greater than or equal to the first preset threshold, the The target storage tier performs data refresh. That is, through the word line crosstalk effect of adjacent layers on the target storage layer, the data storage time of the target storage layer is prolonged, the total data refresh times of the 3D memory are reduced, and the impact on the performance of the 3D memory due to data refresh is reduced.

Description

A method and apparatus for reducing data refresh operations of three-dimensional memory

technical field

The present invention relates to the field of semiconductor devices and their manufacture, and in particular, to a method and device for reducing data refresh operations of a three-dimensional memory.

Background technique

The characteristics of semiconductor memory devices may be volatile or non-volatile, and although volatile semiconductor memory devices can perform read and write operations at high speed, storage in a volatile semiconductor memory device in a power-off state is difficult. will be lost. In contrast, non-volatile semiconductor memory devices are characterized in that the stored contents are retained regardless of whether power is applied or not. A flash memory device (Flash memory) is an example of a typical nonvolatile semiconductor memory device, and the flash memory device can be widely used as a data storage medium.

In NAND Flash memory devices, different numbers of electrons can be injected into the floating gate or charge trapping layer to obtain different threshold voltages, thereby representing different logic states. Take Multi-Level Cell (MLC) NANDFlash as an example , When reading data, four logic states are distinguished by applying 3 different read voltages to the gate.

However, the threshold voltage of a memory cell generally varies with the characteristics of the memory device, the passage of time, and/or the ambient temperature. For example, as shown in FIG. 1, the electrons in the floating gate or charge trapping layer will increase with time. Gradually drain, reducing the threshold voltage of the memory cell. When the threshold voltage of the memory cell decreases from a voltage higher than the corresponding read voltage to a voltage lower than the corresponding read voltage, a read error will occur in the memory cell. , called the data retention error, and the data retention error will gradually increase with the increase of storage time. Error Correcting Code (ECC) can correct errors in read data, and is an important means to ensure the consistency of written data and read data, and to improve the reliability of a storage system. However, ECC also has a certain error correction range. If the original bit error rate of the read data is high, the error correction capability of the error control code will be exceeded, and the written data cannot be recovered correctly.

Referring to FIG. 2, it is a schematic diagram of a current data storage, the abscissa is the threshold voltage (threhold voltage), and the ordinate is the number of memory cells. The initial threshold voltage distribution state formed by the threshold voltage of the memory cell at zero time when data is written into the flash memory. The dotted line represents the threshold voltage distribution state of the flash memory after a period of storage time. It can be seen from the figure that after a period of storage time, Due to the leakage of the charge held by the memory cells, the threshold voltage distribution state of the flash memory is shifted to the side with the smaller threshold voltage, that is, the distribution state is shifted to the left. , Vread3 reads the flash memory, which will result in a higher bit error rate of the read data. It is very likely that the ECC check cannot be passed, and the correct stored data cannot be obtained.

Data retention error is the most important component of NAND Flash data error, which has the greatest impact on the reliability of NAND Flash. The longest storage time corresponding to when the data can finally be correctly read after storage is the data retention time. How to extend the data retention time? Retention time and reducing data retention errors are important research directions in this field.

When the bit error rate of the storage unit reaches a certain threshold, the data retention error is serious, and the data in the storage unit will be refreshed, and the data refresh operation of the memory will have a greater impact on the system performance of the memory. .

Data recovery technology refers to the technology of correct decoding by charging the cell with electrons to shift the threshold distribution to the right so as to reduce the error code to within the ECC error correction range. Schematic diagram of data recovery, the abscissa is the threshold voltage (Vth), the ordinate is the number of memory cells (Cell Count), and the curve distribution represents the initial threshold distribution (Initial Vth), the threshold distribution after the data retention time (After retention time) and the data The threshold value distribution after recovery (After data recovery), that is, after the data retention time has passed, the threshold voltage distribution state of the flash memory shifts to the side with the smaller threshold voltage, that is, the distribution state shifts to the left, and even the threshold voltage of some memory cells changes from The right side of the read voltage moves to the left side, causing the memory cell to read errors, and after data recovery, the threshold voltage can be shifted to the right, thereby reducing the bit error rate.

At present, two methods of reading voltage pulse and programming voltage pulse are used to charge the cell. These two methods have low charging efficiency, take a long time to charge, and cannot significantly reduce data retention errors.

Therefore, how to quickly and effectively reduce the data retention error of the three-dimensional memory, prolong the data storage time, and reduce the data refresh operation is a technical problem to be solved urgently in the art.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present application is to provide a method and device for reducing data refresh operations in a 3D memory, which can quickly and effectively reduce data retention errors in a 3D memory, prolong data storage time, and reduce data refresh operations.

To achieve the above object, the application has the following technical solutions:

In a first aspect, the present application provides a method for reducing a data refresh operation of a three-dimensional memory, including:

When it is detected that the bit error rate of the data in the storage block is greater than or equal to the first preset threshold, the storage block is used as the target storage block;

Determine the target storage tier located in the target storage block;

Data refresh is performed on the adjacent layers of the target storage layer, the refreshed data is stored in the first storage block, and the adjacent layers are marked as invalid, so that the adjacent layers are no longer used. data input;

A programming voltage is applied to memory pages of adjacent layers of the target memory layer to inject electrons into memory pages in the target memory layer by utilizing the word line crosstalk effect; the programming voltage makes the memory pages of the adjacent layers The threshold voltage is higher than the highest threshold voltage of the memory page of the memory, the memory page of the adjacent layer and the memory page in the target memory layer are connected in series;

When it is detected that the bit error rate of the data in the target storage layer is greater than or equal to a first preset threshold, data refresh is performed on the target storage layer.

Optionally, the target storage layer is an upper layer and/or a lower layer of the adjacent layer.

Optionally, the method further includes:

determining a target storage unit located in the target storage layer;

A programming voltage is applied to the programming cells in the adjacent layers of the target memory cell to inject electrons into the target memory cell using the word line crosstalk effect; the programming voltage makes the threshold voltage of the programming cell higher than that of the memory. The highest threshold voltage of the memory cell, the programming cell and the target memory cell are connected in series.

Optionally, the determining the target storage unit located in the target storage layer includes:

A read operation is performed on the memory cells located in the target memory layer by using at least one read voltage to determine a voltage range in which the threshold voltage of each of the memory cells is located; the voltage range is defined by the at least one read voltage, the read The voltage includes at least the first read voltage;

grouping each of the memory cells according to the voltage range in which the threshold voltage of each of the memory cells is located;

The memory cells in the groups whose threshold voltages are all greater than the first read voltage are used as target memory cells, and the memory cells in the groups whose threshold voltages are lower than the first read voltage are used as program suppression units.

Optionally, when the target storage layer is an upper layer or a lower layer of the adjacent layer, the grouping each of the storage cells according to the voltage range in which the threshold voltage of each of the storage cells is located includes: grouping the storage cells into groups. The memory cells located in the same voltage range are regarded as the same group, and each of the memory cells is grouped;

and / or,

When the target storage layer is the upper layer and the lower layer of the adjacent layers, the grouping each of the memory cells according to the voltage range in which the threshold voltage of each of the memory cells is located includes: grouping the memory cells with the corresponding memory cells. Among the memory cells of the two target layers connected to the same memory cell of the adjacent layer, the memory cell with a low threshold voltage is used as the reference cell, and the reference cells located in the same voltage range are regarded as the same group, and each of the reference cells is grouped, And let the memory cells of the two target layers connected to the same memory cell of the adjacent layer belong to the same group.

In a second aspect, the present application provides a device for reducing a data refresh operation of a three-dimensional memory, including:

a target storage block determination unit, configured to use the storage block as a target storage block when it is detected that the bit error rate of the data in the storage block is greater than or equal to a first preset threshold;

The target storage layer determination unit is used to determine the target storage layer located in the target storage block;

The adjacent layer data refresh unit is used to refresh the data of the adjacent layer of the target storage layer, store the refreshed data in the first storage block, and mark the adjacent layer as invalid, so as to causing the adjacent layer to no longer be written with data;

a programming voltage applying unit for applying a programming voltage to the memory pages of the adjacent layers of the target memory layer, so as to inject electrons into the memory pages in the target memory layer by utilizing the word line crosstalk effect; the programming voltage makes the The threshold voltage of the storage page of the adjacent layer is higher than the highest threshold voltage of the storage page of the memory, and the storage page of the adjacent layer is connected in series with the storage page in the target storage layer;

A target storage layer data refresh unit, configured to perform data refresh on the target storage layer when it is detected that the bit error rate of the data in the target storage layer is greater than or equal to a first preset threshold.

Optionally, the target storage layer is an upper layer and/or a lower layer of the adjacent layer.

Optionally, the device also includes:

a target storage unit determination unit, configured to determine a target storage unit located in the target storage layer;

A programming voltage applying subunit is used for applying a programming voltage to the programming cells in the adjacent layers of the target memory cell, so as to inject electrons into the target memory cell by using the word line crosstalk effect; the programming voltage makes the programming cell's The threshold voltage is higher than the highest threshold voltage of a memory cell of the memory, and the programming cell and the target memory cell are connected in series.

Optionally, the target storage unit determination unit includes:

a read unit, configured to perform a read operation on the memory cells located in the target layer by using at least one read voltage to determine a voltage range in which the threshold voltage of each of the memory cells is located; the voltage range is defined by the at least one read voltage, The read voltage includes at least a first read voltage;

a grouping unit, configured to group each of the memory cells according to the voltage range in which the threshold voltage of each of the memory cells is located;

The target storage unit determination subunit is used to use the storage cells in the groups whose threshold voltages are all greater than the first read voltage as the target storage cells, and use the storage cells in the groups whose threshold voltages are less than the first read voltage as the programming Suppression unit.

Optionally, the grouping unit is used for:

When the target storage layer is an upper layer or a lower layer of the adjacent layer, the grouping each of the memory cells according to the voltage range in which the threshold voltage of each of the memory cells is located includes: grouping the memory cells located in the same voltage range The described storage units are regarded as the same group, and each of the described storage units is grouped;

and / or,

When the target storage layer is the upper layer and the lower layer of the adjacent layers, the grouping each of the memory cells according to the voltage range in which the threshold voltage of each of the memory cells is located includes: grouping the memory cells with the corresponding memory cells. Among the memory cells of the two target layers connected to the same memory cell of the adjacent layer, the memory cell with a low threshold voltage is used as the reference cell, and the reference cells located in the same voltage range are regarded as the same group, and each of the reference cells is grouped, And let the memory cells of the two target layers connected to the same memory cell of the adjacent layer belong to the same group.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some embodiments of the present application, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 is a schematic diagram of the direction of electron movement in a current memory that is subject to data retention errors;

FIG. 2 is a schematic diagram of the distribution state of the threshold voltage of a current memory subject to a data retention error;

3 is a schematic diagram of a current data recovery;

4 is a flowchart of a method for reducing a data refresh operation of a three-dimensional memory provided by an embodiment of the present application;

5 is a schematic diagram of determining a target storage unit according to an embodiment of the present application;

6 is a schematic diagram of a target storage layer and an adjacent layer provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of a word line crosstalk effect provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of programming of a memory cell according to an embodiment of the present application;

9 is a schematic diagram of a data refresh operation performed by a target memory block grouping provided by an embodiment of the present application;

10 is a schematic diagram of bidirectional injection of electrons using word line crosstalk according to an embodiment of the present application;

11 is a schematic diagram of a data refresh operation performed by another target memory block grouping provided by an embodiment of the present application;

12 is a schematic diagram of a unidirectional injection of electrons using word line crosstalk according to an embodiment of the present application;

FIG. 13 is a schematic diagram of an apparatus for reducing a data refresh operation of a three-dimensional memory according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

In order to facilitate understanding of the reading method provided by the embodiment of the present application, a specific application scenario of the embodiment of the present application is first introduced. Nonvolatile memory includes a plurality of memory cells arranged in an array for storing data. The storage unit is divided into several blocks, and each block is further divided into several pages, and operations such as reading, writing, verifying, and clearing the non-volatile memory can be performed in units of pages.

Non-volatile memory includes memory cell array, control logic, page buffer (PB), word line voltage generator and word line decoder. Each column of memory cells in the memory cell array passes through a bit line (Bit line). Line, BL) is connected to the page buffer, and the gate of each row of memory cells is connected to the word line decoder through a word line (Word Line, WL). The control logic controls word line voltage generators and page buffers. During the read operation, the control logic applies the read voltage to the selected word line by controlling the word line voltage generator, and after applying the read pass voltage to the unselected word line, the control logic controls the page buffer according to different read operations. The method senses the data stored in the storage unit on the corresponding bit line, so as to read out the data stored in the non-volatile memory.

Non-volatile memory is mainly divided into SLC (Single-Level Cell), MLC (Milti-Level Cell), TLC (Trinary-Level Cell), QLC (Quad-Level Cell) and other types, SLC is 1bit/cell, Each memory cell stores 1-bit data, and the memory cell has only two storage states: "0" and "1". MLC, ie 2bit/cell, each storage unit stores 2-bit data, and the storage unit has four storage states: "00", "01", "10", "11". TLC, that is, 3bit/cell, each storage unit stores 3 bits of data, and the storage unit has eight storage states: "000", "001", "010", "011", "100", "101", "110" ", "111". It is understood that the memory cells of the non-volatile memory can also store more than 3 bits of data. QLC, that is, 4bit/cell, each storage unit stores 4-bit data, and the storage unit has 16 storage states: "0000", "0001", "0010", "0011", "0100", "0101", "0110" ", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111".

In order to determine the storage state of the memory cell, so as to read out the stored data, for the SLC type non-volatile memory, a read operation is performed on the selected word line and a read voltage is applied on the word line. The data stored in the corresponding storage unit can be read out. However, for non-volatile memories such as MLC and TLC that store multiple bits of data per storage unit, since each storage unit has more than two storage states, it is necessary to perform multiple consecutive read operations on the same storage unit in the word After applying multiple read voltages of different magnitudes on the line, the stored data can be sensed, and then the actual storage state of the memory cell can be determined, and the data stored in the non-volatile memory can be read out.

However, in the process of data storage, when the data is stored in the flash memory for a period of time, the charge stored in the memory cells will leak, and the threshold voltage distribution in the flash memory will shift to the side with the smaller threshold voltage. When the read voltage used in the initial stage of data storage is used for the read operation, there will be a problem that the bit error rate of the read data will be high, even exceeding the error correction capability of the ECC.

The longest storage time corresponding to when the data can finally be correctly read after being stored is called the data retention time. How to extend the data retention time is an important research direction in this field. Data recovery technology refers to the technology of correct decoding by charging the cell with electrons to shift the threshold distribution to the right to reduce the error code to within the ECC error correction range, but ECC also has a certain error correction range. If the original bit error rate is high, the error correction capability of the error control coding will be exceeded, and the written data cannot be recovered correctly.

Referring to FIG. 2, it is a schematic diagram of a current data storage, the abscissa is the threshold voltage (threhold voltage), and the ordinate is the number of memory cells. The initial threshold voltage distribution state formed by the threshold voltage of the memory cell at zero time when data is written into the flash memory. The dotted line represents the threshold voltage distribution state of the flash memory after a period of storage time. It can be seen from the figure that after a period of storage time, Due to the leakage of the charge held by the memory cells, the threshold voltage distribution state of the flash memory is shifted to the side with the smaller threshold voltage, that is, the distribution state is shifted to the left. , Vread3 reads the flash memory, which will result in a higher bit error rate of the read data. It is very likely that the ECC check cannot be passed, and the correct stored data cannot be obtained.

Data retention error is the most important component of NAND Flash data error, which has the greatest impact on the reliability of NAND Flash. The longest storage time corresponding to when the data can finally be correctly read after storage is the data retention time. How to extend the data retention time? Retention time and reducing data retention errors are important research directions in this field.

When the bit error rate of the storage unit reaches a certain threshold, the data retention error is serious, and the data in the storage unit will be refreshed, and the data refresh operation of the memory will have a greater impact on the system performance of the memory. .

Data recovery technology refers to the technology of correct decoding by charging the cell with electrons to shift the threshold distribution to the right so as to reduce the error code to within the ECC error correction range. Schematic diagram of data recovery, the abscissa is the threshold voltage (Vth), the ordinate is the number of memory cells (Cell Count), and the curve distribution represents the initial threshold distribution (Initial Vth), the threshold distribution after the data retention time (After retention time) and the data The threshold value distribution after recovery (After data recovery), that is, after the data retention time has passed, the threshold voltage distribution state of the flash memory shifts to the side with the smaller threshold voltage, that is, the distribution state shifts to the left, and even the threshold voltage of some memory cells changes from The right side of the read voltage moves to the left side, causing the memory cell to read errors, and after data recovery, the threshold voltage can be shifted to the right, thereby reducing the bit error rate.

At present, two methods of reading voltage pulse and programming voltage pulse are used to charge the cell. These two methods have low charging efficiency, take a long time to charge, and cannot significantly reduce data retention errors.

Therefore, how to quickly and effectively reduce the data retention error of the three-dimensional memory, prolong the data storage time, and reduce the data refresh operation is a technical problem to be solved urgently in the art.

Based on the above technical problems, the present application provides a method and device for reducing the data refresh operation of a three-dimensional memory. When it is detected that the bit error rate of the data in the storage block is greater than or equal to the first preset threshold, the storage block is used as the target Memory block, determine the target memory layer located in the target memory block, perform data refresh on the adjacent layer of the target memory layer, and apply a programming voltage to the memory page of the adjacent layer of the target memory layer, so as to utilize the word line crosstalk effect to the target memory layer. The memory page in the layer injects electrons, and the programming voltage makes the threshold voltage of the memory page of the adjacent layer higher than the highest threshold voltage of the memory page of the memory, when it is detected that the bit error rate of the data in the target memory layer is greater than or equal to the first pre- When the threshold is set, data refresh is performed on the target storage tier. That is, through the word line crosstalk effect of adjacent layers on the target storage layer, the data storage time of the target storage layer is prolonged, the total data refresh times of the 3D memory are reduced, and the impact on the performance of the 3D memory due to data refresh is reduced.

Based on the above thought, in order to make the above objects, features and advantages of the present application more clearly understood, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

First of all, it should be noted that the method, device and related equipment for reading non-volatile memory provided by the embodiments of this application are not only applicable to NAND flash memory (3D, MLC, TLC, QLC), but also to magnetoresistive memory (Magnetoresistive Random Access Memory, MRAM), phase-change memory (Phase-Change RandomAccess Memory, PCRAM), phase-change memory and switch (Phase-Change Random Access Memory and aswitch, PCMS), resistive memory, ferroelectric RAM (ferroelectric RAM) , FRAM), spin transfer torque memory (Spin Torque Transfer, STT), thermally assisted switching memory (TAS), millipede memory (Millipede memory), floating junction gate memory (FJG RAM), battery backup RAM and other non-easy volatile memory. Each memory cell in the non-volatile memory can store 3 bits or more of data.

Exemplary method

Referring to FIG. 4 , which is a flowchart of a method for reducing a data refresh operation of a three-dimensional memory provided by an embodiment of the present application, the method may include:

S101, when it is detected that the bit error rate of data in a storage block is greater than or equal to a first preset threshold, use the storage block as a target storage block.

In a memory, generally speaking, in a block, the gates of the memory cells of each layer are connected to a word line decoder through a word line to form a page. In this embodiment of the present application, the memory may be one of 3D, MLC, TLC, and QLC, and its memory cells have multiple threshold voltage distribution states.

When it is detected that the bit error rate of the data in the storage block has been greater than or equal to the first preset threshold, it means that the bit error rate of the storage pages in the storage block has reached the data refresh threshold, and a data refresh operation needs to be performed. The storage block is used as the target storage block to perform subsequent data refresh operations. It should be noted that the first preset threshold may have different settings according to different storage blocks. The embodiment of the present application is not specifically limited here, and can be determined by those skilled in the art. Set according to the actual situation.

S102: Determine the target storage layer located in the target storage block.

In this embodiment of the present application, the target storage layer may include a single layer or multiple layers that are not adjacent. For example, the target storage layer may include the second layer, or both the first layer and the third layer.

Specifically, the target storage unit located in the target storage layer can be determined as the storage unit that needs to be injected with electrons. Specifically, the target storage unit can be all storage units in the target storage layer. to charge.

Optionally, the target storage unit may also be a partial storage unit of the target storage layer, and to determine the target storage unit located in the target storage layer, the target storage unit needs to be obtained by screening all storage units of the target storage layer. This is because the memory cells of the target memory layer usually have multiple threshold voltage distribution states. Generally speaking, the electron loss in the low threshold voltage distribution state is slower, and the electron loss in the high threshold voltage distribution state is faster. The left shift of the voltage distribution state is serious. When charging is required, the left shift of the low threshold voltage distribution state is not obvious, and no charging is required. Therefore, it is necessary to select a memory cell with a higher threshold voltage from the memory cells of the target memory layer as the target memory cell. .

In specific implementation, at least one read voltage may be used to perform a read operation on the memory cells located in the target storage layer to determine the voltage range where the threshold voltage of each memory cell is located, and the voltage range where the determined threshold voltage is located is defined by at least one read voltage. , the read voltage may include at least the first read voltage, and of course, may also include other read voltages, or may not include other read voltages. Afterwards, each memory cell can be grouped according to the voltage range in which the threshold voltage of each memory cell is located, and the memory cells in the grouping whose threshold voltages are all greater than the first read voltage are used as target memory cells, and there is a threshold voltage lower than the first read voltage. Memory cells in groups of voltages act as program inhibit cells. Wherein, as an example, the number of read voltages can be 1, 2, 3, 4 or 5, the defined voltage range can be 2, 3, 4, 5 or 6 correspondingly, and the corresponding number of groups can be 2, 3, 4, 5 or 6.

Referring to FIG. 5 , which is a schematic diagram of determining a target memory cell provided by an embodiment of the present application, a TLC NAND flash memory device includes a threshold voltage distribution state of (E, P1, P2, . . . , P7), using P2 and P3 The first read voltage V1 between, and the second read voltage V2 between P5 and P6 perform a read operation on the memory cells of the target memory layer, which define a value smaller than the first read voltage V1, the first read voltage V1 and the second read voltage V2. Among the three voltage ranges between the read voltage V2 and greater than the second read voltage V2, the threshold voltage distribution states of the memory cells belonging to the voltage range less than the first read voltage V1 include E, P1, and P2, which are encoded as "000", the threshold voltage distribution of the memory cells between the first read voltage V1 and the second read voltage V2 includes P3, P4, and P5, which are coded as "010" after reading, which belongs to greater than the second read voltage The threshold voltage distribution states of the memory cells in the voltage range of V2 include P6 and P7, which are coded as "100" after being read. The above read result can be stored in the page buffer.

Afterwards, each storage unit is grouped, and the grouping manner may be different according to the storage unit of the target storage layer being one or more layers.

Specifically, when the target memory layer is one layer, the memory cells belonging to the same voltage range can be regarded as the same group, then the first group can include memory cells whose threshold voltage distribution states are E, P1, and P2, and the second group can include The memory cells whose threshold voltage distribution states are P3, P4, and P5, the third group may include memory cells whose threshold voltage distribution states are P6 and P7, and grouping (the second group and the third group) whose threshold voltage is greater than the first read voltage The memory cells in the 1 are used as the target memory cells, and the memory cells in the group (the first group) whose threshold value is less than the first read voltage are used as the program suppression cells, wherein the target memory cells are the memory cells that need to be charged, and the program suppression cells are not required. For the charged memory cells, program inhibition (Program Inhibit) is performed on the program inhibition cells in the subsequent reprogramming process.

Specifically, when the target layer is a multi-layer, the multi-layer memory cells are connected in series by using other layers in the middle, and the other layers are the common adjacent layers of the multi-layer target layer, which are also used as subsequent programming layers, and the memory cells are grouped. When , the two memory cells connected to the same memory cell of the programming layer can be comprehensively considered, and the memory cell with the lower threshold voltage in the two memory cells can be used as the reference cell. The reference cells in the same voltage range are regarded as the same group, each reference cell is grouped, and the memory cells of the two target layers connected to the same memory cell of the programming layer belong to the same group. For example, the threshold voltage distribution states of the memory cells of the two target layers connected to the same memory cell of the programming layer are E and P7 respectively, then both belong to the first group, and the corresponding threshold voltage range of the first group is less than the first group. Read voltage V1.

After that, the target storage unit can be determined according to the grouping situation, each storage unit is grouped, the storage unit in the group whose threshold voltage is greater than the first read voltage is used as the target storage unit, and the storage unit in the group whose threshold voltage is less than the first read voltage The memory cells act as program inhibit cells. That is to say, in the same group, if there are two memory cells with threshold voltage distribution states, the threshold voltage division distribution state with the smaller threshold voltage determines whether these two memory cells are target memory cells, for example, the same as the programming layer. The threshold voltage distribution states of the memory cells of the two target layers connected to the same memory cell are E and P7 respectively, then the grouping of the two memory cells is a group with a threshold value less than the first read voltage, then the two memory cells are programmed Suppression unit.

S103: Refresh the data of the adjacent layers of the target storage layer, store the refreshed data in the first storage block, and mark the adjacent layers as invalid, so that the adjacent layers do not data is written again.

In the embodiment of the present application, since the bit error rate in the target storage block has reached the data refresh threshold, it is necessary to perform data refresh on the target storage block. In order to delay the data refresh operation on the storage page in the target storage layer, you can First perform a data refresh operation on an adjacent layer of the target storage layer, store the refreshed data in the first storage block, and mark the adjacent layer as invalid, so that data is no longer written to the adjacent layer. It is convenient to apply word line crosstalk to adjacent layers subsequently to reduce the bit error rate of the target storage layer, thereby delaying the data refresh operation of the storage page in the target storage layer.

Referring to Figure 6, for example, WL0 and WL2 can be used as target storage layers, and WL1 can be used as an adjacent layer, and data can be refreshed on WL1. After the data in WL1 is migrated to other storage blocks, the storage pages in WL1 are marked as invalid.

S104 : Apply a programming voltage to the memory pages of the adjacent layers of the target memory layer, so as to inject electrons into the memory pages in the target memory layer by using the word line crosstalk effect; the programming voltage makes the memory pages of the adjacent layers The threshold voltage of the page is higher than the highest threshold voltage of the storage page of the memory, the storage page of the adjacent layer and the storage page in the target storage layer are connected in series.

In the embodiments of the present application, the applicant has found through research that, when writing a page, the high voltage applied to the memory cells will interfere with the memory cells on adjacent word lines, and electrons are injected into these memory cells to make these memory cells. The threshold voltage of the memory cell rises, which is called the word line interference (WI) effect. In normal programming, the word line crosstalk effect is very weak. When the memory cell is programmed to a higher than normal threshold voltage, the word line The crosstalk effect changes significantly.

Referring to FIG. 7 , which is a schematic diagram of a word line crosstalk effect according to an embodiment of the present application, 7A indicates that in a plurality of memory cells, over-programming is performed on the n-th layer word line (WLn) (that is, the programming voltage is higher than normal threshold voltage), due to the word line crosstalk effect, its upper (n+1th layer) wordline (WLn+1) and lower (n-1th layer) wordline (WLn-1) will be disturbed and injected Therefore, the data retention time of the memory cells connected to WLn+1 and WLn-1 is prolonged, thereby reducing the bit error rate in the memory cells connected to WLn+1 and WLn-1.

7B, the abscissa is the threshold voltage (Vth) of the memory cell, and the ordinate is the number of memory cells (cell Count). The threshold voltage distribution state of the memory cells connected to 1 is shifted to the right. The greater the programming voltage of WLn, the greater the degree of right shift of the threshold voltage distribution state of the memory cells connected to WLn+1 and WLn-1. Therefore, by controlling the programming of WLn The voltage can control the injection of electrons.

Referring to FIG. 8 , which is a schematic diagram of programming of a memory cell provided in an embodiment of the present application, the page connected to WLn may be an empty page or an invalid page. When the page can be a blank page, the memory cells of this page are all in the E state, then the memory cells of this page can be programmed to a position higher than the programming voltage _VWI by using the programming voltage _VWI , as shown in FIG. When the connected page can be an _invalid page, and the memory cells of this page are in the E, _P1 , . Referring to Figure 8B.

Therefore, in this embodiment of the present application, a programming voltage can be applied to the memory pages of the adjacent layers of the target memory layer, so as to inject electrons into the memory pages in the target memory layer by using the word line crosstalk effect, and the programming voltage can make the memory pages of the adjacent layers The threshold voltage of the memory is higher than the highest threshold voltage of the storage page of the memory, and the storage page of the adjacent layer and the storage page in the target storage layer are connected in series.

Specifically, after the target memory cell of the memory page in the target memory layer is determined, a programming voltage can be applied to the programming cell in the adjacent layer of the target memory cell to inject electrons into the target memory cell by using the word line crosstalk effect, wherein the programming voltage makes the The programmed threshold voltage of the programming cell is higher than the highest threshold voltage of the memory cell of the memory, and the programming cell and the target memory cell are connected in series. Specifically, the programming voltage makes the programmed threshold voltage of the programming cell higher than the highest threshold voltage of the memory cell in the memory in a range of 5-5.9V. The target storage layer can be the upper layer of its adjacent layer, or the lower layer of its adjacent layer, or the upper layer and lower layer of its adjacent layer at the same time, and the adjacent layer of the target layer for applying the programming voltage is used as the programming layer. , applying a programming voltage to the programming layer can inject electrons into the target memory cells of the target memory layer, so as to reduce the bit error rate of the data in the target memory layer, prolong the storage time of the data, and reduce the data refresh operation.

In specific implementation, when the target storage layer is the upper layer and the lower layer of the adjacent layer, the target storage layer and the adjacent layer are three layers as a group, as shown in FIG. The upper and lower pageset 2 are used as the target storage layer. Since the target storage block has reached the data refresh threshold, data refresh needs to be performed. In order to prolong the storage time and reduce the total number of refreshes, a certain layer can be refreshed first. The layer page set 1 is refreshed and marked as invalid, so a programming voltage can be applied to page set 1 to inject electrons bidirectionally into page set 2 using the word line crosstalk effect, reducing the bit error rate in page set 2.

Referring to FIG. 10 , which is a schematic diagram of a bidirectional electron injection operation, the distribution states corresponding to the four memory cells in the upper target storage layer are E, P7, P3, and P4 in sequence, and the distribution states corresponding to the four memory cells in the lower target storage layer are in turn: For P7, P3, P1, and P3, the required programming voltage needs to be determined according to the grouping of the memory cells of the two target memory layers. In actual operation, when two target memory cells connected in series with the same programming cell belong to different groups, use The grouping of target memory cells with lower threshold voltages prevails. For example, the threshold voltage distribution states of two target memory cells connected in series with the same programming unit are E and P7, then the read results of these two target memory cells are stored as "000" in the page buffer, belonging to the first group; and The threshold voltage distribution states of the two target memory cells connected in series with the same programming unit are P3 and P7, then the read results of the two target memory cells are stored as "010" in the page buffer, belonging to the second group; The threshold voltage distribution states of the two target memory cells connected in series are P3 and P1, then the read results of the two target memory cells are stored as "000" in the page buffer, belonging to the first group; they are connected in series with the same programming cell The threshold voltage distribution states of the two target memory cells are P3 and P4, then the read results of the two target memory cells are stored as "010" in the page buffer, belonging to the second group. Then, corresponding programming voltages may be applied to the connected programming cells according to the grouping of the two target memory cells.

In specific implementation, when the target storage layer is the upper layer or the lower layer of the adjacent layer, as shown in FIG. 11 , firstly take pageset 1 as the adjacent layer and page set 2 as the target storage layer, first perform data refresh on page set 1 and apply The programming voltage is used to reduce the bit error rate of the data in the adjacent page set 2 and page set 3 by using the word line crosstalk effect, and the bit error rate of the data in page set 2 and page set 3 is increased to the data refresh threshold again. When the data is refreshed on page set 2, a programming voltage is applied to the refreshed page set 2, so as to utilize word line crosstalk effect to inject electrons into page set 3 unidirectionally, thereby reducing the bit error rate of data in page set 3.

That is, page set 2 receives one word line crosstalk effect, page set 3 receives word line crosstalk effect twice, the storage time is further extended, and the total number of data refreshes is reduced.

Referring to Figure 12, which is a schematic diagram of a one-way electron injection operation, the distribution states corresponding to the four memory cells of the target storage layer (Target WL) are E, P2, P7, and P4 in sequence, and the read results are "000", "000", "100", and "010" are stored in the page buffer (Page Buffer), so they belong to the first group, the first group, the third group, and the second group respectively, then the first two of the four storage units One is the programming inhibition unit, which is programmed to inhibit (Program Inhibit), the latter two are target memory cells, and the four memory cells of the programming layer (Aggressor WL) are connected in series with the four memory cells of the target layer, respectively. The programming unit connected to the target storage unit can realize the data recovery of the target storage. Specifically, the second programming voltage V _H (Program To V _H ) can be applied to the third storage unit of the programming layer, and the fourth storage unit can be applied to the fourth storage unit. A programming voltage (Program To _VM ).

S105: When it is detected that the bit error rate of the data in the target storage layer is greater than or equal to a first preset threshold, perform data refresh on the target storage layer.

Referring to FIG. 9, when the bit error rate of the data in the target storage layer page set 2 is greater than or equal to the first preset threshold, data refresh is performed on the target storage layer page set 2, that is, the word line crosstalk effect is used to enable The target storage layer page set 2 stores data for a longer time before refreshing the data, so that the total refresh operation is reduced.

Referring to Figure 11, page set 2 only performs data refresh after receiving one word line crosstalk effect, and page set 3 receives word line crosstalk effect twice before performing data refresh, the storage time is further extended, and the total number of data refreshes is reduced.

The present application provides a method for reducing the data refresh operation of a three-dimensional memory. When it is detected that the bit error rate of data in a storage block is greater than or equal to a first preset threshold, the storage block is used as a target storage block, and it is determined that the storage block is located in the target storage block. In the target storage layer in the block, data refresh is performed on the adjacent layers of the target storage layer, and a programming voltage is applied to the storage pages of the adjacent layers of the target storage layer, so as to utilize the word line crosstalk effect to inject electrons into the storage pages in the target storage layer. , the programming voltage makes the threshold voltage of the storage page of the adjacent layer higher than the highest threshold voltage of the storage page of the memory, when it is detected that the bit error rate of the data in the target storage layer is greater than or equal to the first preset threshold, the target memory layer for data refresh. That is, through the word line crosstalk effect of adjacent layers on the target storage layer, the data storage time of the target storage layer is prolonged, the total data refresh times of the 3D memory are reduced, and the impact on the performance of the 3D memory due to data refresh is reduced.

Exemplary device

Referring to FIG. 13 , a schematic diagram of an apparatus for reducing data refresh operations of a three-dimensional memory provided by an embodiment of the present application includes:

A target storage block determination unit 1301, configured to use the storage block as a target storage block when it is detected that the bit error rate of the data in the storage block is greater than or equal to a first preset threshold;

a target storage layer determining unit 1302, configured to determine a target storage layer located in the target storage block;

The adjacent layer data refresh unit 1303 is used to refresh the data of the adjacent layer of the target storage layer, store the refreshed data in the first storage block, and mark the adjacent layer as invalid, so that the adjacent layer is no longer written data;

The programming voltage applying unit 1304 is configured to apply a programming voltage to the memory pages of the adjacent layers of the target memory layer, so as to inject electrons into the memory pages in the target memory layer by utilizing the word line crosstalk effect; The threshold voltage of the storage page of the adjacent layer is higher than the highest threshold voltage of the storage page of the memory, and the storage page of the adjacent layer is connected in series with the storage page in the target storage layer;

The target storage layer data refresh unit 1305 is configured to perform data refresh on the target storage layer when it is detected that the bit error rate of the data in the target storage layer is greater than or equal to a first preset threshold.

Optionally, the target storage layer is an upper layer and/or a lower layer of the adjacent layer.

Optionally, the device also includes:

a target storage unit determination unit, configured to determine a target storage unit located in the target storage layer;

A programming voltage applying subunit is used for applying a programming voltage to the programming cells in the adjacent layers of the target memory cell, so as to inject electrons into the target memory cell by using the word line crosstalk effect; the programming voltage makes the programming cell's The threshold voltage is higher than the highest threshold voltage of a memory cell of the memory, and the programming cell and the target memory cell are connected in series.

Optionally, the target storage unit determination unit includes:

a read unit, configured to perform a read operation on the memory cells located in the target layer by using at least one read voltage to determine a voltage range in which the threshold voltage of each of the memory cells is located; the voltage range is defined by the at least one read voltage, The read voltage includes at least a first read voltage;

a grouping unit, configured to group each of the memory cells according to the voltage range in which the threshold voltage of each of the memory cells is located;

The target storage unit determination subunit is used to use the storage cells in the groups whose threshold voltages are all greater than the first read voltage as the target storage cells, and use the storage cells in the groups whose threshold voltages are less than the first read voltage as the programming Suppression unit.

Optionally, the grouping unit is used for:

When the target storage layer is an upper layer or a lower layer of the adjacent layer, the grouping each of the memory cells according to the voltage range in which the threshold voltage of each of the memory cells is located includes: grouping the memory cells located in the same voltage range The described storage units are regarded as the same group, and each of the described storage units is grouped;

and / or,

When the target storage layer is the upper layer and the lower layer of the adjacent layers, the grouping each of the memory cells according to the voltage range in which the threshold voltage of each of the memory cells is located includes: grouping the memory cells with the corresponding memory cells. Among the memory cells of the two target layers connected to the same memory cell of the adjacent layer, the memory cell with a low threshold voltage is used as the reference cell, and the reference cells located in the same voltage range are regarded as the same group, and each of the reference cells is grouped, And let the memory cells of the two target layers connected to the same memory cell of the adjacent layer belong to the same group.

The present application provides a device for reducing data refresh operations of a three-dimensional memory. When it is detected that the bit error rate of data in a storage block is greater than or equal to a first preset threshold, the storage block is used as a target storage block, and it is determined that the storage block is located in the target storage block. In the target storage layer in the block, data refresh is performed on the adjacent layers of the target storage layer, and a programming voltage is applied to the storage pages of the adjacent layers of the target storage layer, so as to utilize the word line crosstalk effect to inject electrons into the storage pages in the target storage layer. , the programming voltage makes the threshold voltage of the storage page of the adjacent layer higher than the highest threshold voltage of the storage page of the memory, when it is detected that the bit error rate of the data in the target storage layer is greater than or equal to the first preset threshold, the target memory layer for data refresh. That is, through the word line crosstalk effect of adjacent layers on the target storage layer, the data storage time of the target storage layer is prolonged, the total data refresh times of the 3D memory are reduced, and the impact on the performance of the 3D memory due to data refresh is reduced.

Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for related parts, please refer to the partial descriptions of the method embodiments.

The above descriptions are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art, without departing from the scope of the technical solution of the present application, can use the methods and technical contents disclosed above to make many possible changes and modifications to the technical solution of the present application, or be modified into equivalents of equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solutions of the present application still fall within the protection scope of the technical solutions of the present application.

Claims (10)

1. A method of reducing data refresh operations of a three-dimensional memory, comprising:

when the error rate of data in a storage block is detected to be larger than or equal to a first preset threshold value, taking the storage block as a target storage block;

determining a target storage layer located in a target storage block;

performing data refreshing on an adjacent layer of the target storage layer, storing the refreshed data into a first storage block, and marking the adjacent layer as invalid so that the adjacent layer is not written with data any more;

applying a programming voltage to a memory page of an adjacent layer of the target memory layer to inject electrons to the memory page in the target memory layer by using a word line crosstalk effect; the programming voltage enables the threshold voltage of the storage page of the adjacent layer to be higher than the highest threshold voltage of the storage page of the memory, and the storage page of the adjacent layer and the storage page in the target storage layer are connected in series;

and when detecting that the error rate of the data in the target storage layer is greater than or equal to a first preset threshold value, refreshing the data of the target storage layer.

2. The method of claim 1, wherein the target storage layer is an upper layer and/or a lower layer of the adjacent layers.

3. The method of claim 2, further comprising:

determining a target storage unit located in the target storage tier;

applying a programming voltage to a programming cell of an adjacent layer of the target memory cell to inject electrons to the target memory cell by using a word line crosstalk effect; the program voltage causes a threshold voltage of the program cell to be higher than a highest threshold voltage of memory cells of the memory, the program cell and the target memory cell being connected in series.

4. The method of claim 3, wherein determining the target storage unit located in the target storage tier comprises:

performing read operation on the storage units positioned in the target storage layer by using at least one read voltage so as to determine the voltage range of the threshold voltage of each storage unit; the voltage range is defined by the at least one read voltage, the read voltage comprising at least a first read voltage;

grouping the storage units according to the voltage range of the threshold voltage of each storage unit;

and taking the memory cells in the groups with the threshold voltages larger than the first reading voltage as target memory cells, and taking the memory cells in the groups with the threshold voltages smaller than the first reading voltage as program inhibiting cells.

5. The method of claim 4, wherein when the target storage layer is an upper layer or a lower layer of the adjacent layers, the grouping the memory cells according to the voltage range in which the threshold voltage of each memory cell is located comprises: the memory units in the same voltage range are used as the same group, and all the memory units are grouped;

and/or the presence of a gas in the gas,

when the target storage layer is an upper layer and a lower layer of the adjacent layers, grouping the memory cells according to voltage ranges in which the threshold voltages of the memory cells are located, including: and grouping the reference units by taking the memory units with low threshold voltage in the memory units of the two target layers connected with the same memory unit of the adjacent layer as reference units and taking the reference units in the same voltage range as a same group, wherein the memory units of the two target layers connected with the same memory unit of the adjacent layer belong to the same group.

6. An apparatus for reducing data refresh operations for a three dimensional memory, comprising:

the target storage block determining unit is used for taking the storage block as a target storage block when the error rate of the data in the storage block is detected to be greater than or equal to a first preset threshold value;

a target storage layer determining unit for determining a target storage layer located in a target storage block;

the adjacent layer data refreshing unit is used for refreshing the adjacent layer of the target storage layer, storing the refreshed data into a first storage block, and marking the adjacent layer as invalid so that the adjacent layer is not written with data any more;

a program voltage applying unit for applying a program voltage to a memory page of an adjacent layer of the target memory layer to inject electrons to the memory page within the target memory layer using a word line crosstalk effect; the programming voltage enables the threshold voltage of the storage page of the adjacent layer to be higher than the highest threshold voltage of the storage page of the memory, and the storage page of the adjacent layer and the storage page in the target storage layer are connected in series;

and the target storage layer data refreshing unit is used for refreshing the data of the target storage layer when detecting that the error rate of the data in the target storage layer is greater than or equal to a first preset threshold value.

7. The apparatus of claim 6, wherein the target storage layer is an upper layer and/or a lower layer of the adjacent layers.

8. The apparatus of claim 7, further comprising:

a target storage unit determination unit configured to determine a target storage unit located in the target storage layer;

a program voltage applying sub-unit for applying a program voltage to a program cell of an adjacent layer of the target memory cell to inject electrons to the target memory cell using a word line crosstalk effect; the program voltage causes a threshold voltage of the program cell to be higher than a highest threshold voltage of memory cells of the memory, the program cell and the target memory cell being connected in series.

9. The apparatus of claim 8, wherein the target storage unit determining unit comprises:

the reading unit is used for reading the storage units positioned on the target layer by utilizing at least one reading voltage so as to determine the voltage range of the threshold voltage of each storage unit; the voltage range is defined by the at least one read voltage, the read voltage comprising at least a first read voltage;

the grouping unit is used for grouping the storage units according to the voltage range of the threshold voltage of each storage unit;

and the target storage unit determining subunit is used for taking the storage units in the groups with the threshold voltages larger than the first reading voltage as target storage units and taking the storage units in the groups with the threshold voltages smaller than the first reading voltage as program inhibiting units.

10. The apparatus of claim 9, wherein the grouping unit is configured to:

when the target storage layer is an upper layer or a lower layer of the adjacent layers, grouping the memory cells according to the voltage range in which the threshold voltage of each memory cell is located, including: the memory units in the same voltage range are used as the same group, and all the memory units are grouped;

and/or the presence of a gas in the atmosphere,

when the target storage layer is an upper layer and a lower layer of the adjacent layers, grouping the storage units according to the voltage range in which the threshold voltage of each storage unit is located, including: and taking the memory cells with low threshold voltage in the memory cells of the two target layers connected with the same memory cell of the adjacent layer as reference cells, taking the reference cells in the same voltage range as the same group, grouping the reference cells, and enabling the memory cells of the two target layers connected with the same memory cell of the adjacent layer to belong to the same group.

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