CN113220240B - Non-volatile memory chips - Google Patents
Non-volatile memory chips Download PDFInfo
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- CN113220240B CN113220240B CN202110578244.8A CN202110578244A CN113220240B CN 113220240 B CN113220240 B CN 113220240B CN 202110578244 A CN202110578244 A CN 202110578244A CN 113220240 B CN113220240 B CN 113220240B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0622—Securing storage systems in relation to access
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses a nonvolatile memory chip, which comprises a timing circuit, a read-write control circuit and a memory array; the memory array includes a primary memory region; the main memory area is used for storing conventional data; the timing circuit starts timing when the nonvolatile memory chip leaves the factory, and when the timing time length reaches the set time length, the chip life expiration signal is output to the read-write control circuit; when receiving the chip life expiration signal from the timing circuit, the read-write control circuit reads out and stores the data in the main memory area, then erases the main memory area, and rewrites the data read out and stored in the main memory area into the main memory area. The nonvolatile memory chip can effectively prolong the data storage life of the nonvolatile memory chip, improve the data security and save the chip cost.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a nonvolatile memory chip.
Background
Conventional semiconductor nonvolatile memory is typically comprised of charge storage cells, which are MOSFETs having a layer of charge storage material under a control gate and over a MOSFET channel, and access Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The amount of charge in the charge storage material may affect a threshold voltage applied to the control gate to turn on the channel of the MOSFET memory cell. The threshold voltage of an N-type semiconductor memory cell is shifted to a higher voltage by storing electrons (negative charges) in the charge storage layer. However, the threshold voltage of the P-type semiconductor memory cell is shifted to a lower voltage by storing electrons (negative charges) in the charge storage layer. If the charge in the storage layer can be retained for a long period of time (typically greater than 10 years for a typical semiconductor nonvolatile memory), the semiconductor memory cell becomes nonvolatile. If the nonvolatile Memory element can perform multiple cycles of erase/program operations, the nonvolatile Memory is a multiple-program nonvolatile Memory (Multiple Times Programming Non-Volatile Memory, MTPNVM). Typically, for semiconductor nonvolatile memory, the number of erase/program cycles is between thousands and millions of times.
The nonvolatile memory stores data including erase operations and program operations. The erase operation typically includes 2 steps: pre-programming and erasing. The pre-programming programs the states of the memory cells to be erased in the memory to a weaker programmed state by a weaker programming operation, so that the initial states of the memory cells are relatively close. And the state of the memory cell to be erased is changed into the erased state by erasing. The programming operation typically includes 1 programming step to program the corresponding memory cell to a programmed state based on the data to be stored.
When reading data, a read voltage is generally applied to a word line and a bit line of a memory cell, a read current of the memory cell is sent to a read circuit through the bit line, the read circuit compares the magnitude of the memory cell current with a reference current generated in addition, and the state of the memory cell is judged according to the magnitude of the current. For example, the memory cell current is greater than the reference current, the memory cell is in an erased state, and the corresponding memory data is 1; the memory cell current is less than the reference current, the memory cell is in a programmed state, and the memory data is 0.
The extent to which the memory cells hold data can be affected by various factors. For example: operating voltage, temperature, number of erasures, data retention time, etc. Due to these factors, the difference between the current in the two states of the memory cell and the reference current may be reduced, and the margin for reading data may be reduced. When the difference between the memory cell current and the reference current is small, a risk of misreading may occur.
For the anti-aging problem inside the nonvolatile memory chip, the existing technologies are as follows:
1) The optimization design of a bidirectional interlocking memory cell (DICE);
2) 4 node memory cell design, etc.;
3) Various new structures proposed for a bidirectional interlocking memory cell (DICE) are to attenuate read disturb and half select disturb, etc., suffered by the bidirectional interlocking memory cell (DICE).
Disclosure of Invention
The invention aims to provide a nonvolatile memory chip, which can effectively prolong the data storage life of the nonvolatile memory chip, improve the data security and save the chip cost.
In order to solve the technical problems, the nonvolatile memory chip provided by the invention comprises a timing circuit, a read-write control circuit and a memory array;
The storage array includes a primary storage area;
The main memory area is used for storing conventional data;
the timing circuit starts timing when the nonvolatile memory chip leaves the factory, and outputs a chip life expiration signal to the read-write control circuit when the timing time reaches the set time;
and the read-write control circuit reads out and stores the data in the main storage area when receiving the chip life expiration signal sent by the timing circuit, then erases the main storage area, and rewrites the data read out and stored in the main storage area into the main storage area.
Preferably, the memory array further comprises a register memory area;
The register storage area is a readable and writable storage area and is used as a register for writing in a life extension flag bit, and the initial value of the life extension flag bit in the register storage area is 1;
The timing circuit starts timing when the nonvolatile memory chip leaves the factory, when the timing time length reaches the set time length, the chip life expiration signal is output to the read-write control circuit, the allowable timing times are reduced by 1 (n=n-1), the initial value of the allowable timing times (n) is a positive integer, the set time length is reduced, and timing is restarted; if the allowable number of times is greater than 0, the life extension flag position "1" is set, and if the allowable number of times is equal to 0, the life extension flag position "0" is set;
The read-write control circuit reads out and stores the data in the main storage area when receiving the chip life expiration signal sent by the timing circuit and if the life extension flag bit read from the register storage area is 1, then erases the main storage area, and rewrites the data read out and stored in the main storage area into the main storage area; if the life prolonging flag bit read from the register storage area is 0, outputting an alarm trigger signal to an alarm pin of the nonvolatile memory chip;
the alarm pin is used for being externally connected with an alarm circuit;
And the alarm circuit sends out alarm information when receiving the alarm trigger signal.
Preferably, the initial set time is 10 years;
the timing circuit outputs a chip life expiration signal every time and reduces the set time length by half a year;
the initial value of the allowable number of times (n) is 8, 9 or 10.
Preferably, the memory array further comprises a refresh storage area;
and the read-write control circuit reads out and stores the data in the main storage area into the refresh storage area when receiving the chip life expiration signal sent by the timing circuit, then erases the main storage area, and reads out and writes the data read out and stored in the main storage area from the refresh storage area into the main storage area.
Preferably, the read-write control circuit performs an erase operation on the refresh storage area when receiving the chip lifetime expiration signal from the timing circuit, then reads out and stores data in the main storage area into the refresh storage area, performs an erase operation on the main storage area, and then reads out and writes the data read out and stored in the main storage area from and into the refresh storage area.
Preferably, the nonvolatile memory is a flash memory.
The nonvolatile memory chip of the invention reads and stores the data in the main memory area after the set time, then erases the main memory area, rewrites the data read and stored in the main memory area into the main memory area, and re-collects the data by re-reading and writing the main memory area, thereby effectively prolonging the data storage life of the nonvolatile memory chip, improving the data security and saving the chip cost.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the following brief description of the drawings is given for the purpose of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without the need for inventive work for a person skilled in the art.
FIG. 1 is a schematic diagram of a nonvolatile memory chip according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 1, the nonvolatile memory chip comprises a timing circuit, a read-write control circuit and a memory array;
The storage array includes a primary storage area;
The main memory area is used for storing conventional data;
the timing circuit starts timing when the nonvolatile memory chip leaves the factory, and outputs a chip life expiration signal to the read-write control circuit when the timing time reaches the set time;
and the read-write control circuit reads out and stores the data in the main storage area when receiving the chip life expiration signal sent by the timing circuit, then erases the main storage area, and rewrites the data read out and stored in the main storage area into the main storage area.
In the nonvolatile memory chip of the first embodiment, after a set time, the nonvolatile memory chip reads and stores the data in the main memory area, then erases the main memory area, rewrites the data read and stored in the main memory area into the main memory area, and re-collects the data by re-reading and writing the main memory area, thereby effectively prolonging the data storage life of the nonvolatile memory chip, improving the data security and saving the chip cost.
Example two
The nonvolatile memory chip according to the first embodiment, wherein the memory array further includes a register storage area;
The register storage area is a readable and writable storage area and is used as a register for writing in a life extension flag bit, and the initial value of the life extension flag bit in the register storage area is 1;
The timing circuit starts timing when the nonvolatile memory chip leaves the factory, when the timing time length reaches the set time length, the chip life expiration signal is output to the read-write control circuit, the allowable timing times are reduced by 1 (n=n-1), the initial value of the allowable timing times (n) is a positive integer, the set time length is reduced, and timing is restarted; if the allowable number of times is greater than 0, the life extension flag position "1" is set, and if the allowable number of times is equal to 0, the life extension flag position "0" is set;
The read-write control circuit reads out and stores the data in the main storage area when receiving the chip life expiration signal sent by the timing circuit and if the life extension flag bit is 1, then erases the main storage area, and rewrites the data read out and stored in the main storage area into the main storage area; if the life extension flag bit is 0, outputting an alarm trigger signal to an alarm pin of the nonvolatile memory chip;
the alarm pin is used for being externally connected with an alarm circuit;
And the alarm circuit sends out alarm information when receiving the alarm trigger signal.
Preferably, the initial set time is 10 years;
the timing circuit outputs a chip life expiration signal every time and reduces the set time length by half a year;
the initial value of the allowable number of times (n) is 8, 9 or 10.
The nonvolatile memory chip of the second embodiment can automatically read and write the stored data in the main memory area for multiple rounds so as to achieve the purpose of prolonging the service life of the memory chip; the read-write control circuit determines whether to read and write the stored data in the main storage area for a new round according to the state of the life extension flag bit in the register storage area so as to prolong the life of the memory chip; if the state of the life extension flag bit in the register storage area is 0, the life of the memory chip is not required to be prolonged (the life of the memory chip is expired), an alarm trigger signal is output to an external alarm circuit, the alarm circuit is triggered to send alarm information, and the alarm is continued until human intervention.
Example III
Based on the nonvolatile memory chip of the first embodiment, the memory array further includes a refresh storage area;
and the read-write control circuit reads out and stores the data in the main storage area into the refresh storage area when receiving the chip life expiration signal sent by the timing circuit, then erases the main storage area, and reads out and writes the data read out and stored in the main storage area from the refresh storage area into the main storage area.
Preferably, the read-write control circuit performs an erase operation on the refresh storage area when receiving the chip lifetime expiration signal from the timing circuit, then reads out and stores data in the main storage area into the refresh storage area, performs an erase operation on the main storage area, and then reads out and writes the data read out and stored in the main storage area from and into the refresh storage area.
Preferably, the nonvolatile memory is a flash memory.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.
Claims (6)
1. The nonvolatile memory chip is characterized by comprising a timing circuit, a read-write control circuit and a memory array;
the storage array comprises a main storage area and a register storage area;
The main memory area is used for storing conventional data;
The register storage area is a readable and writable storage area and is used as a register for writing in a life extension flag bit, and the initial value of the life extension flag bit in the register storage area is 1;
the timing circuit starts timing when the nonvolatile memory chip leaves the factory, when the timing time length reaches the set time length, the chip life expiration signal is output to the read-write control circuit, the allowed timing times are reduced by 1, the initial value of the allowed timing times is a positive integer, the set time length is reduced, and timing is restarted; if the allowable number of times is greater than 0, the life extension flag position "1" is set, and if the allowable number of times is equal to 0, the life extension flag position "0" is set;
the read-write control circuit reads out and stores the data in the main storage area when receiving the chip life expiration signal sent by the timing circuit and if the life extension flag bit is 1, then erases the main storage area, and rewrites the data read out and stored in the main storage area into the main storage area; if the life extension flag bit is '0', an alarm trigger signal is output to an alarm pin of the nonvolatile memory chip.
2. The non-volatile memory chip of claim 1, wherein the memory chip,
The alarm pin is used for being externally connected with an alarm circuit;
And the alarm circuit sends out alarm information when receiving the alarm trigger signal.
3. The non-volatile memory chip of claim 1, wherein the memory chip,
The initial setting time is 10 years;
the timing circuit outputs a chip life expiration signal every time and reduces the set time length by half a year;
the initial value of the allowed times is 8, 9 or 10.
4. The non-volatile memory chip of claim 1, wherein the memory chip,
The memory array further includes a refresh storage area;
and the read-write control circuit reads out and stores the data in the main storage area into the refresh storage area when receiving the chip life expiration signal sent by the timing circuit, then erases the main storage area, and reads out and writes the data read out and stored in the main storage area from the refresh storage area into the main storage area.
5. The non-volatile memory chip of claim 4, wherein the memory chip comprises a memory chip,
And the read-write control circuit is used for firstly performing erasing operation on the refresh storage area when receiving the chip life expiration signal sent by the timing circuit, then reading out and storing the data in the main storage area into the refresh storage area, then performing erasing operation on the main storage area, and then reading out and writing the data read out and stored in the main storage area into the main storage area from the refresh storage area.
6. The non-volatile memory chip of any one of claims 1 to 5, wherein the non-volatile memory is a flash memory.
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| CN202110578244.8A CN113220240B (en) | 2021-05-26 | 2021-05-26 | Non-volatile memory chips |
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| CN202110578244.8A CN113220240B (en) | 2021-05-26 | 2021-05-26 | Non-volatile memory chips |
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| US6249838B1 (en) * | 1998-12-28 | 2001-06-19 | Cisco Technology Inc. | Physical medium information in file system header |
| JP2002208287A (en) * | 2001-01-12 | 2002-07-26 | Sanyo Electric Co Ltd | Non-volatile semiconductor memory |
| US7065607B2 (en) * | 2002-06-28 | 2006-06-20 | Microsoft Corporation | System and method for implementing a counter |
| US7447944B2 (en) * | 2005-04-29 | 2008-11-04 | Freescale Semiconductor, Inc. | Predictive methods and apparatus for non-volatile memory |
| US7921340B2 (en) * | 2006-01-20 | 2011-04-05 | Panasonic Corporation | Nonvolatile memory device, nonvolatile memory system, and defect management method for nonvolatile memory device |
| JP5134255B2 (en) * | 2007-01-30 | 2013-01-30 | 富士通株式会社 | Data recording system |
| US8055835B2 (en) * | 2008-06-23 | 2011-11-08 | International Business Machines Corporation | Apparatus, system, and method for migrating wear spots |
| CN103513930A (en) * | 2012-06-20 | 2014-01-15 | 群联电子股份有限公司 | Memory management method, memory controller and memory storage device |
| JP6107802B2 (en) * | 2014-12-15 | 2017-04-05 | コニカミノルタ株式会社 | Nonvolatile memory control device, nonvolatile memory control method, and program |
| JP6541369B2 (en) * | 2015-02-24 | 2019-07-10 | キヤノン株式会社 | Data processing apparatus for processing data in memory, data processing method, and program |
| JP6814107B2 (en) * | 2017-08-02 | 2021-01-13 | ルネサスエレクトロニクス株式会社 | Semiconductor storage device and control method for semiconductor storage device |
| CN107797765B (en) * | 2017-09-26 | 2020-09-25 | 昆明理工大学 | Method for prolonging service life of electrically erasable storage element |
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