CN1131818A

CN1131818A - Method for manufacturing source/drain structure of fast electronically erasable programmable read-only memory

Info

Publication number: CN1131818A
Application number: CN95120269A
Authority: CN
Inventors: 理查德·威廉姆·格雷戈尔
Original assignee: AT&T Corp
Current assignee: AT&T Corp
Priority date: 1994-11-28
Filing date: 1995-11-27
Publication date: 1996-09-25
Also published as: TW337044B; DE19543089A1; JPH08222650A; KR960019758A

Abstract

The method involves etching a pn-junction section field oxide next to the pn-junction for its exposure. A further or drain-wash implantation is carried out to position the exposed section of the pn-boundary layer under the field oxide to remove the exposed section.In the mfr. of a source/drain arrangement a field oxide over part of the pn-junction is etched for the junction exposure. After a further or drain-wash implantation, a conductive layer is formed over a substrate part adjacent to the field oxide.

Description

Make the method for the source/drain structure of swift electron erasable programmable read-only memory

The present invention relates generally to semiconductor device, relate in particular to a kind of method of production source/leakage (" S/D ") structure in the quick EEP-ROM of CMOS.

Usually EEPROM (Electrically Erasable Programmable Read Only Memo) device (" EEPROMS ") is well-known.Along with increase day by day, be used to make these devices in the time of new manufacturing process and Manufacturing Technology Development to high density EEPROM device requirement.But these make variation, bring new problem again.

One is used for holding more that the new manufacturing technology of high-density device is to reduce ion implantation energy.Because thereby more small device size requires to inject the thickness that can reduce to allow to increase the EEP-ROM device density and reduce insulation and electric conducting material between the device area, when high-density device uses height to inject energy, just may destroy this thin isolated area, thereby cause the quality of device to descend or inefficacy.In addition, a kind of new manufacturing technology that is used for making highdensity EEPROM device is self calibration silicide (self-aligned silicide (Sali-cide)) technology.Generation, contact resistance and sheet resistance that the self calibration silicide technology is used for making the problem that high density EEPROM device increases with the contact resistance and the surface electrical wave arrestment in the source of preventing/leakage and grid region are to increase along with the reducing (for example, under high density case) of contact size of semiconductor device.The further information of relevant self calibration silicide technology, can consult the U.S. Patent number 5 that is entitled as " for self calibration silicide process and thereby the formation device that forms semiconductor device ", 001,082 and be entitled as that " be the U.S. Patent number 4 of the self calibration silicide process (technology) of the low sheet resistance that forms the doped silicon knot; 663; 191, these two patents will combine with for referencial use at this.

Ion in making high density EEPROM device inject can reduce produce leakage problem with the utilization of self calibration silicide at the source/drain junction of the CMOS technology EEPROM device that is embedded into.Therefore, needed is a kind of being used for to make the method for use self calibration silicide and so on technology that the EEPROM device can overcome the leakage problem of source/drain junction.But this method must not can cause such as the characteristic that reduces EEPROM and too high any undesirable side effects such as manufacturing cost.

For reaching above-mentioned requirements and purpose, as specifying, invented this method of the present invention at this according to the present invention.This method of the present invention has overcome the source/drain leakage problem in (or similar processing) EEPROM device of self calibration silication.The present invention includes one and carry out to leak and to wash the step that (drainwash) injects, so as the exposed portions of a PN junction to be positioned at a proximity oxide below, be convenient to eliminate this expose portion like this.The implementation leakage is washed this step and is preferably carried out after the oxide in this district is corroded.Carry out to leak and to wash this step and finish before being preferably in technologies such as carrying out the self calibration silicide.

As description of drawings, above-mentioned characteristic of the present invention and advantage will be more obvious after preferential embodiment of the present invention is more specifically illustrated, in addition:

Fig. 1 is a typical floating gate structural representation that is used for the EEPROM device;

Fig. 2 A is the schematic diagram of ion implantation step of the source/drain structure of an EEPROM device;

Fig. 2 B is the schematic diagram of the source/drain structure of an EEPROM device that has injected;

Fig. 2 C is the separator corrosion step schematic diagram of the source/drain structure of an EEPROM device;

Fig. 2 D is the schematic diagram of a field oxide that is corroded after the separator corrosion step of the source/drain structure of EEPROM device;

Fig. 2 E be an EEPROM device that is corroded the self calibration silication source/drain structure schematic diagram;

Fig. 3 A is that the step schematic diagram is washed in a leakage according to the source/drain structure that is corroded of EEPROM device of the present invention;

Fig. 3 B is the source of washing according to leaking of an EEPROM device of the present invention/drain structure schematic diagram;

Fig. 3 C be one according to the silication of self calibration of EEPROM device of the present invention, leak source/drain structure schematic diagram of washing and corroding.

A kind of preferential embodiment of the present invention will describe with reference to these schematic diagrames now, and among the figure, identical reference number is represented identical or basic similar elements.In these figures, the numeral of high order end is corresponding with the figure that uses this reference number first in each reference number.When concrete steps, configuration and layout are discussed, just can understand, this way is just for the purpose of description.This area the relevant technologies personnel will appreciate that, under the situation that does not break away from principle of the present invention and scope, other steps, configuration and layout also can be used.

Studying this method of the present invention is in order to overcome the leakage problem of the source/drain structure in EEPROM (Electrically Erasable Programmable Read Only Memo) (" EEPROM ") device.(for example change the EEPROM manufacturing process with the device density that adapts to increase, when using self calibration silication (Sali-cide ") technology, reduce ion implantation energy), the increase of device density with the EEP-ROM device wipe knot that electrode is connected around will produce electronics and leak.Therefore, remove the necessary voltage of this device difficulty that becomes for providing.

Fig. 1 is the typical grid structure of the EEPROM of narration separate gate.Though the discussion of face relates to this concrete structure, the people who is familiar with this semiconductor technology will appreciate that, the EEPROM device that also is applicable to other grid structures of use (for example stack gate EEPROM device) that this discussion relates to.This separate gate structure comprises a memory grid 102 and a floating grid 104.Tunnel oxide material 108 is located between floating gate 104 and the zone 106, a source (or leakage).District 106, source (or leakage) is placed in the silicon chip 107.With regard to described these the regional representative dimensions of Fig. 1, each size in these structures all depends on whole EEPROM device size.The material that comprises structural detail shown in Figure 1 should be conspicuous to the those of skill in the art of semiconductor technology.

The ion injection period of (or leakage) utmost point 106 in the source, injected beam 110 must be guided territory, polar region 106, this source (or leakage) as shown in Figure 1 into.Because the cause of this separate gate physical dimension, some injects, and ion can pass floating gate 104 and source (or leakage) distinguishes the thin channel oxide skin(coating) 108 between 106.This is to produce the penetrating of ion dose (dose) that sufficiently high electronics is annotated energy because this quite thin floating gate 104 can not stop.Therefore, when this injects energy and increases, the amount of ions of passing these grid 104 and therefore passing thin channel oxide skin(coating) 108 will increase.This ionic current can destroy this tunnel oxide 108.

Reduce ion exactly and inject energy for preventing to damage a step that thin tunnel oxide layers 108 can take.Inject energy by reducing ion, just can eliminate flow through this thin channel thin oxide layer 108 and the final electric current that destroys this thin layer of tunnel oxide.Ion inject can reduce also can help avoid destroy be configured between storage grid 102 and the floating grid 104 with and/or around storage grid 102 and floating grid 104 other quite thin oxides and/or nitride (not specifically illustrating) layer.But along with ion injects reducing of energy, the degree of depth in formed source below storage grid 102 and floating grid 104 (or leakage) district 106 also will reduce.Reducing these (source/or leak) 106 regional depths may make and itself have problems further making production period.This method of the present invention just is intended to solve these relevant issues.

As discussed above, can avoid destroying oxide 108 by reducing the ion injection, the degree of depth (or thickness) of the substrate area that is injected (for example, source/leakage 106) is reduced.When being used for the difficulty especially that reduces to become of when forming a metal layer above the substrate area that is injected (for example, production process in) the afterwards this degree of depth after the self calibration silicidation technique etc.

Table 1 narration generally is used for making the main technique step in source/leakage (" S/D ") district of EEPROM.

Table 1

Step 1 storage gate pattern forms

(maskless) injected in the leakage of step 2 light dope (utmost point)

(arsenic) is injected in step 3 source/leakage

Step 4 separator constitutes

The formation of step 5 self calibration silicide etc.

With reference to table 1 and Fig. 2, just can understand the formation of EEPROM source/leakage.Step 2 and 4 in the table 1 (not shown among Fig. 2) is the parts that are used for making the transistorized common process of CMOS outside the memory in the EEPROM device.The S/D of the arsenic in the step 3 of table 1 injects and narrates at Fig. 2 A.Shown in Fig. 2 A and 2B, S/D (source/leakage) injects and realizes by using a kind of arsenical amount (arsenic dose) 206 to mix, for example, (to call " p type " in the following text) forms a kind of n type conductance zone 208 (to call " n type " in the following text) on a kind of p type conductance substrate 202.The degree of depth in n type district 208 and this ion injected beam (ion notes) energy is proportional, and (near " beak " district 205) just reduces gradually near field oxide 204, and an implantation dosage commonly used that is used for forming n type district 208 in typical EEPROM device is approximately 3 * 10 ¹⁵Atom/cm ², energy is approximately 120 * 10 ³The energy of electron-volt (120keV).But as discussed above, along with reducing of device size, the arsenical amount is injected and can also must be reduced to avoid the destroyed (see figure 1) of tunnel oxide.An implantation dosage that typically is reduced that is used in high density EEPROM forming n type district 208 is about 3 * 10 ¹⁵Atom/centimetre ², and have about 60 * 10 ³The energy of electron-volt (60keV).Can be reduced to and be about 60keV from being about 120keV by injecting, will avoid destruction this tunnel oxide.But the degree of depth in n type district 208 equally also can reduce.

Next, Fig. 2 C and 2D are the results who is described in the 4th step in the table 1 of separator corrosion back display field oxide.Separator is the part in the leakage of the cited light dope of the 2nd step (" LDD ") structure, and this step is used for making the conventional cmos transistor beyond memory.During the excessive corrosion step in the separator corrosion process, field oxide will occur and reduce.Shown in Fig. 2 C, this corrosion step will reduce the height (from thickness 210 to thickness 212) of field oxide 204.With reference to Fig. 2 D, this corrosion step to act on beak district 205 obvious especially.Because inject energy owing to reduced ion, the degree of depth in this n type district 208 is reduced, and after the separator corrosion, the part 214 of the pn knot (202/208) in beak district 205 may be exposed to the open air.

Therefore, when to the 5th step (self calibration silication etc.) of this device execution list 1, a short circuit (zone) 218 may produce with PN junction (202/208) is parallel.This can just understand with reference to Fig. 2 E.In Fig. 2 E, self calibration silicification technics process etc. produce structure (for example, the Titanium silicide " TiSi of a metal level 216 near near the knot of the pn the field oxide 204 (202/208) ₂").Therefore, pn knot (202/208) part 214 that is exposed will be covered by a conductive metal layer.This just produce with pn knot (202/208) thus the path of current short circuit that parallel flow is crossed this pn knot.

For improving this short-circuit state, just develop method of the present invention.An embodiment of method of the present invention summarizes by the described processing step of table 2.

Table 2

Step 1 storage gate pattern forms

Step 2 LDD injects (maskless)

(arsenic) is injected in step 3 source/leakage

Step 4 separator constitutes

Step 5 is leaked and is washed injection

Formations such as step 6 self calibration silicide and so on

In one embodiment, the step of represented (and as Fig. 2 A～2D as described in) conventional production process in processing step 1～4 of the present invention and step 1～4 of table 1 is identical.The variation of this technology occurs in that " newly " step 5 in this step, was carried out a kind of leakage and washed implantation step before self calibration silication etc.It is that the n type district to PN junction (202/208) carries out doping again after contiguous field oxide 204 is corroded in essence that injection is washed in this leakage.Being noted that importantly that this leakage washes to be infused in does not need the step of adding in the manufacturing process.Or rather, injection is washed in this leakage can be by the subsequent technique at this device of manufacturing, after separator forms (as, step 4), during any suitable doping step, 208 exposures of n type district are realized, for simplifying whole discussion of the present invention, maskless technology in the time of will discussing or illustrate the processing semiconductor device.

A kind of mode of priority of washing injection of leaking can illustrate with reference to table 2 and Fig. 3.With reference to Fig. 3 A and 3B, this drain electrode implantation step is to finish by the method for carrying out a kind of arsenic (ion) injection after field oxide 204 is corroded.Though arsenic is used for this preferential embodiment, will understand that for the people who is proficient in this semiconductor technology any suitable n type implantation dosage (alloy) can substitute.The degree of depth that implantation step is further deepened the n type district 208 of pn knot (202/208) is washed in this leakage, makes this pn knot (202/208) part 214 that is exposed be advanced to a zone 304 below contiguous field oxide 204 like this.The dosage rate of implantation step is washed in this leakage can be about 1 * 10 ¹⁴Atom/centimetre ²With 1 * 10 ¹⁵Atom/centimetre ²Between.Relevant dosage (doping) energy may be about 20 * 10 ³Electronics-volt and 120 * 10 ³Between electronics-volt.The embodiment of implantation step of preferred dopant dose rate and energy wash to(for) this leakage are approximately 3 * 10 ¹⁵Atom/centimetre ³Energy is approximately 80 * 10 ³Electronics-volt (80keV).

With reference to step 6 and Fig. 3 C of table 2, as (the TiSi for example of formation self calibration silicide on pn knot (202/208) ₂) time just no longer includes and this capable current path that balances.This is because self calibration silicide 216 stops at field oxide 204 places of zone in 308 and impurity can not expand to pn knot (202/208) and is arranged in position 310 below the contiguous oxide 204.Therefore, by after corrosion field oxide 204, and before technologies such as self calibration silication, deepen the parallel short-circuit state that this pn knot is eliminated in n type district 208.

Though the present invention has been carried out at length representing and illustrating with reference to a kind of preferential embodiment of the present invention, can understand for the people who is proficient in this technology do not breaking away from the spirit and scope of the present invention, can do various changes to the present invention in form and details.

Claims

1. A method of avoiding an electrical short circuit of a pn junction of a substrate surface having a pn junction wherein a part of the pn junction is exposed by etching a field oxide located close to the pn junction, the method comprising performing a leak implantation step, so that the exposed portion of the pn junction is positioned under the field oxide to eliminate the exposed portion.

2. A method for manufacturing a source/drain structure in a semiconductor device comprising the steps of:

(1) providing a substrate;

(2) forming a pn junction on the substrate;

(3) forming a field oxide on the part of the pn junction;

(4) etching the field oxide, wherein the etching step exposes a portion of the pn junction adjacent to the substrate surface;

(5) performing a leak wash implant such that the exposed portion of the pn junction is below the field oxide to eliminate the surface exposure of the pn junction; and

(6) A conductive layer is formed on a portion of the substrate adjacent to said field oxide layer.

3. The method of claim 2, wherein step 5 is performed after said step 4.

4. A method of fabricating a source/drain structure in an electrically erasable programmable read only memory comprising the step of performing a drain wash implant to position an exposed portion of a pn junction under an adjacent field oxide so as to eliminate the exposed portion .

5. The method of claim 4, wherein the step of performing a leak implant further comprises the step of performing a leak implant after an adjacent oxide spacer layer is formed and etched.

6. The method of claim 4, wherein the step of performing a leak implant further comprises performing the step of leak implant before said source/drain structure is self-aligned silicided.

7. The method of claim 4, wherein the dopant dose rate at which the step of performing the leak wash implant is between about 1 x ¹⁰¹⁴ atoms/ ^cm2 and 1 x ¹⁰¹⁶ atoms/ ^cm2 .

8. The method of claim 4, wherein the impurity dose for performing the step of leak wash injection has an energy between about 20×10 ³ electron-volts and 120×10 ³ electron-volts.

9. The method of claim 4, wherein the dopant dose of performing the step of leak wash implantation is about 3×10 ¹⁵ atoms/cm ² with an energy of about 80×10 ³ electron-volts (80 keV).