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CN113126817B - Capacitance sensing circuit, related chip and touch device - Google Patents

Capacitance sensing circuit, related chip and touch device Download PDF

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Publication number
CN113126817B
CN113126817B CN202110268896.1A CN202110268896A CN113126817B CN 113126817 B CN113126817 B CN 113126817B CN 202110268896 A CN202110268896 A CN 202110268896A CN 113126817 B CN113126817 B CN 113126817B
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capacitance
coupled
switch
circuit
period
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CN113126817A (en
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黄思衡
王文祺
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Huiding Technology Private Ltd
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Huiding Technology Private Ltd
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Priority to CN202110268896.1A priority Critical patent/CN113126817B/en
Priority to PCT/CN2021/096743 priority patent/WO2022188276A1/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)

Abstract

The application discloses a capacitance sensing circuit, a related chip and a touch device. The capacitance sensing circuit comprises an input end, a charging circuit, a discharging time control circuit and a capacitance amplifying circuit. The input end is coupled with the capacitive element of the touch panel, and the capacitive element has an inherent capacitance value. The charging circuit provides an operating voltage to the input end in a first period so that the capacitive element is charged to the operating voltage. The discharge time control circuit controls the discharge circuit to discharge the capacitor in the discharge time. The capacitor amplifying circuit generates a sensing voltage according to the reference voltage and the voltage of the input end in a third period after the second period.

Description

Capacitance sensing circuit, related chip and touch device
Technical Field
The present application relates to a capacitive sensing circuit, and more particularly to a capacitive sensing circuit for touch detection.
Background
Fig. 1 is a schematic diagram of touch detection by using a capacitive sensing element CS 1. In fig. 1, the capacitive sensing element CS1 has a structure of a plate capacitor, wherein the upper plate E1 of the capacitive sensing element CS1 is disposed below the protection panel CP, so that when a finger or a conductive object approaches the capacitive sensing element CS1, the coupling capacitance of the finger or the object is coupled to the upper plate E1 of the capacitive sensing element CS1, and the lower plate E2 of the capacitive sensing element CS1 is grounded. For example, when a finger or a conductive object approaches the capacitive sensor CS1, a coupling capacitance C BK is generated between the upper plate E1 of the capacitive sensor CS1 and the finger, and the coupling capacitance C BK is connected in series with the human equivalent capacitance C BG to be grounded. That is, the capacitance sensing element CS1 is connected in parallel with the equivalent capacitance of the coupling capacitor C BK and the human body equivalent capacitance C BG connected in series. In this case, the sensed capacitance of the capacitive sensor CS1 is related to the coupling capacitance C BK and the human equivalent capacitance C BG connected in parallel to the capacitive sensor CS1 due to the proximity of the human body, in addition to the intrinsic capacitance C base. For example, the sensed capacitance C S of the capacitive sensor CS1 can be represented by equation (1).
C S＝Cbase +ΔC type (1)
In equation (1), Δc is the sensed capacitance variation of the capacitance sensor CS1 due to the approach of the human body, and according to the above description, the sensed capacitance variation Δc is equivalent to the capacitance value of the coupling capacitance C BK and the human body equivalent capacitance C BG connected in series.
Since the sensed capacitance C S of the capacitive sensing element CS1 changes when the human body approaches the capacitive sensing element CS1, it is possible to determine whether a touch event is generated on the touch panel according to the magnitude of the sensed capacitance change Δc. However, in a flexible touch screen, such as a Y-OCTA screen, the intrinsic capacitance C base of the capacitive sensing element is between about 200pF and 600pF, and the sensing capacitance change Δc due to the proximity of the human body is only about 300fF. The difference between the two is nearly thousand times, so when the sensing capacitance variation Δc is detected, if the intrinsic capacitance value C base and the sensing capacitance variation Δc are simultaneously sensed, even if the sensing result of the intrinsic capacitance value C base has only a small error, a significant error may be caused to the sensing result of the sensing capacitance variation Δc, so that the accuracy of touch detection is reduced. Therefore, how to reduce the influence of the inherent capacitance C base on the sensing result when detecting the capacitance variation Δc becomes a problem to be solved.
Disclosure of Invention
One of the objectives of the present application is to disclose a capacitive sensing circuit, a related chip and a touch device capable of reducing errors, so as to solve the above-mentioned problems.
An embodiment of the application provides a capacitive sensing circuit for generating a plurality of sensing voltages according to sensing capacitance variation amounts of a plurality of capacitive sensing elements of a touch panel. The capacitance sensing circuit comprises a first input end, a first charging circuit, a first discharging circuit and a first capacitance amplifying circuit. The first input end is coupled to a first capacitance sensing element of the touch panel, and the first capacitance sensing element has a first inherent capacitance value. The first charging circuit is coupled to an operating voltage for providing the operating voltage to the first input terminal in a first period of time so that the first capacitive sensing element is charged to the operating voltage. The first discharging circuit is coupled to the ground voltage for discharging the first capacitive sensing element. The discharge time control circuit is used for controlling the discharge time of the first discharge circuit to the first capacitance sensing piece in a second period after the first period. The first capacitance amplifying circuit is used for generating a first sensing voltage according to the reference voltage and the voltage of the first input end in a third period after the second period. The operating voltage is twice the reference voltage.
Another embodiment of the present application provides a chip including the capacitive sensing circuit.
Another embodiment of the present application provides a touch device including a capacitive sensing circuit, a touch panel, and a controller. The controller is used for judging touch events on the touch panel according to the sensing voltages.
The capacitance sensing circuit, the related chip and the touch device can enable the sensing capacitance piece to release preset electric quantity so as to reduce the influence of the inherent capacitance value of the sensing capacitance piece on the sensing voltage, so that the change of the sensing capacitance value caused by the approach of a human body can be more directly presented.
Drawings
FIG. 1 is a schematic diagram of touch detection using a capacitive sensing element.
Fig. 2 is a schematic diagram of a touch device according to an embodiment of the application.
FIG. 3 is a timing diagram of signals detected by the capacitive sensing circuit of FIG. 2.
Fig. 4 is a schematic diagram of a discharge time control circuit according to an embodiment of the application.
FIG. 5 is a schematic diagram of a capacitive sensing circuit according to another embodiment of the application.
FIG. 6 is a signal timing diagram of the capacitive sensing circuit of FIG. 5 when detecting.
Detailed Description
The following disclosure provides various embodiments or examples that can be used to implement the various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. It is to be understood that these descriptions are merely exemplary and are not intended to limit the present disclosure. For example, in the following description, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may include embodiments in which additional components are formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for brevity and clarity purposes and does not itself represent a relationship between the different embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "under," "below," "lower," "upper," and the like, may be used herein to facilitate a description of the relationship between one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be placed in other orientations (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally means that the actual value is within plus or minus 10%, 5%, 1% or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within an acceptable standard error of the average value, depending on the consideration of the person having ordinary skill in the art to which the present application pertains. It is to be understood that all ranges, amounts, values, and percentages used herein (e.g., to describe amounts of materials, lengths of time, temperatures, operating conditions, ratios of amounts, and the like) are modified by the word "about" unless otherwise specifically indicated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present specification and attached claims are approximations that may vary depending upon the desired properties. At least these numerical parameters should be construed as the number of significant digits and by applying ordinary rounding techniques. Herein, a numerical range is expressed as from one end point to another end point or between two end points; unless otherwise indicated, all numerical ranges recited herein include endpoints.
Fig. 2 is a schematic diagram of a touch device 10 according to an embodiment of the application. The touch device 10 may include a capacitive sensing circuit 100, a touch panel TP1, and a controller U1. The touch panel TP1 may include a plurality of capacitive sensing elements CS1 to CSN, and the capacitive sensing circuit 100 may be coupled to the capacitive sensing elements CS1 to CSN. The capacitive sensing elements CS1 to CSN may be disposed at different positions in the touch panel TP1, the capacitive sensing circuit 100 may generate sensing voltages VS1 to VSN according to the sensing capacitance variation of the capacitive sensing elements CS1 to CSN, and the controller U1 in the touch device 10 may determine a touch event on the touch panel TP1, for example, whether the touch panel TP1 is touched or not, and the position coordinates of the touched touch event according to the sensing voltages VS1 to VSN. In some embodiments, the capacitive sensing circuit 100 may be fabricated as a chip separately or may be disposed in the same chip as the controller U1.
In some embodiments, the touch panel TP1 can support self-capacitance sensing and mutual-capacitance sensing simultaneously to determine touch events. For example, the touch panel TP1 may include a lateral electrode and a longitudinal electrode. When the mutual capacitance sensing is utilized to determine a touch event, the transverse electrode on the touch panel TP1 receives the code signal, and the code signal on the transverse electrode is coupled to the longitudinal electrode through the mutual capacitance between the transverse electrode and the longitudinal electrode. When a finger touches the vicinity of the intersection of a transverse electrode and a longitudinal electrode, the mutual capacitance between the transverse electrode and the longitudinal electrode changes, so that the coupling signal on the longitudinal electrode correspondingly changes, and the touch event on the touch panel TP1 can be judged by sensing the signal change on the longitudinal electrode. When the self-capacitance sensing is utilized to determine a touch event, the touch panel TP1 can simultaneously utilize the self-capacitance of the transverse electrode and the longitudinal electrode to perform touch detection because the self-capacitance exists between the transverse electrode and the system ground terminal and the self-capacitance exists between the longitudinal electrode and the system ground terminal. That is, each of the capacitive sensing elements CS1 to CSN shown in fig. 2 may be a self-capacitance formed by the lateral electrode and the ground terminal or a self-capacitance formed by the vertical electrode and the ground terminal of the touch panel TP 1. However, in some other embodiments, the touch panel TP1 may determine the touch event by using only self-capacitance sensing, and the capacitive sensing elements CS1 to CSN may be arranged in other ways or formed in other structures.
The capacitive sensing circuit 100 includes input terminals 1101 to 110N, and the input terminals 1101 to 110N are respectively coupled to corresponding capacitive sensing elements CS1 to CSN of the touch panel TP 1. The capacitive sensing circuit 100 can detect the change of the sensed capacitance of the capacitive sensing elements CS1 to CSN through the input terminals 1101 to 110N to output the corresponding sensing voltages VS1 to VSN.
For example, the capacitance sensing circuit 100 may include first charging circuits 1201 to 120N, first discharging circuits 1301 to 130N, and first capacitance amplifying circuits 1401 to 140N. In the following, the operation of the first charging circuit 1201, the first discharging circuit 1301 and the first capacitance amplifying circuit 1401 is taken as an example for convenience of understanding, and in this embodiment, the first charging circuits 1202 to 120N, the first discharging circuits 1302 to 130N and the first capacitance amplifying circuits 1402 to 140N may have the same structure and may operate according to the same principle as the first charging circuit 1201, the first discharging circuit 1301 and the first capacitance amplifying circuit 1401, respectively.
In fig. 2, a first input 1101 may be coupled to a first capacitive sensing element CS1. The first charging circuit 1201 may be coupled to the operating voltage VDD, and may provide the operating voltage VDD to the first input 1101 in a first period of time such that the first capacitive sensing element CS1 is charged to the operating voltage VDD. The first discharging circuit 1201 may be coupled to the ground voltage VSS, and may enable the first capacitive sensing element CS1 to discharge a portion of the electric power during the discharging time in a second period after the first period, so as to reduce the influence of the first intrinsic capacitance C B1 of the first capacitive sensing element CS1 itself on the first sensing voltage VS1. Next, the first capacitive amplifying circuit 1401 may generate the first sensing voltage VS1 according to the reference voltage VCM and the voltage of the first input 1101 in a third period after the second period.
In fig. 2, the first capacitance amplifying circuit 1401 may include a differential amplifier 142 and an integrating capacitance C INT. The differential amplifier 142 has a first input and a second input, the first input of the differential amplifier 142 may be, for example, a positive input, and the second input of the differential amplifier 142 may be, for example, a negative input. The first input terminal of the differential amplifier 142 may be coupled to the reference voltage VCM, and the integrating capacitor C INT may be coupled between the second input terminal and the output terminal of the differential amplifier 142. In the present embodiment, the reference voltage VCM can be regarded as a reference common mode voltage of the differential amplifier 142, and the negative input terminal of the differential amplifier 142 is coupled to the first input terminal 1101 in the third period, so that the differential amplifier 142 amplifies the difference between the voltage of the first input terminal 1101 and the reference voltage VCM to generate the first sensing voltage VS1 in the third period.
If the first capacitive sensor CS1 releases the target power Q1 in the second period of time when there is no touch event on the first capacitive sensor CS1, the voltage VR1 of the first input terminal 1101 is shown in formula (2), and the first sensing voltage VS1 is shown in formula (3).
In the present embodiment, if the operating voltage VDD is twice the reference voltage VCM, when the target power Q1 is equal to the product of the difference between the operating voltage VDD and the reference voltage VCM and the first intrinsic capacitance C B1, the voltage VR1 and the first sensing voltage VS1 of the first input terminal 1101 can be respectively represented by the equations (4) and (5).
According to the equations (4) and (5), the first input terminal and the second input terminal of the differential amplifier 142 will be at the reference voltage VCM in the third period, and therefore the first sensing voltage VS1 will be 0 in the third period. That is, the first sensing voltage VS1 is independent of the magnitude of the first intrinsic capacitance value C B1 of the first capacitive sensing piece CS1 when no touch event occurs on the first capacitive sensing piece CS 1. In contrast, when a touch event occurs on the first capacitive sensor CS1 to cause a change in the sensed capacitance of the first capacitive sensor CS1, the voltage VR1 at the first input terminal 1101 can be represented by equation (6), and the first sensed voltage VS1 can be represented by equation (7).
In the formulas (6) and (7), Δc1 is the change of the sensing capacitance value of the first capacitive sensing element CS1 due to the approach of the human body, that is, when a touch event occurs on the first capacitive sensing element CS1, the sensing capacitance value of the first capacitive sensing element CS1 is changed from the original first intrinsic capacitance value C B1 to the sum of the first intrinsic capacitance value C B1 and the sensing capacitance value change Δc1. In this case, according to the formula (7), in the case that the touch event occurs on the first capacitive sensing element CS1, the first sensing voltage VS1 is only related to the sensing capacitance change Δc1 of the first capacitive sensing element CS1 caused by the approach of the human body, but is still independent of the magnitude of the first intrinsic capacitance C B1 of the first capacitive sensing element CS1, so that the first sensing voltage VS1 can more directly represent the sensing capacitance change Δc1 of the first capacitive sensing element CS1 caused by the approach of the human body, so that the touch device 10 can perform the touch detection more accurately.
In fig. 2, the first charging circuit 1201 may include a first switch SW1 and a first resistor R1. The first switch SW1 has a first end, a second end and a control end, the first end of the first switch SW1 may be coupled to the operating voltage VDD, and the control end of the first switch SW1 may receive the first control signal SIG CT1. The first resistor R1 has a first end and a second end, the first end of the first resistor R1 is coupled to the second end of the first switch SW1, and the second end of the first resistor R1 is coupled to the first input terminal 1101.
The first discharging circuit 1301 may include a second resistor R2 and a second switch SW2. The second resistor R2 has a first end and a second end, and the first end of the second resistor R2 is coupled to the first input terminal 1101. The second switch SW2 has a first end, a second end and a control end, the first end of the second switch SW2 is coupled to the second end of the second resistor R2, the second end of the second switch SW2 is coupled to the ground voltage VSS, and the control end of the second switch SW2 can receive the second control signal SIG CT2.
The first capacitance amplifying circuit 1401 may include a differential amplifier 142, a fifth switch SW5, a sixth switch SW6, and an integrating capacitance C INT. The differential amplifier 142 has a first input terminal, a second input terminal and an output terminal, and the first input terminal of the differential amplifier 142 is coupled to the reference voltage VCM. In this embodiment, the first input terminal of the differential amplifier 142 may be a positive input terminal, and the second input terminal of the differential amplifier 142 may be a negative input terminal.
The fifth switch SW5 has a first end, a second end and a control end, the first end of the fifth switch SW5 is coupled to the first input 1101, the second end of the fifth switch SW5 is coupled to the second input of the differential amplifier 142, and the control end of the fifth switch SW5 can receive the fourth control signal SIG CT4. The integrating capacitor C INT has a first end and a second end, the first end of the integrating capacitor C INT is coupled to the second input end of the differential amplifier 142, and the second end of the integrating capacitor C INT is coupled to the output end of the differential amplifier 142. The sixth switch SW6 has a first end, a second end and a control end, the first end of the sixth switch SW6 is coupled to the first end of the integrating capacitor C INT, the second end of the sixth switch SW6 is coupled to the second end of the integrating capacitor C INT, and the control end of the sixth switch SW6 can receive the reset control signal SIG RST.
Fig. 3 is a signal timing diagram of the capacitive sensing circuit 100 when detecting. In the first period TP1 of fig. 3, the first control signal SIG CT1 is at a high potential, the second control signal SIG CT2 is at a low potential, and at this time, the first switch SW1 is turned on and the second switch SW2 is turned off, so the first charging circuit 1201 charges the first capacitive sensing element CS1 through the first resistor R1.
Next, in the second period TP2 of fig. 3, the first control signal SIG CT1 is at a low potential, the second control signal SIG CT2 is at a high potential, and at this time, the first switch SW1 is turned off and the second switch SW2 is turned on, so that the first discharging circuit 1301 discharges the first capacitive sensing element CS1 through the second resistor R2. According to the physical characteristics of the capacitor discharge, the discharge amount of the first capacitive sensing element CS1 in the second period TP2 can be controlled by appropriately selecting the magnitude of the second resistor R2 and appropriately controlling the discharge time T DSC when the second control signal SIG CT2 is at a high potential. For example, if the target power to be discharged is (VDD-VCM) C B1, the voltage at the first input 1101 needs to be discharged from the operating voltage VDD to the reference voltage VCM. If the operating voltage VDD is twice the reference voltage VCM, the relationship between the discharging time T DSC and the first intrinsic capacitance C B1 and the second resistance R2 of the first capacitive sensor CS1 can be shown in equation (8) according to the discharging characteristic of the capacitor, and can be simplified into equation (9).
T DSC＝ln 2×R2×CB1 type (9)
That is, in the second period TP2, if the second control signal SIG CT2 can be kept at a high potential during the discharging time T DSC, the first capacitive sensor CS1 can be caused to release the target electric quantity (VDD-VCM) C B1. In this way, the voltage VR1 at the first input terminal 1101 is independent of the first intrinsic capacitance C B1 of the first capacitive sensor CS1 according to the description of equation (4).
Then, in the third period TP3, the fourth control signal SIG CT4 goes high, so that the fifth switch SW5 is turned on, and the first capacitive amplifying circuit 1401 generates the first sensing voltage VS1 according to the difference between the voltage VR1 of the first input terminal 1101 and the reference voltage VCM. In this case, since the first capacitive sensing element CS1 has released the target electric quantity (VDD-VCM) C B1, the first sensing voltage VS1 is independent of the first intrinsic capacitance value C B1 of the first capacitive sensing element CS1, and can be used to more directly represent the sensing capacitance value variation Δc1 of the first capacitive sensing element CS1 due to the proximity of the human body, so that the touch device 10 can perform touch detection more accurately.
In addition, in fig. 3, before the fourth control signal SIG CT4 changes to the high level, the reset signal SIG RST may change from the low level to the high level and then return from the high level to the low level, so that the integrating capacitor C INT in the first capacitor amplifying circuit 1401 may be reset and discharged in advance, so as to avoid the residual charges in the integrating capacitor C INT from affecting the generation of the first sensing voltage VS 1. Although in fig. 3, the reset signal SIG RST is changed to a high level in the second period TP2, i.e., the third period TP3, in some other embodiments, the reset signal SIG RST is changed from a low level to a high level before the fifth switch SW5 is turned on by the fourth control signal SIG CT4, and then is changed from the high level to the low level, so that the integrating capacitor C INT is completely discharged to complete the reset, and thus may be changed to the high level in the second period TP 2.
Furthermore, in the present embodiment, in order to more precisely control the discharge time of the first discharging circuit 1301 to the first capacitive sensing element CS1, that is, the discharge time T DSC of the second control signal SIG CT2 at the high potential, the capacitive sensing circuit 100 may include the discharge time control circuit 150 to generate the second control signal SIG CT2 to control the discharge time T DSC of the first discharging circuit 1301 in the second period TP2, so that the first capacitive sensing element CS1 can release the target electric quantity in the discharge time T DSC. Fig. 4 is a schematic diagram of a discharge time control circuit 150 according to an embodiment of the application. The discharge time control circuit 150 includes a reference capacitor C R, a third switch SW3, a third resistor R3, a fourth resistor R4, a fourth switch SW4, a comparator 152, a D-type flip-flop 154 and an and gate 156.
The reference capacitor C R has a first end and a second end, and the second end of the reference capacitor C R is coupled to the ground voltage VSS. The third switch SW3 has a first end, a second end and a control end, the first end of the third switch SW3 may be coupled to the ground voltage VSS, and the third switch SW3 may receive the first control signal SIG CT1. The third resistor R3 has a first end and a second end, the first end of the third resistor R3 is coupled to the second end of the third switch SW3, and the second end of the third resistor R3 is coupled to the first end of the reference capacitor C R. The fourth resistor R4 has a first end and a second end, and the first end of the fourth resistor R4 is coupled to the first end of the reference capacitor C R. The fourth switch SW4 has a first end, a second end and a control end, the first end of the fourth switch SW4 is coupled to the second end of the fourth resistor R4, the second end of the fourth switch SW4 is coupled to the operating voltage VDD, and the control end of the fourth switch SW4 can receive the second control signal SIG CT2.
The comparator 152 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the comparator 152 is coupled to the reference voltage VCM, and the second input terminal of the comparator 152 is coupled to the first terminal of the reference capacitor C R. The D-type flip-flop 154 has a data terminal D, a reset terminal RST, a rising edge trigger terminal TRG, an output terminal Q, and an inverting output terminal Q'. The reset terminal RST of the D-type flip-flop 154 receives the inverted control signal SIG CT1B inverted from the first control signal SIG CT1, and the rising edge trigger terminal of the D-type flip-flop 154 is coupled to the output terminal of the comparator 152. The and gate 156 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the and gate 156 is coupled to the inverting output terminal Q' of the D flip-flop 154, the second input terminal of the and gate 156 can receive the third control signal SIG CT3, and the output terminal of the and gate 156 can output the second control signal SIG CT2.
In the first period TP1 of fig. 3, the first control signal SIG CT1 is high and the inverted control signal SIG CT1B is low, so that the D-type flip-flop 154 is in the reset state and the inverted output terminal Q' outputs a high signal. However, since the third control signal SIG CT3 is kept at the low level in the first period TP1, the second control signal SIG CT2 outputted from the and gate 156 is still at the low level.
Next, in the second period TP2 of fig. 3, the first control signal SIG CT1 goes low, and the third control signal SIG CT3 goes high, and both input terminals of the and gate 156 are at high, so that the output of the high second control signal SIG CT2 is started. When the second control signal SIG CT2 goes high, the discharge time control circuit 150 charges the first terminal of the reference capacitor C R through the fourth resistor R4, and when the first terminal of the reference capacitor C R is charged to be greater than the reference voltage VCM, the voltage outputted by the comparator 152 changes, so that the D-type flip-flop 154 is triggered to output a low signal from the inverting output terminal Q', and the second control signal SIG CT2 outputted by the and gate 156 changes back to low.
In the present embodiment, if the capacitance of the reference capacitor C R is equal to the first intrinsic capacitance C B1 of the first capacitance sensor CS1, and the capacitance of the fourth resistor R4 is equal to the second resistor R2. In addition, since the operating voltage VDD is twice the reference voltage VCM, the first terminal of the reference capacitor C R is charged from the ground voltage VSS to the reference voltage VCM, so that the time required for the output potential of the comparator 152 to generate the transition will be the same as the time required for the first capacitor CS1 to discharge the target power (VDD-VCM) C B1 from the operating voltage VDD to the reference voltage VCM through the second resistor R2, that is, the discharge time control circuit 150 may keep the second control signal SIG CT2 at the high potential for the discharge time T DSC of the second period TP2 and change back to the low potential after the end of the discharge time T DSC, so that the first capacitor CS1 can discharge the power close to or equal to the target power (VDD-VCM) C B1.
In addition, in some embodiments, to reduce the area required by the capacitive sensing circuit 100, the capacitance of the reference capacitor C R is K times the first intrinsic capacitance C B1, where K is greater than 1, the resistance of the third resistor R3 is K times the resistance of the first resistor R1, and the resistance of the fourth resistor R4 is K times the resistance of the second resistor R2. In this way, the product of the capacitance value of the reference capacitor C R and the third resistor R3 (or the fourth resistor R4) is the same as the product of the first intrinsic capacitance value C B1 and the first resistor R1 (or the second resistor R2), so that the two have the same charge-discharge time constant, and thus have the same charge-discharge characteristics. In this case, the time required for the reference capacitor C R to be charged from the ground voltage VSS to the reference voltage VCM to transition the output voltage of the comparator 152 is still the same as the time required for the first capacitor CS1 to discharge the target power (VDD-VCM) C B1 from the operating voltage VDD to the reference voltage VCM through the second resistor R2, and the area required for the reference capacitor C R can be reduced.
In addition, in the present embodiment, the third control signal SIG CT3 is kept at the high level during the second period TP2, and in order to ensure that the second control signal SIG CT2 does not change back to the low level early, the third control signal SIG CT3 may be kept at the high level for a longer period of time, so as to ensure that the second control signal SIG CT2 changes to the low level after the fourth switch SW4 is turned on and the reference capacitor C R is charged to the reference voltage VCM, without causing the and gate 156 to pull back the second control signal SIG CT2 to the low level early due to the third control signal SIG CT3 changing to the low level early.
Since the capacitance sensing circuit 100 can make the first capacitance sensing element CS1 release the target electric quantity, the influence of the first intrinsic capacitance value C B1 of the first capacitance sensing element CS1 on the first sensing voltage VS1 can be eliminated, so that the first sensing voltage VS1 can more directly represent the sensing capacitance value variation Δc1 of the first capacitance sensing element CS1 caused by the approach of the human body, and is irrelevant to the magnitude of the first intrinsic capacitance value C B1. In this way, the touch device 10 can obtain more accurate results when performing touch detection according to the first sensing voltage VS 1.
In the embodiment of fig. 2, the second control signal SIG CT2 generated by the charge time control circuit 150 can also be used to control the other discharging circuits 1302 to 130N so that the capacitive sensing devices CS2 to CSN release a predetermined amount of power. For example, if the discharging circuits 1302 to 130N also discharge the capacitive sensing elements CS2 to CSN in the discharging time T DSC when the second control signal SIG CT2 is at high voltage, the portion related to the intrinsic capacitance values of the capacitive sensing elements CS1 to CSN can be eliminated in the sensing voltages VS2 to VSN, and the change of the sensing capacitance values of the capacitive sensing elements CS2 to CSN due to the proximity of the human body can be more directly presented.
However, in some embodiments, the intrinsic capacitance values of the capacitive sensing elements CS1 to CSN may not be exactly the same, but may have an error of about 10% with respect to each other due to the process-difficult difference. In this case, the capacitive sensing circuit 100 may use the capacitive sensing element with the smallest intrinsic capacitance value as a reference to generate the second control signal SIG CT2, and further remove the error of the intrinsic capacitance values of the other capacitive sensing elements by canceling the capacitance.
Fig. 5 is a schematic diagram of a capacitive sensing circuit 200 according to another embodiment of the application. The capacitive sensing circuit 200 has a similar structure and operates according to a similar principle as the capacitive sensing circuit 100. The capacitance sensing circuit 200 may include input terminals 2101 to 210N, charging circuits 2201 to 220N, discharging circuits 2301 to 230N, capacitance amplifying circuits 2401 to 240N, a discharging time control circuit 250, offset capacitors 2601 to 260N, and offset capacitance control circuits 2701 to 270N.
In this embodiment, since the intrinsic capacitances of the capacitive sensing elements CS1 to CSN are not identical, after the intrinsic capacitances of the capacitive sensing elements CS1 to CSN are measured, the capacitive sensing element with the smallest intrinsic capacitance can be selected as the reference. For example, if the first intrinsic capacitance C B1 of the capacitive sensor CS1 is smaller than the intrinsic capacitances of the other capacitive sensors CS2 to CSN, the capacitance of the reference capacitive element C R in the discharge time control circuit 250 can be set to be K-th of the first intrinsic capacitance C B1. In this way, the discharging time control circuit 250 can maintain the second control signal SIG CT2 at a high level during the discharging time T DSC, and make the first capacitive sensor CS1 release the target power (VDD-VCM) C B1 after charging. According to the descriptions of the formulas (6) to (7), after the first capacitive sensing element CS1 is enabled to release the target electric quantity (VDD-VCM) C B1, the first sensing voltage VS1 can more directly represent the sensing capacitance change Δc1 of the first capacitive sensing element CS1 due to the proximity of the human body, and is independent of the magnitude of the first intrinsic capacitance C B1.
After the charging circuits 2302 to 230N charge the capacitive sensing devices CS2 to CSN, although the discharging circuits 2302 to 230N synchronously release the corresponding electric quantities from the capacitive sensing devices CS2 to CSN according to the second control signal SIG CT2, the intrinsic capacitance values of the capacitive sensing devices CS2 to CSN may not be exactly the same as the first intrinsic capacitance value C B1, so that the influence of the intrinsic capacitance values of the capacitive sensing devices CS2 to CSN on the sensing voltages VS2 to VSN after the corresponding electric quantities are released from the capacitive sensing devices CS2 to CSN still cannot be completely eliminated, that is, the sensing voltages VS2 to VSN are still related to the intrinsic capacitance values of the capacitive sensing devices CS2 to CSN. To solve this problem, the capacitance sensing circuit 200 can further cancel the amount of power that should be released but not released in the capacitance sensing devices CS2 to CSN by canceling the capacitance elements 2601 to 260N and canceling the capacitance control circuits 2701 to 270N, thereby reducing errors caused by the difference of the intrinsic capacitance values of the capacitance sensing devices CS2 to CSN.
In fig. 5, the second canceling capacitor 2602 has a first end and a second end, and the second canceling capacitor control circuit 2702 may be coupled to the second canceling capacitor 2602 and the second input end 2102. In the present embodiment, the second canceling capacitance control circuit 2702 may include a seventh switch SW7, an eighth switch SW8, a ninth switch SW9 and a tenth switch SW10.
The seventh switch SW7 has a first end, a second end and a control end, the first end of the seventh switch SW7 may be coupled to the ground voltage VSS, the second end of the seventh switch SW7 may be coupled to the first end of the second offset capacitor 2602, and the control end of the seventh switch SW7 may receive the first control signal SIG CT1. The eighth switch SW8 has a first end, a second end and a control end, the first end of the eighth switch SW8 is coupled to the second end of the second offset capacitor 2602, the second end of the eighth switch SW8 is coupled to the operating voltage VDD, and the control end of the eighth switch SW8 can receive the first control signal SIG CT1. The ninth switch SW9 has a first end, a second end and a control end, the first end of the ninth switch SW9 is coupled to the second end of the second offset capacitor 2602, the second end of the ninth switch SW9 is coupled to the ground voltage VSS, and the control end of the ninth switch SW9 can receive the fifth control signal SIG CT5. The tenth switch SW10 has a first end, a second end and a control end, the first end of the tenth switch SW10 is coupled to the first end of the second offset capacitor 2602, the second end of the tenth switch SW10 is coupled to the second input end 2102, and the control end of the tenth switch SW10 can receive the fifth control signal SIG CT5.
Fig. 6 is a signal timing diagram of the capacitive sensing circuit 200 when detecting. In the first period TP1, the first control signal SIG CT1 is high, and the second control signal SIG CT2, the fourth control signal SIG CT4, and the fifth control signal SIG CT5 are low. At this time, the second capacitance sensing device CS2 is charged to the operating voltage VDD, the first terminal of the second offset capacitance device 2602 is coupled to the ground voltage VSS, and the second terminal of the second offset capacitance device 2602 is coupled to the operating voltage VDD.
In the second period TP2, the first control signal SIG CT1 is low, and the second control signal SIG CT2 is maintained high for a time T DSC, so that the second capacitive sensor CS2 also discharges a charge close to (VDD-VCM) C B1. If the difference between the second intrinsic capacitance C B2 of the second capacitive sensor CS2 and the first intrinsic capacitance C B1 of the first capacitive sensor CS1 is Δc B, a portion of the power of the second capacitive sensor CS2 is released within the time T DSC, and then the remaining portion of the power needs to be released to remove the influence of the difference Δc B on the second sensing voltage VS2, so that the second sensing voltage VS2 is independent of the magnitude of the second intrinsic capacitance C B2 of the second capacitive sensor CS 2.
In order to eliminate the remaining amount of power to be discharged, in the fourth period TP4 between the second period TP2 and the third period TP3, the fifth control signal SIG CT5 becomes high, and at this time, the first terminal of the second canceling capacitor 2602 is coupled to the second input terminal 2102, and the second terminal of the second canceling capacitor 2602 is coupled to the ground voltage VSS. In this case, the charges stored in the second capacitance sensing element CS2 and the second canceling capacitor 2602 are redistributed among the second capacitance sensing element CS2 and the second canceling capacitor 2602.
If the capacitance of the offset capacitor 2602 is one third of the intrinsic capacitance of the capacitor CS2 when the capacitor CS2 is not previously discharged, part of the charge in the capacitor CS2 can be received by the offset capacitor 2602 to remove the portion of the sensing voltage VS2 related to the intrinsic capacitance of the capacitor CS 2. However, in the present embodiment, since the capacitance sensing circuit 200 can discharge part of the electric quantity of the capacitance sensing element CS2 through the discharging circuit 2302, the smaller canceling capacitance element 2602 can be used, and the portion of the sensing voltage VS2 related to the inherent capacitance value of the capacitance sensing element CS2 can be effectively removed. For example, if the difference between the first intrinsic capacitance C B1 and the second intrinsic capacitance C B2 is Δc B, and the discharge circuits 2301 and 2302 are also discharging according to the discharge time T DSC of the second control signal SIG CT2 of the discharge time control circuit 250, the capacitance of the second canceling capacitor 2602 is the difference Δc B between the first intrinsic capacitance C B1 and the second intrinsic capacitance C B2 according to the characteristics of the capacitive dischargeWhen the power is doubled, the remaining power to be eliminated is transferred to the second offset capacitor 2602. In this way, in the third period TP3, when the fourth control signal SIG CT4 goes high, the second sensing voltage VS2 generated by the second capacitance amplifying circuit 2402 can directly represent the sensing capacitance value variation of the second capacitance sensing piece CS2 due to the proximity of the human body.
Furthermore, since the difference Δc B is generally about 10% of the first inherent capacitance C B1, the capacitance required to cancel the capacitor 2602 of the capacitive sensing circuit 200 can be significantly reduced compared to the prior art. Similarly, the canceling capacitors 2603 to 260N and the canceling capacitor control circuits 2703 to 270N can cancel the amount of power that should be released but not released in the capacitive sensing devices CS3 to CSN in the same manner as the canceling capacitors 2602 and the canceling capacitor control circuits 2702, so that the capacitance value required for canceling the capacitors 2603 to 260N is also smaller, and thus the area required for the capacitive sensing circuit 200 can be significantly reduced.
In addition, in some embodiments, since the magnitude of the intrinsic capacitance of each of the capacitive sensing elements CS1 to CSN in the touch panel TP1 cannot be known at the time of manufacturing the capacitive sensing circuit 200, the canceling capacitors 2601 to 260N may include a variable capacitor or a capacitor array. In this way, the capacitance of the offset capacitors 2601 to 260N can be adjusted according to the actual requirement. For example, in the present embodiment, the canceling capacitor 2602 can be changed according to the difference Δc B between the first intrinsic capacitance C B1 and the second intrinsic capacitance C B2 by the control signal, so that the amount of power remaining to be canceled in the second capacitive sensor CS2 can be effectively canceled in the fourth period TP 4.
Furthermore, although the second control signal SIG CT2 can be generated by the discharge time control circuits 150 and 250 in the foregoing embodiment, the first capacitive sensor CS1 can release the target power (VDD-VCM) C B1 in the time T DSC of the second period TP2 to eliminate the influence of the first intrinsic capacitance C B1 of the first capacitive sensor CS1 on the first sensing voltage VS 1. However, in some other embodiments, it is also possible to estimate the minimum inherent capacitance value of the capacitive sensing devices CS1 to CSN in advance, and make the discharge time control circuit 250 generate the second control signal SIG CT2 according to the estimated value, and then remove the charges remaining to be removed but not removed in the capacitive sensing devices CS1 to CSN by using the canceling capacitors 2601 to 260N and the canceling capacitor control circuits 2701 to 270N in the manner described above. In this way, the portion of the sensing voltages VS1 to VSN related to the intrinsic capacitance values of the capacitive sensing elements CS1 to CSN can be effectively removed without actually detecting the intrinsic capacitance value of each capacitive sensing element CS1 to CSN, so that the sensing voltages VS1 to VSN can directly represent the variation of the sensing capacitance value of the capacitive sensing element due to the approach of the human body, and the touch device can perform touch detection more accurately.
In summary, the capacitive sensing circuit, the related chip and the touch device provided by the embodiments of the application can release part of the electric quantity from the capacitive sensing element through the discharging circuit when the capacitive sensing element in the touch panel is sensed, so that the influence of the intrinsic capacitance of the capacitive sensing element on the sensing voltage can be effectively eliminated. In addition, the capacitive sensing circuit, the related chip and the touch device provided by the embodiment of the application can further eliminate the influence of the inherent capacitance value of the capacitive sensing element on the sensing voltage by utilizing the offset capacitive element and the offset capacitive control circuit, so that the sensing voltage generated by the capacitive sensing circuit can directly represent the sensing capacitance value variation of the capacitive sensing element caused by the approach of a human body, thereby improving the accuracy of touch detection.
The foregoing description briefly sets forth features of certain embodiments of the application in order to provide a thorough understanding of the various aspects of the present disclosure to those skilled in the art. It will be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. It will be apparent to those skilled in the art that such equivalent embodiments are within the spirit and scope of the present disclosure, and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.

Claims (16)

1. A capacitive sensing circuit for generating a plurality of sensing voltages according to sensing capacitance variation of a plurality of capacitive sensing elements of a touch panel, the capacitive sensing circuit comprising:
The first input end is coupled with a first capacitance sensing piece of the touch panel, and the first capacitance sensing piece has a first inherent capacitance value;
The first charging circuit is coupled to an operating voltage and is used for providing the operating voltage to the first input end of the capacitance sensing circuit in a first period of time so that the first capacitance sensing element is charged to the operating voltage;
The first discharging circuit is coupled to the ground voltage and used for discharging the first capacitance sensing element; a discharge time control circuit for controlling a discharge time of the first discharge circuit to the first capacitive sensing element in a second period after the first period; and
A first capacitance amplifying circuit for generating a first sensing voltage according to a reference voltage and a voltage of the first input terminal of the capacitance sensing circuit in a third period after the second period, wherein the operating voltage is twice the reference voltage;
The first discharging circuit enables the first capacitance sensing piece to release target electric quantity in the discharging time, and the target electric quantity is smaller than or equal to the product of the difference value of the operating voltage minus the reference voltage and the first inherent capacitance value, so that correlation between the first sensing voltage and the first inherent capacitance value of the first capacitance sensing piece is reduced.
2. The capacitive sensing circuit of claim 1, wherein the first charging circuit comprises:
The first switch is provided with a first end, a second end and a control end, wherein the first end of the first switch is coupled with an operating voltage, and the control end of the first switch is used for receiving a first control signal; and
The first resistor is provided with a first end and a second end, the first end of the first resistor is coupled with the second end of the first switch, and the second end of the first resistor is coupled with the first input end of the capacitance sensing circuit.
3. The capacitive sensing circuit of claim 2, wherein said first discharge circuit comprises:
a second resistor having a first end and a second end, the first end of the second resistor being coupled to the first input end of the capacitive sensing circuit; and
The second switch is provided with a first end, a second end and a control end, wherein the first end of the second switch is coupled with the second end of the second resistor, the second end of the second switch is coupled with the ground voltage, and the control end of the second switch is used for receiving a second control signal.
4. The capacitive sensing circuit of claim 3, wherein the discharge time control circuit comprises:
a reference capacitor having a first end and a second end, the second end of the reference capacitor being coupled to the ground voltage;
the third switch is provided with a first end, a second end and a control end, wherein the first end of the third switch is coupled with the ground voltage, and the third switch is used for receiving the first control signal;
A third resistor having a first end and a second end, the first end of the third resistor being coupled to the second end of the third switch, and the second end of the third resistor being coupled to the first end of the reference capacitor;
A fourth resistor having a first end and a second end, the first end of the fourth resistor being coupled to the first end of the reference capacitor;
A fourth switch having a first end, a second end and a control end, wherein the first end of the fourth switch is coupled to the second end of the fourth resistor, the second end of the fourth switch is coupled to the operating voltage, and the control end of the fourth switch is used for receiving the second control signal;
A comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the comparator is coupled to the reference voltage, and the second input terminal of the comparator is coupled to the first terminal of the reference capacitor;
The D-type flip-flop is provided with a reset end, a rising edge trigger end and an inverting output end, wherein the reset end of the D-type flip-flop is used for receiving an inverting control signal which is in inverting phase with the first control signal, and the rising edge trigger end of the D-type flip-flop is coupled with the output end of the comparator; and
The AND gate is provided with a first input end, a second input end and an output end, wherein the first input end of the AND gate is coupled with the reversed phase output end of the D-type flip-flop, the second input end of the AND gate is used for receiving a third control signal, and the output end of the AND gate is used for outputting the second control signal.
5. The capacitive sensing circuit of claim 4, wherein:
the capacitance value of the reference capacitance element is one-fourth of the first inherent capacitance value, wherein K is greater than or equal to 1;
The resistance value of the third resistor is K times of the resistance value of the first resistor; and
And the resistance value of the fourth resistor is K times of the resistance value of the second resistor.
6. The capacitive sensing circuit of claim 4, wherein:
The first control signal is at a high potential in the first period and turns on the third switch, and the first control signal is at a low potential in the second period and turns off the third switch; and
The third control signal is low in the first period and the third control signal is high in the second period.
7. The capacitive sensing circuit of claim 1, wherein the first capacitive amplifying circuit comprises:
A differential amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the differential amplifier being coupled to the reference voltage;
A fifth switch having a first end, a second end and a control end, wherein the first end of the fifth switch is coupled to the first input end of the capacitance sensing circuit, and the first end of the capacitance sensing circuit
The second end of the fifth switch is coupled to the second input end of the differential amplifier;
An integrating capacitor having a first end and a second end, the first end of the integrating capacitor being coupled to the second input of the differential amplifier, and the second end of the integrating capacitor being coupled to the output of the differential amplifier; and
The sixth switch has a first end, a second end and a control end, the first end of the sixth switch is coupled to the first end of the integrating capacitor, and the second end of the sixth switch is coupled to the second end of the integrating capacitor, and the control end of the sixth switch is used for receiving a reset control signal.
8. The capacitive sensing circuit of claim 1, further comprising:
the first offset capacitor piece is provided with a first end and a second end; and
The first offset capacitance control circuit is coupled to the first offset capacitance element and the first input terminal of the capacitance sensing circuit, and is configured to couple the first terminal of the first offset capacitance element to the ground voltage and the second terminal of the first offset capacitance element to the operating voltage in the first period, and to couple the first terminal of the first offset capacitance element to the first input terminal of the capacitance sensing circuit and the second terminal of the first offset capacitance element to the ground voltage in a fourth period between the second period and the third period.
9. The capacitive sensing circuit of any one of claims 1 to 8, further comprising:
The second input end is coupled with a second capacitance sensing piece of the touch panel, and the second capacitance sensing piece has a second inherent capacitance value;
A second charging circuit for providing the operating voltage to the second input terminal of the capacitance sensing circuit in a first period of time so that the second capacitance sensing element is charged to the operating voltage;
a second discharge circuit for synchronously discharging the second capacitive sensing element and the first capacitive sensing element in the second period; and
The second capacitance amplifying circuit is used for generating a second sensing voltage according to the reference voltage and the voltage of the second input end of the capacitance sensing circuit in the third period.
10. The capacitive sensing circuit of claim 9, wherein said second intrinsic capacitance value is greater than said first intrinsic capacitance value, and said capacitive sensing circuit further comprises:
The second offset capacitor piece is provided with a first end and a second end; and
The second offset capacitance control circuit is coupled to the second offset capacitance element and the second input terminal of the capacitance sensing circuit, and is configured to couple the first terminal of the second offset capacitance element to the ground voltage and the second terminal of the second offset capacitance element to the operating voltage in the first period, and to couple the first terminal of the second offset capacitance element to the second input terminal of the capacitance sensing circuit and the second terminal of the second offset capacitance element to the ground voltage in a fourth period between the second period and the third period.
11. The capacitance sensing circuit of claim 10, wherein the second canceling capacitance control circuit comprises:
A seventh switch having a first end, a second end and a control end, wherein the first end of the seventh switch is coupled to the ground voltage, and the second end of the seventh switch is coupled to the first end of the second offset capacitor;
an eighth switch having a first end, a second end and a control end, wherein the first end of the eighth switch is coupled to the second end of the second offset capacitor, and the second end of the eighth switch is coupled to the operating voltage;
a ninth switch having a first end, a second end, and a control end, the first end of the ninth switch being coupled to the second end of the second cancellation capacitor, and the second end of the ninth switch being coupled to the ground voltage; and
A tenth switch having a first end, a second end and a control end, wherein the first end of the tenth switch is coupled to the first end of the second offset capacitor, and the second end of the tenth switch is coupled to the second input end of the capacitance sensing circuit.
12. The capacitive sensing circuit of claim 10, wherein the capacitance value of said second canceling capacitor is the difference between said first intrinsic capacitance value and said second intrinsic capacitance valueMultiple times.
13. The capacitive sensing circuit of claim 12, wherein the second canceling capacitor comprises a variable capacitor or a capacitor array, wherein a capacitance value of the variable capacitor or the capacitor array is changeable by a control signal in dependence on the difference between the first intrinsic capacitance value and the second intrinsic capacitance value.
14. A chip, comprising:
A capacitive sensing circuit as claimed in any one of claims 1 to 13.
15. The chip of claim 14, further comprising:
and the controller is used for judging the touch event on the touch panel according to the plurality of sensing voltages.
16. A touch device, comprising:
a capacitive sensing circuit as claimed in any one of claims 1 to 13;
The touch panel; and
And the controller is used for judging the touch event on the touch panel according to the plurality of sensing voltages.
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