CN113066818B

CN113066818B - Display screen and electronic equipment

Info

Publication number: CN113066818B
Application number: CN202010106846.9A
Authority: CN
Inventors: 安亚斌; 贺海明; 庞永强; 田旭辉
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-12-13
Filing date: 2020-02-20
Publication date: 2022-10-04
Anticipated expiration: 2040-02-20
Also published as: CN113066818A

Abstract

Embodiments of the present application provide a display screen and an electronic device, which relate to the technical field of display. It is used to improve the problem of large power consumption of self-luminous display screens under low frequency driving. The display screen includes a plurality of sub-pixels, a substrate, a light-emitting device, a pixel circuit and an isolation portion. Wherein, the light-emitting device, the pixel circuit and the isolation part are arranged on the substrate, and the pixel circuit is coupled with the light-emitting device and is located in the sub-pixel. The pixel circuit includes a first transistor and a second transistor, an active layer of the first transistor includes polysilicon, and an active layer of the second transistor includes a semiconductor oxide. In addition, the isolation portion includes an isolation base and an isolation barrier wall surrounding the isolation base. The active layer of the second transistor is disposed in the groove formed by the isolation barrier and the isolation base, wherein the isolation portion is at least used to block hydrogen ions in the active layer of the first transistor from diffusing into the active layer of the second transistor.

Description

Display screen and electronic equipment

The present application claims priority from a chinese patent application filed by the national intellectual property office on 12/13/2019, having application number 201911284587.2, entitled "semiconductor oxide thin film transistor display and electronic device," the entire contents of which are incorporated herein by reference.

Technical Field

The application relates to the technical field of display, in particular to a display screen and electronic equipment.

Background

Self-luminous display screens, such as Organic Light Emitting Diode (OLED) display screens, have been receiving great attention and developed for a long time due to their advantages of self-luminescence, fast response, high brightness, light weight, and the like. However, in the current self-emitting display, the leakage current of a part of transistors in the pixel circuit is large, so that the power consumption is high in a low-frequency driving scene, such as a standby state, and the standby time of the device is reduced.

Disclosure of Invention

The embodiment of the application provides a display screen and an electronic device, which are used for solving the problem that the self-luminous display screen is large in power consumption under low-frequency driving.

In order to achieve the purpose, the following technical scheme is adopted in the application:

in a first aspect of embodiments of the present application, there is provided a display panel including a plurality of sub-pixels, a substrate, a light emitting device, a pixel circuit, and an isolation portion. The light emitting device, the pixel circuit and the isolation portion are arranged on the substrate, and the pixel circuit is coupled with the light emitting device and located in the sub-pixel. The pixel circuit includes a first transistor whose active layer includes polysilicon and a second transistor whose active layer includes a semiconductor oxide. In addition, the isolation part comprises an isolation base and an isolation retaining wall arranged around the isolation base. The active layer of the second transistor is arranged in a groove formed by the isolation retaining wall and the isolation substrate, wherein the isolation part is at least used for preventing hydrogen ions in the active layer of the first transistor from diffusing into the active layer of the second transistor.

As described above, the first transistor is a polysilicon thin film transistor, and the second transistor is an oxide thin film transistor. The isolating part is composed of an isolating retaining wall and an isolating substrate, the isolating retaining wall and the isolating substrate form a groove, the active layer of the second transistor is arranged in the groove formed by the isolating retaining wall and the isolating substrate, and the active layer of the first transistor is arranged outside the groove formed by the isolating retaining wall and the isolating substrate, so that the isolating part can be used for isolating hydrogen ions in the active layer of the first transistor from diffusing into the active layer of the second transistor, and further, the situation that the oxide thin film transistor fails after the hydrogen ions in the low-temperature polycrystalline silicon thin film transistor diffuse into the active layer of the oxide thin film transistor is avoided, the pixel circuit not only comprises the low-temperature polycrystalline silicon thin film transistor, but also comprises the oxide thin film transistor is realized, and the oxide thin film transistor has low off-state current compared with the low-temperature polycrystalline silicon thin film transistor, therefore, when low-frequency driving is carried out, power consumption can be reduced, and standby time is prolonged.

Optionally, the display screen further includes a first gate insulating layer, a first passivation layer, a second passivation layer, and a second gate insulating layer sequentially over the substrate, where a material forming the first passivation layer includes silicon nitride, and a material forming the second passivation layer includes silicon oxide. In addition, the first gate insulating layer is positioned between the active layer and the first gate electrode of the first transistor, the active layer of the first transistor is close to the substrate, and the first passivation layer and the second passivation layer cover the first gate electrode of the first gate insulating layer.

In this case, the isolation barrier wall penetrates at least the first gate insulating layer and the first passivation layer, at least a portion of the second gate insulating layer is located within the isolation barrier wall, and further, the second gate insulating layer is located between the active layer of the second transistor and the second gate electrode, and the active layer of the second transistor is close to the substrate.

Therefore, the isolation retaining wall not only blocks hydrogen ions in the active layer of the first transistor, but also blocks hydrogen ions in the silicon nitride of the first passivation layer from diffusing into the active layer of the second transistor, so that damage of the hydrogen ions to the active layer of the second transistor is avoided, and meanwhile, the isolation retaining wall at least disconnects the first grid insulating layer and the first passivation layer, so that stress concentration caused by overlarge area of an inorganic oxide material can be prevented, and internal fracture when the display screen is bent is avoided.

Optionally, the isolation wall further penetrates the second passivation layer. In this case, the isolation barrier wall penetrates the first gate insulating layer, the first passivation layer, and the second passivation layer, and since the isolation barrier wall is higher than that of the above-described scheme, it is possible to better block hydrogen ions in the active layer of the first transistor and hydrogen ions in silicon nitride of the first passivation layer from diffusing into the active layer of the second transistor.

Optionally, the display screen further includes a common electrode layer, and the common electrode layer is located on one side of the first transistor and one side of the second transistor close to the substrate. And the first electrode of the first transistor or the second transistor is coupled with the common electrode layer. Based on this, firstly, because the common electrode layer is located at one side of the first transistor and the second transistor close to the substrate and is not in the same layer with the source/drain (S/D), the voltage drop (IR drop) can be reduced, the crosstalk of the data line can be avoided, meanwhile, the wiring space of the data line is saved, the resolution is improved, and secondly, the common electrode layer is not located at the upper lamination position, the thickness of the lamination can be reduced, and the continuous bending of the display screen can be conveniently realized.

In addition, the isolation substrate and the common electrode layer are made of the same material and are of an integral structure. Therefore, the manufacturing process can be simplified, and when the common electrode layer is manufactured, the same mask is used, and the isolation substrate is formed at the same time.

Optionally, the common electrode layer includes a metal material layer or a metal material layer and a surface oxide material layer stacked on the metal material layer. In this case, a perpendicular projection of the active layer of the first transistor onto the substrate is within a perpendicular projection of the common electrode layer onto the substrate, and a perpendicular projection of the active layer of the second transistor onto the substrate is within a perpendicular projection of the common electrode layer onto the substrate. Therefore, the common electrode layer can shield ambient light and damage to the active layer of the first transistor and the active layer of the second transistor in the processing process of Laser Lift Off (LLO) and other processing technologies, and secondly, the common electrode layer is made of a metal material, so that an external electric field and electrostatic discharge (ESD) can be shielded from entering, and the stability of the light-emitting device is improved.

Optionally, the first transistor further includes a third gate, where the third gate is located on a side of the first gate of the first transistor close to the substrate, and the first gate and the third gate in the first transistor are insulated. In addition, the third grid electrode of the first transistor and the common electrode layer are made of the same material and are insulated. Based on this, can use same mask, when making public electrode layer, form the third grid simultaneously, simplify technology, secondly, the bigrid compares with single gate, can increase the driving capability of transistor.

Optionally, the second transistor further includes a fourth gate, where the fourth gate is located on a side of the second gate of the second transistor close to the substrate, and the second gate and the fourth gate in the second transistor are insulated. In addition, the fourth gate electrode and the common electrode layer of the second transistor are made of the same material and are insulated. Based on this, can use same mask, when making public electrode layer, form the fourth grid simultaneously, simplify technology, secondly, the drive ability that can increase the transistor is compared to single gate to the double grid.

Optionally, the material constituting the substrate includes an organic material. At this moment, the display screen further comprises a first barrier layer, a first stress release layer and a second barrier layer which are sequentially arranged on the substrate, wherein the active layer of the first transistor is arranged on the surface of one side, far away from the substrate, of the second barrier layer. In addition, the common electrode layer is positioned between the first barrier layer and the first stress release layer and is connected with the first barrier layer and the first stress release layer. Under this condition, public electrode layer can play the effect of supporting the display screen, to flexible display screen, can be so that display screen panel stress homogeneous, reaches the effect of curling in succession, simultaneously, improves the magic seal that exists in the production process and the bad problem of garrulous spangle.

Optionally, the display screen further includes a first via hole. The first via hole penetrates through the first stress release layer, the second barrier layer, the first gate insulating layer and the first passivation layer in sequence. In addition, a first end of the first via hole is coupled to the common electrode layer, and a second end of the first via hole is coupled to the first electrode of the first transistor or the second transistor. The first via hole comprises a first metal conductive layer, and the isolation retaining wall and the first metal conductive layer are made of the same material in the same layer. In this case, the same mask can be used to form the first metal conductive layer when the isolation barrier is manufactured, thereby simplifying the process.

Optionally, the display screen further includes a second via hole. The first end of the second via is coupled to the second end of the first via, and the second end of the second via is coupled to the first electrode of the first transistor or the second transistor. In addition, the first via hole comprises a second metal conducting layer, and the second metal conducting layer and the first electrode layer of the first transistor are made of the same material. In this case, the same mask may be used to form the second metal conductive layer during the fabrication of the first electrode of the first transistor, so as to simplify the process.

Optionally, the material constituting the substrate includes an organic material. The display screen further comprises a first blocking layer, a connecting layer and a first stress release layer which are sequentially arranged on the substrate, wherein the connecting layer is used for connecting the first blocking layer with the first stress release layer. In addition, the common electrode layer is located between the substrate and the first barrier layer and is connected with the substrate and the first barrier layer. Or the display screen further comprises a second barrier layer positioned on one side, far away from the substrate, of the first stress release layer, and the active layer of the first transistor is positioned on the surface of one side, far away from the substrate, of the second barrier layer. The common electrode layer is located between the first stress release layer and the second barrier layer and connected with the first stress release layer and the second barrier layer. In this case, the common electrode layer can also play a role in supporting the display screen, and for the flexible display screen, the stress of the display screen panel can be uniform, so that the effect of continuous curling is achieved. Meanwhile, the problems of magic marks and poor broken bright sheets in the production process are solved.

Optionally, in the isolation barrier, the active layer of the second transistor is insulated from the isolation substrate, and the second barrier layer is disposed on the outer surface of the isolation barrier, which is far away from the active layer of the second transistor.

Therefore, firstly, the active layer of the second transistor and the isolation substrate can be isolated from each other to avoid electrical connection, and secondly, because the thickness of the second blocking layer is much greater than the thickness of the second passivation layer and the second gate insulating layer under normal conditions, when the second blocking layer is arranged on the outer surface of the isolation retaining wall far away from the active layer of the second transistor, the active layer of the second transistor can be positioned in the isolation part and lower than the active layer of the first transistor.

Optionally, the material constituting the substrate includes an inorganic material. The display screen also comprises a buffer layer positioned on the substrate, the common electrode layer is positioned between the substrate and the buffer layer and is connected with the substrate and the buffer layer, in addition, the active layer of the second transistor is insulated from the isolation base, and the buffer layer is arranged on the outer surface of the isolation retaining wall far away from the active layer of the second transistor. Based on this, for the display panel with the substrate material including the inorganic material, the common electrode layer can be also used to shield the active layer of the first transistor and the active layer of the second transistor from the damage of the process technologies such as shielding external light and Laser Lift Off (LLO), and to shield the external electric field and the electrostatic discharge (ESD). Second, since the thickness of the buffer layer is usually much greater than the thickness of the second passivation layer and the second gate insulating layer, when the buffer layer is disposed on the outer surface of the isolation barrier wall away from the active layer of the second transistor, the active layer of the second transistor can be located in the isolation portion and lower than the active layer of the first transistor.

Optionally, the pixel circuit further comprises a storage capacitor, and the storage capacitor comprises an insulated first electrode and an insulated second electrode. The first electrode is positioned on the surface of one side, away from the substrate, of the first gate insulating layer, and the first electrode and the gate of the first transistor are made of the same material at the same layer. In addition, the second electrode is located on the surface of one side, away from the substrate, of the second passivation layer, the second electrode is coupled with the first transistor, and the second electrode and the grid electrode of the second transistor are made of the same material in the same layer. In this case, the first electrode and the second electrode of the storage capacitor can be manufactured by using the same mask plate while the gate of the first transistor and the gate of the second transistor are manufactured, so that the process is simplified.

Optionally, the display screen further includes a third passivation layer covering the second gate insulating layer, and the storage capacitor further includes a third electrode, where the third electrode is located on a side surface of the third passivation layer away from the substrate and covers the second electrode, and the third electrode and the first electrode of the first transistor are made of the same material in the same layer. In addition, the display screen further comprises a third via hole penetrating through the second electrode, and the third electrode is coupled with the first electrode through the third via hole. Based on this, firstly, the third passivation layer can prevent hydrogen ions in the air from diffusing to the active layer of the second transistor in the production process, and damage to the active layer of the second transistor is avoided.

Optionally, the first transistor is coupled to the light emitting device, wherein the first transistor is configured to provide a driving current to the light emitting device, so that the light emitting device can be turned on quickly.

In a second aspect of the embodiments of the present application, an electronic device is provided, where the electronic device includes any one of the display screens described above, and the electronic device has the same technical effects as the display screen provided in the foregoing embodiments, and details are not repeated here.

Drawings

Fig. 1a is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

FIG. 1b is a schematic diagram of a display screen of the electronic device of FIG. 1 a;

fig. 1c is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;

fig. 2a is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 2b is a cross-sectional view taken along O-O in FIG. 1 b;

fig. 3 is a schematic structural diagram of another display screen provided in an embodiment of the present application;

fig. 4a is a schematic structural diagram of another display screen provided in an embodiment of the present application;

fig. 4b is a schematic structural diagram of another display screen provided in the embodiment of the present application;

fig. 4c is a schematic structural diagram of another display screen provided in the embodiment of the present application;

fig. 4d is a schematic structural diagram of another display screen provided in the embodiment of the present application;

fig. 4e is a schematic structural diagram of another display screen provided in the embodiment of the present application;

fig. 5a is a schematic structural diagram of another display screen provided in an embodiment of the present application;

fig. 5b is a schematic structural diagram of another display screen provided in the embodiment of the present application;

fig. 6a is a schematic structural diagram of another display screen provided in an embodiment of the present application;

fig. 6b is a schematic structural diagram of another display screen provided in the embodiment of the present application;

fig. 7a is a schematic structural diagram of another display screen provided in an embodiment of the present application;

fig. 7b is a schematic structural diagram of another display screen provided in the embodiment of the present application;

fig. 8 is a schematic structural diagram of another display screen provided in an embodiment of the present application;

fig. 9 is a schematic structural diagram of another display screen provided in an embodiment of the present application;

fig. 10 is a schematic structural diagram of another display screen provided in an embodiment of the present application.

Reference numerals:

01-an electronic device; 10-a display module; 11-middle frame; 12-a rear shell; 100-a display screen; 101-pixel circuitry; 102-a light emitting device; 103-sub-pixels; an s-source; a d-drain electrode; g-a grid; an AL-active layer; GL-grid line; td-drive transistor; tc-switching transistor; 215-pixel definition layer; 216-an anode; 217-light emitting layer; 218-a cathode; 225-hollow structure; 219 — second pole of first transistor; 222-a first gate; 212-first transistor active layer; 201-a substrate; 202-a first transistor; 203-a second transistor; 223-a second gate; 210-a third passivation layer; 208-a second gate insulation layer; 207-a second passivation layer; 206-a first passivation layer; 205-a first gate insulation layer; 213-second transistor active layer; 214-isolation retaining wall; 224-an isolation substrate; 204-a spacer; 301-a first barrier layer; 302-a first stress-release layer; 303-a second barrier layer; 228-a groove; 305 — a first via hole; 306-a second via hole; 307-a first metal conductive layer; 308-a second metal conductive layer; 304-a common electrode layer; a-a first electrode; b-a second electrode; e-a first via first end; f-a second via first end; cst-storage capacitance; c-a third electrode; d-a third via hole; 309-third gate; 310-a fourth gate; 311-a connection layer; 601-buffer layer.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, the meaning of "a plurality" is two or more unless otherwise specified.

Further, in the present application, directional terms such as "upper", "lower", and the like may include, but are not limited to, being defined relative to a schematically-disposed orientation of components in the drawings, it being understood that these directional terms may be relative concepts that are intended for relative description and clarification, and that will vary accordingly depending on the orientation of the components in the drawings in which they are disposed.

In this application, unless expressly stated or limited otherwise, the term "coupled" is to be construed broadly, e.g., "coupled" may be a fixed connection or a releasable connection or may be integral; may be directly connected or indirectly connected through an intermediate. Furthermore, the term "coupled" may be a manner of making electrical connections that communicate signals. "coupled" may be a direct electrical connection or an indirect electrical connection through intervening media.

The embodiment of the application provides electronic equipment. The electronic device includes a mobile phone (mobile phone), a tablet computer (pad), a computer, an intelligent wearable product (e.g., a smart watch, a smart band), a set top box, a media player, a portable electronic device, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, and other electronic products. The embodiment of the present application does not particularly limit the specific form of the electronic device.

For convenience of explanation, the electronic device 01 is taken as an example of a mobile phone as shown in fig. 1 a. In this case, the electronic device 01 mainly includes a display module 10, a middle frame 11 and a rear case 12. The middle frame 11 is located between the display module 10 and the rear case 12. The display module 10 and the rear shell 12 are respectively connected with the middle frame 11. The accommodating cavity formed between the rear case 12 and the middle frame 11 is used for accommodating a battery, a camera (not shown in fig. 1 a), and electronic components such as a Printed Circuit Board (PCB) shown in fig. 1 a.

As for any one of the electronic devices 01, the display module 10 in the electronic device 01 may include the display panel 100 as shown in fig. 1b, and the display panel 100 may include a plurality of sub-pixels 103 arranged in rows and columns, wherein the pixel circuits 101 and the light emitting devices 102 are located in the sub-pixels 103. The pixel circuit 101 drives the light emitting device 102 to emit light so that each sub-pixel 103 in the display screen 100 can perform display in a preset gray scale.

For example, the light emitting device 102 may be an organic light-emitting diode (OLED), a micro light-emitting diode (micro LED), or a mini light-emitting diode (mini LED). For convenience of description, the following description will be made by taking the light emitting device 102 as an OLED.

In some embodiments of the present application, the pixel circuit 101 may include a plurality of transistors, which may be Thin Film Transistors (TFTs), and at least one capacitor.

Any of the transistors may include a gate (gate, g), an Active Layer (AL) and a first electrode, such as a source(s), and a second electrode, such as a drain (d), as shown in fig. 1c (a cross-sectional view of the transistor). Alternatively, the first pole of the transistor may be the drain d and the second pole may be the source s. For convenience of illustration, the first pole of the transistor is taken as the source s, and the second pole is taken as the drain d.

The active layer AL is made of a semiconductor material. When a voltage applied to the gate electrode g of the transistor is capable of turning on the transistor, the active layer AL is converted into a conductor by an insulator, so that the source s and the drain g of the transistor are coupled. When the transistor cannot be turned on by a voltage applied to the gate electrode g of the transistor, the active layer AL is in an insulating state, and the source s and the drain d of the transistor are disconnected.

The active layers of the transistors are made of different materials, and the transistors have different properties. For example, when the material constituting the active layer of the transistor is polysilicon (e.g., low temperature polysilicon, LTPS), the polysilicon transistor has high electron mobility, and is generally applied to a case where the switching frequency is fast (e.g., the electronic device 01 is in an on state) to improve the switching efficiency. The low-temperature polysilicon is polysilicon deposited in a low-temperature environment (e.g., a temperature lower than 600 ℃).

Alternatively, for another example, when the material forming the active layer of the transistor is a semiconductor oxide (e.g., amorphous indium gallium zinc oxide, IGZO), since the semiconductor oxide transistor has a lower electron mobility than a polysilicon transistor but has a very low off-state current, it is generally applied to a case where the switching frequency is slow (e.g., the electronic device 01 is in a standby state), and can be used to reduce the leakage current, thereby reducing the power consumption. For convenience of description, a transistor whose active layer is made of polysilicon is referred to as a first transistor, and a transistor whose active layer is made of a semiconductor oxide is referred to as a second transistor.

In this regard, in order to enable the pixel circuit 101 to be quickly turned on when the high frequency driving is performed (for example, the electronic device 01 is in an on state) and to reduce power consumption when the low frequency driving is performed (for example, the electronic device 01 is in a standby state), the pixel circuit 101 includes at least one of the first transistor and the second transistor. Illustratively, as shown in fig. 2a, the pixel circuit 101 may include a driving transistor Td and a switching transistor Tc, and a capacitor Cst. At this time, the pixel circuit 101 has a 2T1C structure. Here, "2T" means two transistors, and "1C" means one storage capacitor.

The switching transistor Tc is used to be in a turned-on state under the control of a Gate Line (GL), thereby writing the data voltage Vdata into the gate g of the driving transistor Td and the storage capacitor Cst. The storage capacitor Cst may hold the gate voltage of the driving transistor Td, so that the gate voltage of the driving transistor Td can be stabilized within one image frame. In this case, the driving transistor Td may generate a driving current according to the data voltage Vdata, so that the light emitting device 102 may emit light according to the driving current.

In some embodiments of the present application, the driving transistor Td in fig. 2a may be the first transistor, for example, the active layer of the driving transistor Td is LTPS, and the switching transistor Tc may be the second transistor, for example, the active layer of the switching transistor is IGZO, in which case, since the electron mobility of the driving transistor Td (i.e., the first transistor) is high, the light emitting device 102 can be turned on quickly when the first transistor is connected to the light emitting device 102, and since the off-state current of the second transistor is very low, when the circuit switch is controlled by using the second transistor as the switching transistor Tc, the leakage current can be reduced, thereby reducing power consumption and increasing the standby time of the device.

Alternatively, in other embodiments of the present application, the driving transistor Td in fig. 2a may be the second transistor, for example, the active layer of the driving transistor Td is IGZO, and the switching transistor Tc may be the first transistor, for example, the active layer of the switching transistor Tc is LTPS.

Note that the above description deals with an arrangement of an active layer of a transistor in the pixel circuit, taking the structure of the pixel circuit 101 as 2T1C as an example. In other embodiments of the present application, in order to eliminate the influence of the threshold voltage (Vth) of the driving transistor Td on the light emitting brightness of the light emitting device 102 and improve the uniformity of the brightness of the light emitting device, the pixel circuit is added with a compensation and initialization module, and at this time, the number of the switching transistors is increased, for example, in a 7T1C or 8T1C structure. Other structures of the pixel circuit 101 are not described in detail herein. As long as at least one first transistor (e.g., the active layer is LTPS) and one second transistor (e.g., the active layer is IGZO) in the pixel circuit 101 can be ensured. For convenience of description, the pixel circuit 101 is exemplified as having a structure of 2T1C, and the driving transistor Td in the pixel circuit 101 is the first transistor (for example, the active layer is LTPS), and the switching transistor Tc is the second transistor (for example, the active layer is IGZO).

The structure of the display panel 100 having the pixel circuit 101 described above, i.e., the pixel circuit 101 including a first transistor (e.g., the active layer is LTPS) and a second transistor (e.g., the active layer is IGZO) will be described in detail below.

As shown in fig. 2b (a cross-sectional view taken along a dotted line O-O in fig. 1 b), the display panel 100 may include a substrate 201, and a first transistor (e.g., an active layer is LTPS) 202 and a second transistor (e.g., an active layer is IGZO) 203 disposed on the substrate 201.

In an embodiment of the present application, the material constituting the substrate 201 may include a hard material, such as at least one of glass, sapphire, or a metal material. Alternatively, the material constituting the substrate 201 may further include a flexible material, such as a high molecular polymer material.

The first transistor 202 acts as a driving transistor Td as shown in fig. 2 a. The second pole, e.g., the drain d, may be coupled to the anode (anode, 216) of the light emitting device 102, so that the anode 216 of the light emitting device 102 is in contact with the second pole, e.g., the drain d (i.e., the one in which 219 is located) of the first transistor 202, as shown in fig. 2 b. In addition, the light emitting device 102 includes a light emitting layer 217 and a cathode 218 which are sequentially disposed on the anode 216. In addition, the display screen 100 also includes a Pixel Definition Layer (PDL) 215. The pixel defining layer 215 has a plurality of hollow structures 225. One of the light emitting devices 102 may be disposed in one hollow structure 225.

The first transistor 202 includes a gate, a first electrode (e.g., a source s), a second electrode (e.g., a drain d), and an active layer AL. In some embodiments of the present application, as shown in fig. 2b, the first gate electrode 222 of the first transistor 202 and the active layer 212 have a first gate insulating layer 205 (e.g., a SiOx layer of silicon oxide) therebetween, and the first gate electrode 222 is disposed further away from the substrate 201 relative to the first gate insulating layer 205. Therefore, in fig. 2b, the first transistor 202 is a top-gate transistor. In addition, the first passivation layer 206, the second passivation layer 207 and the second gate insulating layer 208 sequentially cover the first gate electrode 222. The first passivation layer 206 is made of silicon nitride (SiNx), and the second passivation layer 207 is made of silicon oxide (SiOx).

Similarly, since the second gate insulating layer 208 is provided between the active layer 213 and the second gate 223 of the second transistor 203 and the active layer 213 of the second transistor 203 is close to the substrate 201, the second transistor 203 is also a top gate transistor.

The material of the first gate electrode 222 and the second gate electrode 223 may be molybdenum (Mo), titanium/aluminum/titanium alloy (Ti/Al/Ti), (molybdenum/aluminum/molybdenum alloy) Mo/Al/Mo, titanium (Ti), or other metal materials.

As can be seen from the above, the active layer 212 of the first transistor 202 is made of polysilicon, and in order to improve the electrical performance of the first transistor 202, a hydrogenation process (for example, a solid diffusion method, using silicon nitride (i.e., the first passivation layer 206) as a hydrogenation source, using high temperature to diffuse hydrogen ions into the active layer 212) is usually adopted, and hydrogen ions are used to fill unsaturated bonds or unbound bonds in the polysilicon of the active layer 212 of the first transistor 202, so as to reduce the number of unstable states in the polysilicon, thereby improving the electrical mobility, improving the uniformity of the threshold voltage, and the like.

The active layer 213 of the second transistor 203 is made of semiconductor oxide, and hydrogen ions may damage the active layer 213 of the second transistor 203, so that the forbidden bandwidth of the active layer 213 of the second transistor 203 is reduced, and even the active layer is failed. Therefore, in order to prevent the hydrogen ions in the first transistor 202 from diffusing into the active layer 213 of the second transistor 203, in the embodiment of the present application, the display panel 100 may further include the isolation portion 204 disposed on the substrate 201.

The isolation portion 204, as shown in fig. 2b, may include an isolation base 224 and an isolation wall 214 surrounding the isolation base 224. The isolation wall 214 penetrates at least the first gate insulating layer 205 and the first passivation layer 206, and at least a portion of the second gate insulating layer 208 is located within the isolation wall 214. Since the active layer 213 of the second transistor 203 is located on the side of the second gate insulating layer 208 close to the substrate 201, the active layer 213 of the second transistor 203 is disposed in the recess formed by the isolation wall 214 and the isolation base 224. However, as can be seen from the above, the active layer 212 of the first transistor 202 adjacent to the second transistor 203 is disposed outside the recess formed by the isolation wall 214 and the isolation substrate 224. As such, on the one hand, the isolation barriers 214 can not only block the hydrogen ions in the active layer 212 of the first transistor 202 from diffusing into the active layer 213 of the second transistor 203, but also block the hydrogen ions in the silicon nitride of the first passivation layer 206 from diffusing into the active layer 213 of the second transistor 203 when the active layer 212 of the first transistor 202 is hydrogenated by using a solid state diffusion method (e.g., using silicon nitride (e.g., the first passivation layer 206) as a hydrogenation source and using a high temperature to diffuse the hydrogen ions into the active layer 212), because the first passivation layer 206 also has a high content of hydrogen ions. Thereby preventing damage of the active layer 213 of the second transistor 203 by hydrogen ions. Thus, when the pixel circuit 101 includes both the LTPS transistor and the IGZO transistor, since the IGZO transistor has an extremely low off-state current as compared with the LTPS transistor, power consumption can be reduced when low-frequency driving is performed (for example, when the IGZO transistor is applied to a display screen of a mobile phone, 1Hz driving can be achieved, and when the IGZO transistor is applied to a device using all LTPS in the

pixel circuit

101, 15% power consumption can be reduced), and standby time can be prolonged (for example, when the IGZO transistor is applied to a wearable product, one month of ultra-long standby can be achieved).

On the other hand, the isolation wall 214 at least separates the first gate insulating layer 205 (e.g., siOx) from the first passivation layer 206 (SiNx), which can prevent stress concentration caused by an excessively large area of the inorganic oxynitride material, thereby preventing the problem of internal fracture when the display panel is bent.

In addition, in some embodiments of the present application, the display panel 100 may further include a third passivation layer 210 covering the second gate insulating layer 208, wherein a material constituting the third passivation layer 210 may include silicon oxide (SiOx), and since the third passivation layer 210 covers a surface of the second transistor 203 and the second gate electrode 223 is also located on a side of the active layer 213 of the second transistor 203 away from the substrate 201, the third passivation layer 210 and the second gate electrode 223 may further be used to block hydrogen ions in air from diffusing into the active layer 213 of the second transistor 203 during a production process, so as to avoid damage to the active layer 213 of the second transistor 203.

The structure of the display panel 100 having the spacer 204 will be described below by way of example.

Example 1

In this example, the display panel 100 is a flexible display panel, and as shown in fig. 3, the material constituting the substrate 201 includes an organic material, such as Polyimide (PI). The display panel 100 further includes a first barrier layer 301 (e.g., silicon oxide, siOx), a first stress relief layer 302 (e.g., PI), and a second barrier layer 303 (e.g., silicon oxide, siOx) sequentially disposed on the substrate 201.

In some embodiments of the present application, the process of manufacturing the display screen 100 having the above-mentioned spacer 204 structure is as follows:

first, as shown in fig. 4a, a first barrier layer 301 is formed on a substrate 201 by Chemical Vapor Deposition (CVD), and then an isolation base 224 is formed on a surface of the first barrier layer 301 by Physical Vapor Deposition (PVD).

Then, a first stress release layer 302 is coated on the isolation base 224 by a coating process, and then a second barrier layer 303 is formed on the substrate on which the first stress release layer 302 is formed by a CVD process. It should be noted that the isolation base 224 may be disposed in any layer between the substrate 201 and the second barrier layer 303, and for convenience of description, the isolation base 224 is disposed between the first barrier layer 301 and the first stress relief layer 302 in this example.

Next, an active layer 212 of the first transistor 202 is formed on a surface of the second barrier layer 303 on a side away from the substrate 201. Then, the active layer 212 of the first transistor 202 is covered with the first gate insulating layer 205, and then the first gate 222 is formed on the surface of the first gate insulating layer 205 away from the substrate 201 by a PVD process. Then, a first passivation layer 206 is covered on the first gate electrode 222.

In this case, as shown in fig. 4b, a recess 228 may be formed at one side (e.g., right side) of the first transistor 202 using a dry etching process. The first stress release layer 302 may be etched to a position on a side of the first stress release layer 302 away from the substrate 201 by using a fully transparent mask, and then the first stress release layer 302 in the groove 228 is retained by using a semi-transparent mask, and the position where the isolation wall 214 is located is etched and communicated with the isolation base 224. Then, by a PVD process, the isolation walls 214 are formed on the sidewalls of the recess 228, and the isolation walls 214 are electrically connected to the isolation base 224.

The material of the isolation portion 204 may be titanium/aluminum/titanium (Ti/a/lTi), molybdenum/aluminum/molybdenum (Mo/Al/Mo), molybdenum (Mo), copper (Cu), etc., wherein the materials of the isolation base 224 and the isolation wall 214 may be the same or different.

Since the isolation substrate 224 is made of a metal material, as shown in fig. 3, the active layer 213 of the second transistor 203 needs to be isolated from the isolation substrate 224 by at least one insulating layer. In some embodiments of the present application, as shown in fig. 3, the second passivation layer 207 and the first stress relief layer 302 are between the active layer 213 of the second transistor 203 and the isolation substrate 224. Therefore, as shown in fig. 4b, in forming the recess 228, in the case of ensuring that the isolation wall 214 is electrically connected to the isolation substrate 224, at least a portion of the second barrier layer 303, the first gate insulating layer 205 and the first passivation layer 206 at the bottom of the recess 228 may be etched, thereby insulating the active layer 213 from the isolation substrate 224 through the second passivation layer 207 and the first stress relief layer 302.

It should be further noted that when the recess 228 is formed on one side (for example, the right side) of the first transistor 202 by using a dry etching process, in the case that insulation between the active layer 213 of the second transistor 203 and the isolation substrate 224 is satisfied, the second blocking layer 303 is further required to be disposed on the outer surface of the isolation barrier 214 away from the active layer 213 of the second transistor 203 (as shown in fig. 4 b), and since the thickness of the second blocking layer 303 is generally larger than the thicknesses of the first passivation layer 206 and the second passivation layer 207, when the second blocking layer 303 is disposed on the outer surface of the isolation barrier 214 away from the active layer 213 of the second transistor 203, the active layer 213 of the second transistor 203 can be made lower than the active layer 212 of the first transistor 202, so as to better block hydrogen ions from diffusing into the active layer 213 of the second transistor 203. Alternatively, the portion of the second barrier layer 303, which is located at the isolation wall 214 and close to the active layer 213 of the second transistor 203, may have a first thickness smaller than a second thickness of the portion of the second barrier layer 303, which is located at the isolation wall 214 and far from the active layer 213 of the second transistor 203, wherein the thickness is a length in a direction in which the second barrier layer 303 grows when the second barrier layer 303 is deposited on the substrate 201. At this time, the first thickness may be adjusted to satisfy both the insulation between the active layer 213 of the second transistor 203 and the isolation substrate 224 and the condition that the active layer 213 of the second transistor 203 is lower than the active layer 212 of the first transistor 202, so as to better block the diffusion of hydrogen ions into the active layer 213 of the second transistor 203.

Next, as shown in fig. 4c, a second passivation layer 207 and a second gate insulating layer 208 are sequentially formed on a surface of the first passivation layer 206 on a side away from the substrate 201 by using a CVD process. At this time, the second passivation layer 207 and a portion of the second gate insulating layer 208 are located within the isolation wall 214. Thereafter, the active layer 213 and the second gate electrode 223 of the second transistor 203 are formed on both sides of the second gate insulating layer 208, respectively, by the same process as the first transistor 202.

Then, a third passivation layer 210 is formed on a surface of the second gate insulating layer 208 on a side away from the substrate 201 using a CVD process, and then a source electrode s and a drain electrode d are formed on both ends of the active layer 212 of the first transistor 202 and the active layer 213 of the second transistor 203 by a PVD process, respectively.

Furthermore, in fig. 3, in order to ensure the insulation between the active layer 213 of the second transistor 203 and the isolation substrate 224, the second passivation layer 207 and the first stress relief layer 302 are provided between the active layer 213 of the second transistor 203 and the isolation substrate 224, and in other embodiments of the present application, as shown in fig. 4d, only the second passivation layer 207 may be provided between the active layer 213 of the second transistor 203 and the isolation substrate 224. At least a portion of the second barrier layer 303, the first gate insulating layer 205, the first passivation layer 206 and the first stress relief layer 302 at the bottom of the groove 228 may be etched when the groove 228 is formed, thereby insulating the active layer 213 from the isolation substrate 224 through the second passivation layer 207. At this time, the second barrier layer 303 is disposed on the outer surface of the active layer 213 of the isolation barrier 214 away from the second transistor 203. It should be noted that, in this example, other manufacturing processes are the same as those described above, and are not described here again.

In order to ensure insulation between the active layer 213 of the second transistor 203 and the isolation substrate 224, in other embodiments of the present application, as shown in fig. 4e, there may be a first stress relief layer 302, a second passivation layer 207 and a portion of the second barrier layer 303 between the active layer 213 of the second transistor 203 and the isolation substrate 224 (compared to the solution described in fig. 3, there may be a portion of the second barrier layer 303 between the active layer 213 of the second transistor 203 and the isolation substrate 224). When the groove 228 is formed, a portion of the second barrier layer 303, the first gate insulating layer 205, and at least a portion of the first passivation layer 206 at the bottom of the groove 228 may be etched so that the active layer 213 isolation substrate 224 is insulated from each other by the first stress relief layer 302, the second passivation layer 207, and a portion of the second barrier layer 303. In this case, the second barrier layer 303 is a case where a portion of the second barrier layer 303, which is located at the isolation wall 214 and close to the active layer 213 of the second transistor 203, has a first thickness smaller than a second thickness of a portion of the second barrier layer 303, which is located at the isolation wall 214 and far from the active layer 213 of the second transistor 203. It should be noted that, in this example, other manufacturing processes are the same as those described above, and are not described here again.

In other embodiments of the present application, as shown in fig. 5a, the isolation wall 214 may further penetrate the second passivation layer 207, and at this time, the process of manufacturing the display panel 100 having the above-mentioned isolation portion 204 structure is as follows:

a first barrier layer 301, a first stress release layer 302, a second barrier layer 303, an active layer 212 of the first transistor 202, a first gate insulating layer 205, a first passivation layer 206, and a second passivation layer 207 are sequentially formed on the substrate 201, and the formation processes of the above layers are the same as those described above, and are not described herein again. Next, a groove 228 is formed on one side (e.g., the right side) of the first transistor 202 using a dry etching process on the substrate on which the second passivation layer 207 is formed.

As can be seen from the above, what layers need to be etched inside the recess 228 at least satisfy the following conditions: the active layer 213 of the second transistor 203 is insulated from the isolation base 224, and the second barrier layer 303 is disposed on the outer surface of the isolation wall 214 away from the active layer 213 of the second transistor 203, or the active layer 213 of the second transistor 203 is insulated from the isolation base 224, and a portion of the second barrier layer 303, which is located at the isolation wall 214 and close to the active layer 213 of the second transistor 203, has a first thickness smaller than a second thickness of a portion of the second barrier layer 303, which is located at the isolation wall 214 and away from the active layer 213 of the second transistor 203, and the active layer 213 of the second transistor 203 can be made lower than the active layer 212 of the first transistor 202 by adjusting the size of the first thickness.

In fig. 5b, at least a portion of the second barrier layer 303, the first gate insulating layer 205, the first passivation layer 206 and the second passivation layer 207 at the bottom of the recess 228 is etched during the formation of the recess 228, wherein the active layer 213 is insulated from the isolation substrate 224 by the first stress relief layer 302, and the second barrier layer 303 is provided on the isolation wall 214 away from the outer surface of the active layer 213 of the second transistor 203. Regarding other setting manners, as described above, details are not repeated here.

Next, a second gate insulating layer 208 is formed on a surface of the second passivation layer 207 on a side away from the substrate 201 by using a CVD process. At this time, a portion of the second gate insulating layer 208 is located within the isolation wall 214. The subsequent processes are the same as those described above, and are not described herein again.

For convenience of description, the isolation wall 214 penetrating the first gate insulating layer 205 and the first passivation layer 206 is used as an example for description.

As shown in fig. 2a, when the driving transistor Td is turned on, a current path is formed between the first voltage VDD and the second voltage VSS, so that the driving current generated by the driving transistor Td can flow into the light emitting device 102 to drive the light emitting device 102 to emit light. In this case, in order to supply the above-mentioned first voltage VDD to the pixel circuit 101 in each sub-pixel 103, the display screen further includes a common electrode layer 304 as shown in fig. 6a, and the common electrode layer 304 can be coupled to the source s of the driving transistor Td in each pixel circuit 101, thereby supplying the above-mentioned first voltage VDD to each pixel circuit 101.

The manner of disposing the common electrode layer 304 will be described in detail below.

In this example, as shown in fig. 6a, the common electrode layer 304 may be disposed between the first barrier layer 301 and the first stress relief layer 302. As can be seen from the above, the isolation substrate 224 in the isolation portion 204 is located between the first barrier layer 301 and the first stress releasing layer 302, and the isolation substrate 224 is made of a metal material. Therefore, in order to simplify the manufacturing process, the isolation substrate 224 and the common electrode layer 304 may be disposed in the same layer and the same material, and are integrated. In this way, the preparation of the common electrode layer 304 may be completed while the isolation substrate 224 is fabricated.

The "same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process (e.g., a coating process) and then performing a patterning process by using the same mask. Depending on the specific pattern, the same patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses.

Therefore, as shown in fig. 6a, the display screen 100 may further include a common electrode layer 304, wherein the common electrode layer 304 is located between the first barrier layer 301 and the first stress release layer 302, and is connected to the first barrier layer 301 and the first stress release layer 302.

The common electrode layer 304 may be formed of a metal material layer, or the common electrode layer 304 may include a metal material layer and a surface oxide material layer stacked on the metal material layer. For example: titanium/aluminum/titanium (Ti/Al/Ti), molybdenum/nickel/copper (Mo/Ni/Cu), copper (Cu), stainless steel (SUS), indium Tin Oxide (ITO), a surface oxide layer thereof, and the like.

In order to realize that the common electrode layer 304 is coupled to the source s of the driving transistor Td (i.e. the first transistor 202 or the second transistor 203, for example, the first transistor in fig. 6 a), the display panel 100 may further include a first via hole 305 and a second via hole 306. In some embodiments of the present application, the first via hole 305 sequentially penetrates through the first stress relieving layer 302, the second barrier layer 303, the first gate insulating layer 205 and the first passivation layer 206, a first end E of the first via hole 305 is coupled to the common electrode layer 304, and a second end (i.e., an end opposite to the end E) of the first via hole 305 is coupled to a first electrode (not shown) of the first transistor 202 or the second transistor 203. In addition, the first via hole 305 may include a first metal conductive layer 307, and the first metal conductive layer 307 and the isolation wall 214 are made of the same material.

In addition, a first end F of the second via 306 is coupled to a second end (i.e., an end opposite to the end E) of the first via 305, a second end (i.e., an end opposite to the end F) of the second via 306 is coupled to a first pole of the first transistor 202 or the second transistor 203 (not shown), and the second via 306 may include a second metal conductive layer 308, and the second metal conductive layer 308 is the same material as the first pole of the first transistor 202.

The material constituting the first metal conductive layer 307 may be titanium/aluminum/titanium (Ti/Al/Ti), molybdenum/aluminum/molybdenum (Mo/Al/Mo), molybdenum (Mo), copper (Cu), or the like. The first metal conductive layer 307 and the isolation wall 214 penetrate the same layer (e.g., the first stress relief layer 302, the second barrier layer 303, the first gate insulating layer 205, and the first passivation layer 206), so that the first metal conductive layer 307 and the isolation wall 214 can be made of the same material at the same layer, and thus, the first metal conductive layer 307 can be formed at the same time by using the same mask during the manufacturing of the isolation wall 214, which simplifies the process.

In addition, the material of the second metal conductive layer 308 may be titanium/aluminum/titanium (Ti/Al/Ti), copper (Cu), molybdenum/nickel/copper (Mo/Ni/Cu), molybdenum/aluminum/molybdenum (Mo/Al/Mo), etc., and the second metal conductive layer 308 and the film layer (e.g., the second passivation layer 207, the second gate insulating layer 208, and the third passivation layer 210) penetrating through the first electrode (or the second electrode) of the first transistor 202 are the same, so that the second metal conductive layer 308 and the first electrode (or the second electrode) of the first transistor 202 may be made of the same material, and thus, the same mask may be used to form the second metal conductive layer 308 at the same time when the first electrode (or the second electrode) of the first transistor 202 is fabricated, thereby simplifying the process.

Secondly, dividing the via hole into the first via hole 305 and the second via hole 306 can reduce the difficulty of the process.

As can be seen from the above, in the embodiment of the present application, the common electrode layer 304 is disposed on a side of the transistor TFT close to the substrate 201, and is not on the same layer as a source/drain (S/D), which can reduce a voltage drop (IR drop), avoid crosstalk of data lines, save a wiring space of the data lines, and improve a resolution, and secondly, the common electrode layer 304 is not located at an upper stacked position, which reduces a thickness of a stack, and facilitates continuous bending of the display screen. Third, since the common electrode layer 304 is made of a metal material and electrically connected to the first electrode of the first transistor 202, an external electric field and electrostatic discharge (ESD) can be shielded from entering the display panel 100, so as to improve the stability of the light emitting device 102, and then, since the hardness of the metal material is greater than that of the inorganic material or the organic material, when the common electrode layer 304 is added on the substrate 201, the common electrode layer 304 can support the display panel, so that the stress of the display panel is uniform for the flexible display panel, and a continuous curling effect is achieved. Meanwhile, the problems of magic marks and poor broken bright sheets in the production process are solved. Finally, the common electrode layer 304 can also shield the active layer 212 of the first transistor 202 and the active layer 213 of the second transistor 203 from damage caused by processes such as Laser Lift Off (LLO) and ambient light.

In order to shield the active layer 212 of the first transistor 202 and the active layer 213 of the second transistor 203, the common electrode layer 304 may be a whole thin film layer covering the substrate 201 or a thin film layer with a certain hollow pattern. The hollowed-out pattern may comprise a grid pattern, a mesh pattern, etc. However, when the common electrode layer 304 has a hollow pattern, at least the following requirements must be satisfied: the vertical projection of the active layer 212 of the first transistor 202 on the substrate 201 is within the range of the vertical projection of the common electrode layer 304 on the substrate 201, and the vertical projection of the active layer 213 of the second transistor 203 on the substrate 201 is within the range of the vertical projection of the common electrode layer 304 on the substrate 201.

As can be seen from fig. 2a, in order to maintain the gate voltage of the driving transistor Td (i.e., the first transistor 202) so that the gate voltage of the driving transistor Td (i.e., the first transistor 202) can be stabilized within one image frame, the display screen 100 may further include a storage capacitor Cst, and thus, in some embodiments of the present application, as shown in fig. 6a, the storage capacitor Cst may further include an insulated first electrode a and a second electrode B. The first electrode a is located on a side surface of the first gate insulating layer 205 away from the substrate 201, and the first electrode a and the gate 222 of the first transistor 202 are made of the same material in the same layer. In addition, the second electrode B is located on a side surface of the second passivation layer 207 away from the substrate 201, the second electrode B is coupled to the first transistor 202, and the second electrode B and the gate 222 of the second transistor 203 are made of the same material in the same layer. In this case, the second electrode B is an upper plate of the storage capacitor Cst, and the first electrode a is a lower plate of the storage capacitor.

Therefore, the first electrode a and the second electrode B of the storage capacitor Cst may be respectively fabricated using the same mask while the first gate 222 of the first transistor 202 and the second gate 223 of the second transistor 203 are respectively fabricated, thereby simplifying the process.

It should be noted that, the positions of the first electrode a and the second electrode B in the storage capacitor Cst are not limited in the present application, and may be set in different stacked layers according to requirements (for example, the first electrode a may be disposed on the first gate insulating layer 205 and may be made of the same material as the active layer 212 of the first transistor 202), where the first electrode a and the second electrode B are not in the same stacked layer.

Alternatively, in other embodiments of the present application, as shown in fig. 6B, the storage capacitor Cst may include the first electrode a and the second electrode B, and the third electrode C between the first electrode a and the second electrode B. The third electrode C is located on a side surface of the third passivation layer 210 away from the substrate 201, and covers the second electrode B. The third electrode C is made of the same material as the first electrode of the first transistor 202. The display screen 100 further includes a third via hole D penetrating the second electrode B, and the third electrode C is coupled to the first electrode a through the third via hole D. At this time, the third electrode C is electrically connected to the first electrode a and is equivalent to one electrode of the storage capacitor Cst, and the second electrode B is equivalent to the other electrode of the storage capacitor Cst, so that compared with the above scheme (the storage capacitor Cst only includes the first electrode a and the second electrode B), the relative area between the two electrodes of the storage capacitor Cst is increased, and the energy storage effect of the storage capacitor Cst is improved.

In the above, the first transistor 202 and the second transistor 203 are both of a top gate type as an example, in other embodiments of the present application, the first transistor 202 may also have a double gate structure, in which case, as shown in fig. 7a, the first transistor 202 may further include a third gate 309 in addition to the first gate 222.

At this time, the third gate electrode 309 is made of the same material as the common electrode layer 304 and is insulated therefrom. The third gate 309 is located on a side of the first gate 222 of the first transistor 202 close to the substrate of the substrate 201, and the first gate 222 of the first transistor 202 is insulated from the third gate 309. Therefore, the same mask can be used to form the third gate 309 during the fabrication of the common electrode layer 304, which simplifies the process, and the dual gates can increase the driving capability of the first transistor 202 compared to the single gate.

In other embodiments of the present application, the second transistor 203 may also have a double-gate structure, in which case, as shown in fig. 7b, the second transistor 203 includes a fourth gate 310 in addition to the first gate 222, and in this case, the fourth gate 310 and the common electrode layer 304 are made of the same material and are insulated. The fourth gate 310 is located on the side of the second gate 223 of the second transistor 203 close to the substrate of the substrate 201, and the second gate 223 of the second transistor 203 is insulated from the fourth gate 310. Based on this, the same mask can be used to form the second gate electrode when the common electrode layer is fabricated, which simplifies the process, and secondly, the dual gate can increase the driving capability of the second transistor 203 compared to the single gate.

Fig. 7a illustrates an example in which the first transistor 202 has a double-gate structure and the second transistor 203 has a top-gate structure, and fig. 7b illustrates an example in which the first transistor 202 has a top-gate structure and the second transistor 203 has a double-gate structure. In other embodiments of the present application, the first transistor 202 and the second transistor 203 may be both dual gate structures, and the present application is not limited thereto.

Example two

In this example, the display panel 100 is a flexible display panel, and as shown in fig. 8, the material constituting the substrate 201 includes an organic material. The display panel 100 further includes a first barrier layer 301, a first stress relief layer 302, and a second barrier layer 303 sequentially disposed on the substrate 201, wherein the active layer 212 of the first transistor 202 is disposed on a side surface of the second barrier layer 303 away from the substrate 201. In contrast to the example one, a connection layer 311 is present between the first barrier layer 301 and the first stress relief layer 302, wherein the connection layer 311 serves to increase the adhesion between the first barrier layer 301 and the first stress relief layer 302.

In this example, the common electrode layer 304 is located between the substrate 201 and the first barrier layer 301, and is connected to the substrate 201 and the first barrier layer 301, and as can be seen from the above, the common electrode layer 304 and the isolation base 224 may be made of the same material in the same layer, so that, as shown in fig. 8, the isolation base 224 is also located between the substrate 201 and the first barrier layer 301.

In this case, the isolation walls 214 may penetrate the first passivation layer 206 to the first barrier layer 301 to be electrically connected to the common electrode layer 304, and the active layer 213 of the second transistor 203 is insulated from the isolation substrate 224 by the first barrier layer 301, the connection layer 311, the first stress relief layer 302, and the second passivation layer 207. At this time, the second blocking layer 303 is disposed on the outer surface of the active layer 213 of the isolation barrier 214 away from the second transistor 203.

It should be noted that, regarding the setting of the insulating layer between the active layer 213 of the second transistor 203 and the isolation substrate 224, the present application is not limited, and it is only required that the insulating layer between the active layer 213 of the second transistor 203 and the isolation substrate 224 is satisfied, and the second barrier layer 303 is disposed on the outer surface of the isolation wall 214 away from the active layer 213 of the second transistor 203, or the insulating layer between the active layer 213 of the second transistor 203 and the isolation substrate 224 is satisfied, and a portion of the second barrier layer 303, which is located at the isolation wall 214 and close to the active layer 213 of the second transistor 203, has a first thickness smaller than a second thickness of a portion of the second barrier layer 303, which is located at the isolation wall 214 and far from the active layer 213 of the second transistor 203, and the size of the first thickness can be adjusted so that the active layer 213 of the second transistor 203 is lower than the active layer 212 of the first transistor 202. The specific setting method is the same as that described above, and is not described herein again.

In this example, the isolation wall 214 may also penetrate the second passivation layer 207, and the disposing method thereof is the same as that described above, and is not described herein again. In addition, the arrangement of the first transistor 202, the second transistor 203 and the storage capacitor Cst is the same as that described above, and is not described herein again.

Example three

In this example, the display panel 100 is a flexible display panel, and as shown in fig. 9, the material constituting the substrate 201 includes an organic material. The display panel 100 comprises a first barrier layer 301, a first stress relief layer 302 and a second barrier layer 303 which are sequentially arranged on a substrate 201, wherein an active layer 212 of a first transistor 202 is arranged on one side surface of the second barrier layer 303 far away from the substrate 201, and unlike the first example, a connecting layer 311 is arranged between the first barrier layer 301 and the first stress relief layer 302, wherein the connecting layer 311 is used for increasing the adhesive force between the first barrier layer 301 and the first stress relief layer 302.

In this example, the common electrode layer 304 is located between the first stress relieving layer 302 and the second barrier layer 303, and is connected to the first stress relieving layer 302 and the second barrier layer 303, as can be seen from the above, the common electrode layer 304 and the isolation substrate 224 are made of the same material in the same layer, so that the isolation substrate 224 is also located between the first stress relieving layer 302 and the second barrier layer 303 as shown in fig. 9.

In this case, the isolation walls 214 may penetrate the first passivation layer 206 to the first barrier layer 301, electrically connected to the common electrode layer 304, and the active layer 213 of the second transistor 203 is insulated from the isolation substrate 224 by the second passivation layer 207. At this time, the second blocking layer 303 is disposed on the outer surface of the active layer 213 of the isolation retaining wall 214 away from the second transistor 203.

It should be noted that, regarding the setting of the insulating layer between the active layer 213 of the second transistor 203 and the isolation substrate 224, the present application is not limited, and it is only required to satisfy that the active layer 213 of the second transistor 203 and the isolation substrate 224 are insulated, and the second barrier layer 303 is disposed on the outer surface of the isolation barrier 214 away from the active layer 213 of the second transistor 203, or the active layer 213 of the second transistor 203 and the isolation substrate 224 are insulated, and a portion of the second barrier layer 303, which is located at the isolation barrier 214 and close to the active layer 213 of the second transistor 203, has a first thickness smaller than a second thickness of a portion of the second barrier layer 303, which is located at the isolation barrier 214 and away from the active layer 213 of the second transistor 203, and the active layer 213 of the second transistor 203 can be lower than the active layer 212 of the first transistor 202 by adjusting the size of the first thickness. The specific setting method is the same as that described above, and is not described herein again.

In this example, the isolation wall 214 may also penetrate the second passivation layer 207, and the disposing method thereof is the same as that described above, and is not described herein again. In addition, the arrangement of the first transistor 202, the second transistor 203, and the storage capacitor Cst is the same as that described above, and therefore, the description thereof is omitted.

Example four

Unlike the example in which the display panel 100 is a rigid display panel, as shown in fig. 10, the material forming the substrate 201 includes an inorganic material, and the display panel 100 further includes a buffer layer 601 on the substrate 201.

In this example, the common electrode layer 304 is located between the substrate 201 and the buffer layer 601, and is connected to the substrate 201 and the buffer layer 601. As described above, the common electrode layer 304 and the isolation base 224 may be made of the same material in the same layer, so that the isolation base 224 is also located between the substrate 201 and the buffer layer 601 as shown in fig. 10.

In this case, the isolation walls 214 may penetrate the first passivation layer 206 to the first barrier layer 301, electrically connected to the common electrode layer 304, and the active layer 213 of the second transistor 203 is insulated from the isolation substrate 224 by the second passivation layer 207.

It should be noted that, regarding the setting of the insulating layer between the active layer 213 of the second transistor 203 and the isolation substrate 224, the present application is not limited, and it is only required that the insulating layer between the active layer 213 of the second transistor 203 and the isolation substrate 224 is satisfied, and the buffer layer 601 is disposed on the outer surface of the isolation wall 214 away from the active layer 213 of the second transistor 203, or the insulating layer between the active layer 213 of the second transistor 203 and the isolation substrate 224 is satisfied, and a portion of the buffer layer 601 located at the isolation wall 214 close to the active layer 213 of the second transistor 203 has a first thickness smaller than a second thickness of a portion of the buffer layer 601 located at the isolation wall 214 away from the active layer 213 of the second transistor 203, where the thickness is a length in a direction in which the buffer layer 601 grows when the buffer layer 601 is deposited on the substrate 201. The first thickness may be sized such that the active layer 213 of the second transistor 203 is lower than the active layer 212 of the first transistor 202. The specific setting method is the same as that described above, and is not described herein again.

In this example, the isolation wall 214 may also penetrate the second passivation layer 207, and the method of disposing is the same as that described above, and is not described herein again. In addition, the arrangement of the first transistor 202, the second transistor 203, and the storage capacitor Cst is the same as that described above, and therefore, the description thereof is omitted.

The embodiment of the present application further provides an electronic device, where the electronic device includes any one of the display screens described above, and the electronic device has the same technical effects as the display screen provided in the foregoing embodiment, and details are not repeated here.

The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A display screen, characterized in that the display screen comprises a plurality of sub-pixels; the display screen comprises:

substrate;

a light-emitting device, disposed on the substrate, and located in the sub-pixel;

a pixel circuit, disposed on the substrate and located in the sub-pixel; the pixel circuit is coupled with the light-emitting device; the pixel circuit includes a first transistor and a second transistor; the first transistor The active layer of the second transistor includes polysilicon; the active layer of the second transistor includes a semiconductor oxide;

an isolation part, disposed on the substrate and located in the sub-pixel; the isolation part includes an isolation base and an isolation barrier wall surrounding the isolation base; the active layer of the second transistor is provided in the groove formed by the isolation barrier wall and the isolation base; the isolation part is at least used to block hydrogen ions in the active layer of the first transistor from diffusing into the active layer of the second transistor;

Common electrode layer, the common electrode layer is located on the side of the first transistor and the second transistor close to the substrate; the first electrode of the first transistor or the second transistor and the common electrode The layers are coupled; the isolation base and the common electrode layer are of the same layer and the same material, and have an integrated structure.

2 . The display screen according to claim 1 , wherein the display screen further comprises a first gate insulating layer, a first passivation layer, a second passivation layer and a first gate insulating layer on the substrate. 3 . Two gate insulating layers; the material constituting the first passivation layer includes silicon nitride; the material constituting the second passivation layer includes silicon oxide;

The first gate insulating layer is located between the active layer of the first transistor and the first gate, and the active layer of the first transistor is close to the substrate; the first passivation layer and the second passivation layer covers the first gate;

The isolation barrier at least penetrates the first gate insulating layer and the first passivation layer; at least a part of the second gate insulating layer is located in the isolation barrier; the second gate insulating layer A layer is located between the active layer of the second transistor and the second gate, and the active layer of the second transistor is adjacent to the substrate.

3 . The display screen of claim 2 , wherein the isolation barrier wall further penetrates the second passivation layer. 4 .

4. The display screen according to any one of claims 1-3, wherein the common electrode layer comprises a metal material layer; or, the common electrode layer comprises a metal material layer and a metal material layer layered surface oxide material layers;

The vertical projection of the active layer of the first transistor on the substrate is located within the range of the vertical projection of the common electrode layer on the substrate;

The vertical projection of the active layer of the second transistor on the substrate is within the range of the vertical projection of the common electrode layer on the substrate.

5. The display screen according to any one of claims 1-3, wherein the first transistor further comprises a third gate; the third gate is located at the first gate of the first transistor one side close to the substrate; the first gate of the first transistor is insulated from the third gate;

The third gate of the first transistor and the common electrode layer are of the same layer and the same material and insulated.

6 . The display screen according to claim 1 , wherein the second transistor further comprises a fourth gate; the fourth gate is located at the second gate of the second transistor. 7 . one side close to the substrate; the second gate of the second transistor is insulated from the fourth gate;

The fourth gate of the second transistor and the common electrode layer are in the same layer and the same material, and are insulated.

7. The display screen according to any one of claims 1-3, wherein the material constituting the substrate comprises an organic material; the display screen further comprises a first barrier layer sequentially located on the substrate , a first stress release layer and a second barrier layer; the active layer of the first transistor is located on the side surface of the second barrier layer away from the substrate;

The common electrode layer is located between the first barrier layer and the first stress release layer, and is connected to the first barrier layer and the first stress release layer.

8. The display screen according to claim 7, wherein the display screen further comprises a first via hole;

In the case that the display screen further includes a first gate insulating layer, a first passivation layer, a second passivation layer and a second gate insulating layer sequentially located on the substrate, the first conduction A hole runs through the first stress release layer, the second barrier layer, the first gate insulating layer and the first passivation layer in sequence; the first end of the first via hole and the common the electrode layers are coupled to each other, and the second end of the first via hole is coupled to the first transistor or the first electrode of the second transistor;

The first through hole includes a first metal conductive layer; the isolation barrier and the first metal conductive layer are of the same layer and the same material.

9. The display screen according to claim 8, wherein the display screen further comprises a second via hole;

The first end of the second via hole is coupled with the second end of the first via hole; the second end of the second via hole is connected to the first transistor or the second transistor The first pole is coupled;

The second via hole includes a second metal conductive layer; the second metal conductive layer and the first electrode of the first transistor are of the same layer and the same material.

10. The display screen according to any one of claims 1-3, wherein the material constituting the substrate comprises an organic material; the display screen further comprises a first barrier layer sequentially located on the substrate , a connection layer, and a first stress release layer; the connection layer is used to connect the first barrier layer and the first stress release layer;

The common electrode layer is located between the substrate and the first barrier layer, and is connected to the substrate and the first barrier layer; or, the display screen further comprises a layer located on the first stressor a second barrier layer on the side of the release layer away from the substrate; the active layer of the first transistor is located on the surface of the second barrier layer away from the substrate; the common electrode layer is located on the second barrier layer A stress release layer is between the second barrier layer and connected with the first stress release layer and the second barrier layer.

11. The display screen according to claim 7, wherein,

The active layer of the second transistor is insulated from the isolation base, and the second barrier layer is disposed on the outer surface of the isolation barrier far from the active layer of the second transistor.

12. The display screen according to claim 10, wherein,

13. The display screen according to any one of claims 1-3, wherein the material constituting the substrate comprises an inorganic material;

The display screen further includes a buffer layer on the substrate; the common electrode layer is located between the substrate and the buffer layer, and is connected with the substrate and the buffer layer;

The active layer of the second transistor is insulated from the isolation base, and the buffer layer is disposed on the outer surface of the isolation barrier far from the active layer of the second transistor.

14. The display screen according to claim 2, wherein the pixel circuit further comprises a storage capacitor; the storage capacitor comprises an insulated first electrode and a second electrode;

The first electrode is located on a surface of the first gate insulating layer away from the substrate; the first electrode and the gate of the first transistor are of the same layer and the same material;

the second electrode is located on a surface of the second passivation layer away from the substrate; the second electrode is coupled with the first transistor; the second electrode is connected to the second transistor The gate is of the same layer and the same material.

15. The display screen according to claim 14, wherein the display screen further comprises a third passivation layer covering the second gate insulating layer;

The storage capacitor further includes a third electrode; the third electrode is located on a surface of the third passivation layer away from the substrate, and covers the second electrode; the third electrode is connected to the first The first pole of a transistor is of the same layer and the same material;

The display screen further includes a third conducting hole penetrating the second electrode; the third electrode is coupled to the first electrode through the third conducting hole.

16 . The display screen of claim 1 , wherein the first transistor is coupled to the light emitting device; the first transistor is used to provide a driving current to the light emitting device. 17 .

17. An electronic device, characterized by comprising the display screen according to any one of claims 1-16.