CN113054006A - Semiconductor device layout structure - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
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- 230000008569 process Effects 0.000 description 43
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- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
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- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
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- H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
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- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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Abstract
本发明公开了一种半导体器件布局结构，其可使半导体器件尺寸缩小，同时可确保半导体器件的电学性能，其包括衬底、布置于衬底上的源极区、漏极区、栅极区、连通源极区与漏极区的沟道、连接线，源极区、漏极区、栅极区均为主动区域，主动区域包括第一主动区域、第二主动区域，源极区、漏极区均包括若干间隔平行分布的第一主动区域，栅极区包括三个间隔平行分布的第二主动区域，且三个第二主动区域分别与源极区和漏极区的两侧端、中部垂直，连接线位于相邻两个第二主动区域之间，连接线与栅极区平行，与第一主动区域垂直相交，连接线的两端凸出于第一主动区域的两侧，或连接线位于第一主动区域的中部位置或边缘位置，第二主动区域的宽度为14nm。
The invention discloses a layout structure of a semiconductor device, which can reduce the size of the semiconductor device and at the same time can ensure the electrical performance of the semiconductor device, which comprises a substrate, a source region, a drain region and a gate region arranged on the substrate , The channel and connecting line connecting the source region and the drain region, the source region, the drain region and the gate region are all active regions, and the active region includes the first active region, the second active region, the source region, the drain region Each of the electrode regions includes a plurality of first active regions distributed in parallel at intervals, the gate region includes three second active regions distributed in parallel at intervals, and the three second active regions are respectively connected with the two side ends of the source region and the drain region, The middle is vertical, the connecting line is located between two adjacent second active regions, the connecting line is parallel to the gate region, and intersects perpendicularly with the first active region, and the two ends of the connecting line protrude from both sides of the first active region, or The connection line is located in the middle position or edge position of the first active region, and the width of the second active region is 14 nm.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device layout structure.
Background
The semiconductor refers to a material with electric conductivity between a conductor and an insulator at normal temperature, and is mainly used in the fields of integrated circuits, consumer electronics, communication systems, photovoltaic power generation, illumination, high-power voltage conversion and the like, and common semiconductor materials comprise silicon, germanium, gallium arsenide and the like. At present, a common semiconductor device is a field effect transistor, a metal-oxide semiconductor field effect transistor (MOSFET), which is a field effect transistor that can be widely used in analog circuits and digital circuits, and its working principle is that a specific voltage is applied to a port of a tube, electrons are sent from one end (source) to the other end (drain) through a channel, and the conduction or the shutdown of the communication is determined by a gate, so that the electrical performance of the tube is seriously affected by process parameters such as the length, width, thickness, layout structure, and the like of the gate, the source, and the drain.
In the conventional MOSFET structure, the gate length is as low as 20nm, and below 20nm, the current leakage is increased, the current control capability of the tube body is reduced, the problems of large current leakage, low current control capability and the like can be improved by the FinFET transistor (fin transistor) with the existing three-dimensional structure and the silicon transistor on the ultrathin insulating layer (UTB-SOI, namely FD-SOI transistor) based on the SOI, and a large amount of early electrical simulation results show that, simultaneously, the reduction of the thickness of the BOX and the thickness of the top silicon of the FD-SOI substrate can reduce the degree of Drain Induced Barrier Lowering (DIBL) of the transistor, the gate of the FDSOI planar transistor can be continuously scaled down to 14nm, however, the transistor structure of the prior art, in which the gate can be scaled down to 14nm, is lacking, and therefore a transistor is designed to be effectively scaled down, a semiconductor device layout structure for ensuring the electrical performance of the device while improving the transistor process is an urgent problem to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a semiconductor device layout structure, which can reduce the size of a semiconductor device, ensure the electrical performance and enable the semiconductor device to meet the requirements of process improvement and device efficiency improvement at the same time.
In order to achieve the purpose, the invention adopts the following technical scheme: a semiconductor device layout structure comprises a substrate, a source region, a drain region, a gate region and a channel, wherein the source region, the drain region and the gate region are arranged on the substrate, the channel is communicated with the source region and the drain region, the semiconductor device layout structure is characterized in that the source region, the drain region and the gate region are active regions, the active regions comprise a first active region and a second active region, the source region and the drain region respectively comprise a plurality of first active regions which are distributed in parallel at intervals, the gate region comprises three second active regions which are distributed in parallel at intervals, and the three second active regions are respectively vertical to the two side ends and the middle part of the source region and the drain region;
the semiconductor device is a FinFET transistor or an FDSOI transistor;
the connecting line is positioned between two adjacent second active regions, is parallel to the gate region and is vertically intersected with the first active region;
when the semiconductor device is a FinFET transistor, two ends of the connecting line protrude out of two sides of the first active region, and when the semiconductor device is an FDSOI transistor, the connecting line is positioned in the middle or edge position of the first active region;
the width of the second active region is 14 nm.
It is further characterized in that the method further comprises the steps of,
the first active area is strip-shaped, block-shaped, square, U-shaped or L-shaped;
the number of the first active regions is 1 to 1536;
the connecting line is strip-shaped or square;
when the connecting wire is strip-shaped, the connecting wire extends towards two sides, and the extending direction of the connecting wire is vertical to the extending direction of the source electrode region and the drain electrode region;
the distance between two adjacent second active regions is 90 nm;
the active regions comprise at least two groups, each group comprises two second active regions, each group comprises one, two or four first active regions, and the second active regions are in cross connection with the first active regions;
when the semiconductor device is a FinFET transistor and the first active region is in a strip shape, two second active regions in each group of active regions respectively cover and protrude out of the first active region;
the length of the connecting line is 48nm, 96nm or 192 nm;
when the semiconductor device is an FDSOI transistor and the first active region is in a block shape, the connecting line is positioned at the middle position or the edge of the first active region, and the width of the first active region is 48nm, 96nm or 192 nm.
After the structure is adopted, when the current of the gate region reaches the conduction current threshold of the channel, the source region and the drain region can be quickly conducted, and the length of the gate region is 14 nanometers, so that the size of the semiconductor device is greatly reduced by adopting the structure of the semiconductor device. The layout structure of the semiconductor device is detected, and the obtained electrical performance parameters can meet the performance requirements of the semiconductor device, so that the gate region width of the semiconductor device is greatly reduced compared with the existing semiconductor device with the gate region width of 20nm, and the electrical performance of the semiconductor device is ensured.
Drawings
Fig. 1 is a schematic top view of a first active region according to a first embodiment of the present invention;
fig. 2 is a schematic top view of a first active region according to a second, third or fourth embodiment of the present invention;
FIG. 3 is a schematic diagram of a top view of a semiconductor transistor of a FinFET transistor with 48nm, 96nm, or 192nm interconnect lines according to an embodiment of the present invention;
FIG. 4 is a schematic top view of a second embodiment of the present invention when the semiconductor transistor is an FDSOI transistor, the width of the first active region is 48nm, 96nm or 192nm, and the interconnect is located in the middle of the first active region;
FIG. 5 is a schematic top view of a third embodiment of the present invention, wherein the semiconductor transistor is an FDSOI transistor, the width of the first active region is 48nm, 96nm or 192nm, and the connecting lines are located at the middle (a), middle and edge (b) and edge (c) of the first active region;
FIG. 6 is a schematic top view of a fourth embodiment of the present invention when the semiconductor transistor is an FDSOI transistor, the width of the first active region is 48nm, 96nm or 192nm, and the length of the connecting line is the same as the width of the first active region;
FIG. 7 is a front view of the structure of any one of FIGS. 3 to 6 taken along the direction A-A;
fig. 8 is a schematic circuit diagram of a ring oscillator including a semiconductor device according to the first embodiment or the second embodiment;
FIG. 9 is a flowchart of a method for collecting electrical performance parameters of a semiconductor device based on the ring oscillator of FIG. 8;
fig. 10 is a flowchart of a method of analyzing electrical characteristics of the semiconductor device according to the first or second embodiment;
fig. 11 is a schematic top view of a semiconductor device in which a first active region of the invention is L-shaped (fig. 11A is the fifth embodiment, and fig. 11B is the sixth embodiment) or U-shaped (fig. 11c is the seventh embodiment);
fig. 12 is a schematic top view of a semiconductor device in a L-shape (fig. 11A ' is an eighth embodiment, and fig. 11B ' is a ninth embodiment) or a U-shape (fig. 11c ' is a tenth embodiment) of a first active region according to the present invention;
FIG. 13a is a graph showing the relationship between the gate region width, the electrical delay time, and the leakage current of the present invention;
FIG. 13b is a graph showing the relationship between the angle of the top angle of the oxide layer and the electrical property delay time and leakage current according to the present invention;
fig. 14 is a schematic front view of a cross-section of the direction B-B (including the substrate, the source region, the drain region, and the gate region) shown in any one of fig. 3-6 according to the present invention.
Detailed Description
Referring to fig. 1, 3 and 7, in a first embodiment, the semiconductor device is a FinFET transistor, the first active region has two semiconductor device layout structures, and the FinFET transistor includes a substrate 10, a source region 1, a drain region 2, a gate region 3, a channel connecting the source region 1 and the drain region 2, and connecting wires 4 distributed on the source region 1 and the drain region 2, where the source region 1, the drain region 2, and the gate region 3 are all active regions, the active regions include a first active region and a second active region, the first active region and the second active region are cross-connected, the second active region has a width of 14nm, the source region 1 and the drain region 2 are first active regions, the first active regions are spaced and distributed in parallel, the gate region 3 is a second active region, the second active region includes three and spaced and distributed in parallel, and the three second active regions are respectively connected to two side ends, a portion, and, The middle part is vertical;
the connecting lines 4 are strip-shaped, the connecting lines 4 are respectively arranged between two adjacent second active regions, the connecting lines 4 are parallel to the gate regions 3 and are vertically intersected with the first active regions, two ends of each connecting line protrude out of two sides of the first active regions, the distance between the two adjacent second active regions is 90nm, and the length of each connecting line 4 is 48nm (see fig. 3a), 96nm (see fig. 3b) or 192nm (see fig. 3C).
Referring to fig. 2 and fig. 4, in a second embodiment, the semiconductor device is an FDSOI transistor, the first active region has two semiconductor device layout structures, and the semiconductor device layout structures include a substrate, a source region 1, a drain region 2, a gate region 3 arranged on the substrate, a channel communicating the source region 1 and the drain region 2, and connecting lines 4 distributed on the source region 1 and the drain region 2, where the source region 1, the drain region 2, and the gate region 3 are active regions, the active regions include first active regions and second active regions, the width of the second active region is 14nm, the source region 1 and the drain region 2 are first active regions, the first active regions are distributed in parallel at intervals, the gate region 3 is a second active region, the second active regions include three active regions distributed in parallel at intervals, and the three second active regions are respectively perpendicular to two side ends and the middle portions of the source region;
in this embodiment, as shown in fig. 4, the length of the connection line 4 is smaller than the width of the first active region, the connection line 4 is in a strip shape, the connection line 4 is respectively disposed in the first active region between two adjacent second active regions, the connection line 4 is parallel to the gate region 3 and perpendicularly intersects with the first active region, the distance between two adjacent second active regions is 90nm, and the width of the first active region is 48nm (see fig. 4a), 96nm (see fig. 4b) or 192nm (see fig. 4 c);
in the third embodiment and the fourth embodiment, the source region 1, the drain region 2, and the gate region 3 are the same as the layout structure of the second embodiment, but the structure of the connection line 4 in the third embodiment and the fourth embodiment is not exactly the same as the second embodiment, and in the third embodiment, as shown in fig. 2 and 5, when the width of the first active region is 48nm, the length of the connection line 4 is equal to the width of the first active region (see fig. 5a), and when the width of the first active region is 96nm or 192nm, the length of the connection line 4 is smaller than the width of the first active region and the connection line 4 is located in the middle or at the edge of the first active region (see fig. 5b and 5 c); in the fourth embodiment, referring to fig. 2 and 6, the connection line 4 is a strip, the connection line 4 extends towards two sides, the extending direction of the connection line 4 is perpendicular to the extending direction of the source region and the drain region, and the length of the connection line 4 is equal to the width of the first active region.
Referring to fig. 7, in the first, second, third, or fourth embodiments, the gate region 3 is located in the middle of the substrate 1, a SPACE region (i.e., a SPACE charge region) is located between two sides of the gate region 3 and the substrate 1, a nickel silicide layer NiSi is distributed between the top end of the gate region 3 and the substrate 1, a metal layer TIN, a source region 1, and a drain region 2 (a first active region RX) are sequentially disposed between the gate region 3 and the substrate 1, the first active region RX is U-shaped, the nickel silicide layer NiSi and a connecting line 4 are sequentially disposed from bottom to top at the top end of two sides of the first active region RX, an M1 layer (M1 is a conductive metal layer) for communicating the connecting lines 4 at two sides is disposed at the top end of the connecting line 4, and the gate region 3 is made of the same material as that of an existing transistor (28.
Fig. 11 shows three other embodiments (fifth embodiment, sixth embodiment, seventh embodiment) of the semiconductor device according to the present invention, in the fifth embodiment and the sixth embodiment, the first active region of the source region 1 and the drain region 2 has an L-shape (fig. 11A and 11B) or a U-shape (fig. 11C), the longitudinal region of the first active region of the source region and the drain region in fig. 11A is parallel to the channel (the channel on both sides of the gate region) and has a distance a, the longitudinal region of the first active region in fig. 11B is parallel to the channel and has a distance B, a > B, and the first active region in the seventh embodiment includes two longitudinal regions parallel to the channel, the distance between the longitudinal region and the channel is C, a > C > B;
fig. 12 shows three other embodiments (an eighth embodiment, a ninth embodiment, and a tenth embodiment) of the semiconductor device according to the present invention, where the structures of the first active region and the channel (the channel on both sides of the gate region) in the eighth embodiment (fig. 12A) and the ninth embodiment (fig. 13B) are substantially the same as those in the fifth embodiment and the sixth embodiment, but in the eighth embodiment and the ninth embodiment (fig. 12C), the inner corner of the first active region is arc-shaped, and in the tenth embodiment, both the inner corners of the first active region are arc-shaped.
The ring oscillator is a differential ring oscillator and comprises a switch S, a semiconductor device combination, a delay circuit and an amplifier, wherein the delay circuit is connected with the input end of the amplifier in parallel, the output end of the amplifier is a signal output end, the semiconductor device combination comprises 101 semiconductor devices Stage0 and Stage1 … … Stage100 which are connected in series, and the delay circuit comprises four latches which are connected in series; the switch is used for controlling the on or off of current, the current is bias current generated by a voltage source, the delay circuit is used for generating a differential signal to the next delay Stage, the delay circuit is used for reducing the frequency, for example, the frequency of the output end of the semiconductor device combination is reduced from 100HZ to 5HZ, so that the electrical performance parameters of the semiconductor devices Stage0 and Stage1 … … Stage100 can be measured, and the amplifier Buffer is used for amplifying the voltage signal and outputting the voltage signal through the signal output end.
The sensitivity analysis is carried out based on the process parameters and the electrical performance parameters of the semiconductor device, and the analysis method comprises the following steps:
s1, measuring and obtaining process parameters of the semiconductor device, wherein the process parameters comprise the Gate region Width (Gate Width), the TOP angle (TOP Fin angle), the NiSi layer Thickness (SD maximum) at two sides of a source region and a drain region, the Depth (SD Depth) of the source region and the drain region, the Thickness (Gate-Space-1Thickness) of the Space at two sides of the Gate region, the Length (Gate Length) of the Gate region, the Thickness (High-K Thickness) of a High-K insulating layer and the Height (Gate Height) of the Gate region, and the process parameters are obtained by measuring the existing optical device in the processing process of the semiconductor device;
s2, measuring and acquiring electrical performance parameters of the semiconductor device based on the ring oscillator, wherein the electrical performance parameters comprise Delay time Delay and leakage current IDDQ; acquiring electrical performance parameters of the semiconductor device by controlling the ring oscillator and the output signal indication of the signal output end of the ring oscillator, and measuring the conduction current and the frequency of the semiconductor device when the semiconductor device is combined and conducted when the switch is turned on; when the switch is turned off, the semiconductor device combination is turned off, and the leakage current is measured. The delay circuit in the ring oscillator has the function of reducing the frequency, so that the frequency output by the combined output end of the semiconductor device is reduced, and the electrical performance parameters of the semiconductor device can be conveniently measured;
s3, carrying out sensitivity analysis on the electrical performance of the semiconductor device:
s31, correlating the electrical performance parameters with the corresponding process parameters to construct a correlation model;
calculating the covariance cov (IK) of the correlation model of the process parameters and the electrical property parameters according to the covariance formula1、IK2)，
cov(IK1、IK2)＝E[(IK1-k1)(IK2-k2)]；
Wherein, IK1Indicating a key process parameter, IK2Representing a key electrical property parameter, k1Is a key workerMean value of the technological parameters, k2Is the mean value of the key electrical performance parameters.
Correlation coefficient corr (IK) of correlation model is calculated based on covariance1,IK2)：
S32, analyzing the sensitivity of each correlation model, and obtaining a sensitivity analysis result according to the correlation coefficient of the correlation model;
s33, sorting the process parameters according to the magnitude of the correlation coefficients based on the sensitivity analysis result;
s34, determining key process parameters according to the sequencing result: the correlation coefficient is large, which indicates that the process parameters are greatly influenced by the electrical performance parameters, so that the process parameters with large correlation with the electrical performance parameters are determined as key process parameters;
s4, performing similarity test on the key process parameters by adopting a width method:
s41, performing cluster analysis on the key process parameters based on the database of machine learning, and classifying the key process parameters with similar or same characteristics according to groups;
s42, the width method is to compare the classified key process parameters in the same group with standard characteristic parameters in a pre-established database, for example, compare the width of the gate region in the process parameters measured in the processing process with the width of the standard gate region in the database, and calculate the relevance between the key process parameters and the standard characteristic parameters in each group according to the covariance formula:
calculating the covariance of the key process parameters and the standard characteristic parameters according to a covariance formulacov(IL1，IL2)，
Wherein IL1Representing a key process parameter, IL2Represents a key electrical property parameter, u1Is the mean value of the key process parameter, u2Is the mean value of the key electrical performance parameters.
Calculating correlation coefficient corr (IL) of key process parameter and standard characteristic parameter based on covariance1，IL2)，
S5, according to the correlation coefficient, screening out important key process parameters, namely determining the important key process parameters according to the correlation between the key process parameters and the standard characteristic parameters, wherein the smaller the correlation is, the larger the difference between the key process parameters and the standard characteristic parameters is, the more important the key process parameters are, namely, the important process variation parameters are.
And judging whether the layout structure of the semiconductor device is reasonable or not and judging whether the process parameters meet the performance requirements in the processing process or not through the process variation parameters obtained by the sensitivity analysis. The layout structure of the semiconductor device of the present application may also be analyzed and determined by a process analysis method in the prior art, the correlation between the process parameters (gate region width, top angle, width, depth of the source region and the drain region, thickness of the NiSi layer on both sides of the source region and the drain region, length of the gate region, thickness of the High-K insulating layer, height of the gate region, etc.) and the electrical performance parameters (Delay time, leakage current, etc.) of the semiconductor device may be obtained by the sensitivity analysis, as shown in fig. 13a and 13b, the horizontal axis respectively represents the Space thickness on both sides of the gate region and the gate region length, and the vertical axis respectively represents the Delay time of the electrical performance parameters on both sides of the gate region, The leakage current IDDQ, the curve a represents the variation curve of the Delay time Delay with the increasing Space thickness, the curve B represents the variation curve of the leakage current IDDQ with the increasing process parameter gate region length, the circles represent the Delay time Delay and the square points represent the leakage current IDDQ, as can be seen from fig. 13a, the larger the process parameter Space thickness, the lower the Delay time Delay, and the larger the leakage current IDDQ, as can be seen from fig. 13B, the larger the process parameter gate region length, the lower the Delay time Delay, and the higher the leakage current IDDQ, indicating that the electrical performance parameters Delay time Delay, leakage current IDDQ have a greater correlation with the process parameters Space thickness, and gate region length, and as can be seen from fig. 13a and 13B, the circles coincide with the curve a, or are arranged adjacent to the curve a, the squares coincide with the curve B, or are arranged adjacent to the curve B, indicating that when the semiconductor structure of the first embodiment of the present application is adopted, the process parameter variation is small, and the semiconductor structures in the second embodiment to the tenth embodiment can achieve the effect similar to that of the first embodiment after being tested and analyzed by the method.
Therefore, the semiconductor device in the application has a reasonable layout structure, the gate region width of the semiconductor device is 14nm, the size of the semiconductor device is greatly reduced compared with the existing semiconductor device with the gate region width of 20nm, and after the size of the semiconductor device is reduced, the integration level of an integrated circuit chip provided with the semiconductor device can be greatly improved, so that the functions of the integrated circuit chip can be increased, and the cost of the chip can be reduced by improving the integration level according to the existing moore's law.
The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (9)
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