CN113010470B - Edge node remote control system, method, equipment and storage medium - Google Patents
Edge node remote control system, method, equipment and storage medium Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The invention provides an edge node remote control system, a method, equipment and a storage medium, wherein the system comprises the following components: the system comprises a server and an SOC chip, wherein the SOC chip is connected with the server; the server initializes PCI-E resources, identifies and drives equipment connected with the SOC chip, configures parameter instructions, enables the SOC chip to configure data of the BAR space, resets protocol bits of the BAR space, analyzes the parameter instructions, feeds back instruction execution states to the server, confirms the instruction execution states, and adaptively updates the parameter instructions. The invention can realize a series of management operations such as inputting, starting, closing, program upgrading, IP configuration inquiry, version updating and the like of the control instructions of the chips, has high transmission speed and flexible operation, can manage a plurality of chips simultaneously, has high efficiency and flexibility, and reduces the peripheral dependence of the SOC chips.
Description
Technical Field
The present invention relates to remote control devices, and in particular, to an edge node remote control system, method, device, and storage medium.
Background
At present, in a control system formed by an SOC chip, simultaneous management of a plurality of chips is difficult, the efficiency is low, the flexibility is poor, and the peripheral equipment of the SOC chip is very dependent.
Accordingly, the present invention provides an edge node remote control system, method, apparatus, and storage medium.
Disclosure of Invention
Aiming at the problems in the prior art, the invention aims to provide an edge node remote control system, an edge node remote control method, edge node remote control equipment and an edge node remote control storage medium, which overcome the difficulties in the prior art, can realize the management operation of control instructions of chips, has high transmission speed and flexible operation, can manage a plurality of chips simultaneously, has high efficiency and flexibility, and reduces the peripheral dependence of an SOC chip.
An embodiment of the present invention provides an edge node remote control system, including: the system comprises a server and an SOC chip, wherein the SOC chip is connected with the server;
the server initializes PCI-E resources, identifies and drives equipment connected with the SOC chip, configures parameter instructions to enable the SOC chip to configure data of a BAR space, resets protocol bits of the BAR space, analyzes the parameter instructions, feeds back instruction execution states to the server, confirms the instruction execution states, and adaptively updates the parameter instructions.
Preferably, the SOC chip comprises the SOC chip driving layer and the SOC chip service layer, the SOC chip driving layer is connected with the server to realize data interaction between the SOC slave chip and the server, and the SOC chip driving layer performs output transmission and reading and writing of parameters of BAR space.
Preferably, the PCI-E interface of the server sends a control instruction and receives the input of the control instruction of the SOC chip.
Preferably, the server comprises a PC application layer and a PC driving layer, wherein the PC driving layer runs PCI-E driving development, encapsulates the PCI-E interface and communicates with the SOC chip.
Preferably, a control instruction is input to the SOC chip through the PCI-E interface, and the control instruction at least includes: starting, closing, upgrading a program, tracing an abnormal log, debugging a chip, inquiring IP configuration and updating a version.
Preferably, the PC application layer encapsulates a call interface at the PC end, and performs DMA memory access and BAR space parameter issuing.
Preferably, the PC application layer identifies a hardware device, accesses a device file handle under dev, and distinguishes and identifies the SOC chip.
Preferably, the PC application layer configures the Bar space, inputs instruction data, and sends the instruction data to the slave SOC equipment end through the PCI-E interface.
Preferably, the operation instruction of the SOC chip service layer at least includes: deleting files, designating file folder addresses, acquiring program version numbers, acquiring IP addresses of the SOC chips, restarting the SOC equipment, starting related program process control, and acquiring an SOC equipment log.
The embodiment of the invention also provides a remote control method of the edge node, which adopts the remote control system of the edge node and comprises the following steps:
s110, the server identifies and drives equipment connected with the SOC chip;
s120, the server configures parameter instructions to enable the SOC chip to configure data of a BAR space;
s120, resetting protocol bits of the BAR space and analyzing the parameter instruction; and
s130, feeding back the instruction execution state to the server, and confirming the instruction execution state by the server and adaptively updating the parameter instruction.
Preferably, the operation steps of the PC application layer are as follows:
s201, creating a parameter acquisition channel, and designating an SOC slave ID;
s202, reading a state address of a BAR space;
s203, writing an instruction for operating the slave chip;
s204, mapping a virtual memory;
s205, judging whether to upgrade the SOC slave slice program, if so, executing a step S206, and if not, executing a step S210;
s206, reading the corresponding file to the memory;
s207, deleting the slave slice program;
s208, segmenting the data length, and sequentially transmitting 6M data each time;
s209, when the transmission is finished, checking whether the version number is sure, if so, executing a step S210, and if not, executing a step S206;
s210, releasing the mapped virtual memory, and returning to the step S202.
Preferably, the operation steps of the SOC chip driving layer are as follows:
s301, accessing a bar space;
s302, checking whether the PC terminal is configured with parameters, if so, executing a step S303, and if not, returning to the step S301;
s303, allocating a DMA (direct memory access) carrying address;
s304, obtaining a destination address of DMA (direct memory access) transportation;
s305, inquiring the DMA, judging whether the DMA is operating, if so, returning to the step S301, and if not, executing the step S306;
s306, if the DMA is currently idle, executing the carrying task.
Preferably, the operation steps of the SOC chip driving layer are as follows:
s401, accessing bar space data;
s402, judging whether the instruction state is valid, if so, executing step S403, and if not, returning to step S401;
s403, judging whether upgrading is needed, if yes, executing a step S405, and if not, executing a step S404;
s404, judging whether the command is a console command, if so, executing a step S406, and if not, returning to the step S401;
s405, receiving DMA data, and executing step S408;
s406, analyzing the instruction type;
s407, executing corresponding instruction operation; and
s408, resetting an instruction status bit, wherein the instruction status bit is used for identifying whether instruction information in the instruction segment is valid.
The embodiment of the invention also provides edge node remote control equipment, which comprises:
a processor;
a memory having stored therein executable instructions of a processor;
wherein the processor is configured to perform the steps of the above-described edge node remote control method via execution of executable instructions.
The embodiment of the invention also provides a computer readable storage medium for storing a program, which when executed, implements the steps of the edge node remote control method.
The edge node remote control system, the method, the equipment and the storage medium can realize a series of management operations such as inputting, starting, closing, program upgrading, IP configuration inquiry, version updating and the like of control instructions of chips, have high transmission speed and flexible operation, can manage a plurality of chips simultaneously, have high efficiency and flexibility, reduce the peripheral dependence of the SOC chips, have low maintenance cost, can complete some column debugging and program upgrading work without on-site support, and reduce personnel business trip cost.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings.
Fig. 1 is a schematic diagram of an edge node remote control system of the present invention.
Fig. 2 is a flow chart of the edge node remote control method of the present invention.
Fig. 3 is a flow chart of the data flow of the PC application layer in the process of implementing the edge node remote control method of the present invention.
Fig. 4 is a flowchart of a data flow of the SOC chip driver layer in the process of implementing the edge node remote control method of the present invention.
Fig. 5 is a flowchart of a data flow of the SOC chip service layer in the process of implementing the edge node remote control method of the present invention.
Fig. 6 is a schematic structural diagram of the edge node remote control device of the present invention. and
Fig. 7 is a schematic structural view of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted.
Fig. 1 is a schematic diagram of an edge node remote control system of the present invention. As shown in fig. 1, the edge node remote control system of the present invention includes: a server 1 and an SOC chip 2, the SOC chip 2 is connected with the server 1. The server 1 initializes PCI-E resources, identifies and drives equipment connected with the SOC chip 2, configures parameter instructions, enables the SOC chip 2 to configure data of the BAR space, resets protocol bits of the BAR space, analyzes the parameter instructions, feeds back instruction execution states to the server 1, and the server 1 confirms the instruction execution states and adaptively updates the parameter instructions. The PCI-E in the invention refers to PCI-Express (peripheral component interconnect express) which is a high-speed serial computer expansion bus standard originally named as '3 GIO', proposed by Intel in 2001, and aims to replace the old PCI, PCI-X and AGP bus standards. PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, where connected devices allocate exclusive channel bandwidth, do not share bus bandwidth, and mainly support functions such as active power management, error reporting, end-to-end reliability transmission, hot plug, and quality of service (QOS). The BAR space is a shared memory segment of PCI-E. The SOC chip is called a system-on-chip, also known as a system-on-chip, meaning that it is a product that is an integrated circuit with dedicated targets, containing the complete system and having the entire contents of embedded software.
In a preferred embodiment, the SOC chip 2 comprises an SOC chip driving layer 21 and an SOC chip service layer 22, the SOC chip driving layer 21 is connected with the server 1 to realize data interaction between the SOC slave chip and the server 1, and the SOC chip driving layer 21 performs transmission of output and reading and writing of parameters of BAR space.
In a preferred embodiment, the PCI-E interface of the server 1 transmits control instructions and receives inputs of control instructions of the SOC chip 2.
In a preferred embodiment, the server 1 includes a PC application layer 11 and a PC driver layer 12, the PC driver layer 12 running PCI-E driver development, encapsulating a PCI-E interface, in communication with the SOC chip 2.
In a preferred embodiment, the PC application layer 11 encapsulates the call interface of the PC side, and performs DMA memory access and BAR space parameter issuing. DMA in the present invention refers to Direct Memory Access, direct memory access, allowing hardware devices of different speeds to communicate without relying on the massive interrupt load of the CPU. DMA transfers copy data from one address space to another. When the CPU initiates this transfer action, the transfer action itself is carried out and completed by the DMA controller. A typical example is to move a block of external memory to a faster memory area inside the chip. Operations such as this do not hold the processor work off, but may be rearranged Cheng Quchu to handle other work. DMA transfer is important for high performance embedded system algorithms and networks.
In a preferred embodiment, the PC application layer 11 identifies the hardware device, accesses the device file handle under dev, distinguishes and identifies the SOC chip 2.
In a preferred embodiment, the PC application layer 11 configures the Bar space, inputs instruction data, and sends the instruction data to the slave SOC device side through the PCI-E interface.
The invention mainly aims at a series of management operations such as inputting, starting, closing, program upgrading, IP configuration inquiry, version updating and the like of control instructions of chips by taking PCI-E interfaces as the basis of control systems of some embedded end chip programs, has high transmission speed and flexible operation, can manage a plurality of chips simultaneously, has high efficiency and flexibility, and reduces the peripheral dependence of the SOC chips.
The invention transmits the appointed control instruction through the PCI-E interface of the PC end to realize a series of management operations such as inputting, starting, closing, program upgrading, abnormal log tracking, chip debugging, IP configuration inquiry, version updating and the like of the control instruction of the chip, and the invention comprises the following steps: the PC application layer mainly realizes the functions of the application, mainly transmits instructions and transmits data. The PC driving layer mainly realizes PCI-E driving development, encapsulates related interfaces and realizes communication work with the SOC chip. The SOC chip control applet mainly realizes the instruction analysis issued by the PC end and completes the corresponding operation. The SOC chip driving layer mainly realizes data interaction between the SOC slave chip and the PC terminal, and mainly transmits output and reads and writes parameters of the bar space.
The driving layer mainly comprises 4 modules, hardware resource identification and loading, and bar space parameter configuration, and is mainly used for defining a communication protocol with an ep side. And acquiring the state of the DMA, acquiring the required picture according to the state, and resetting the bar space, wherein the bar space is mainly used for controlling the channel.
The PC application layer interface is mainly composed of 4 modules, namely an initial PCI-E resource, which is used for opening a device file handle. The iPC parameters are configured. And acquiring a picture pointer address. And closing the channel and releasing the resources. The driving layer mainly encapsulates a calling interface of the PC end to realize access of the DMA memory and issuing of bar space parameters. The hardware device is identified, primarily by accessing the device file handle under dev, to distinguish and identify the multi-card. The configuration of Bar space and the configuration of parameters are mainly operation protocol instructions formulated by instruction data input such as reboot, decode_version, update, ifconfig and the like, and the operation protocol instructions are sent to a designated slave SOC equipment end through a PCI-E interface. And the parameter of the parameter structure body is transmitted to the SOC equipment end through the address of the bar space.
The data module of the SOC from the chip side is mainly divided into a driving layer and a data monitoring application layer. The driving layer is mainly used for carrying out a resource identification handshake with the PC side. And (5) identifying and transmitting parameters of the configuration address segment of the bar space. The file data is interacted with the PC end through the DMA. And initializing main resources of an application layer, resolving the transmitted data from the bar space, and sending a corresponding instruction to the terminal.
The SOC chip driving layer mainly has the function of realizing the configuration of hardware registers. And accessing bar space data, and configuring transparent transmission of parameter data. DMA data handling. The most predominant of which is DMA data handling.
The SOC chip service layer is mainly in interactive control with instructions of a PC end, is mainly used for monitoring protocol addresses of a bar space, analyzing command types, wherein the types mainly comprise upgrading programs and operation instructions, the upgrading programs mainly comprise DMA data carrying, high-speed data transmission is realized, and the transmission speed is determined by PCI-E bandwidth; the operation instructions mainly comprise deletion of files, specification of folder addresses, acquisition of program version numbers, acquisition of IP addresses of the SOC chips, restarting of the SOC equipment, starting of related program process control, acquisition of related debugging information such as the SOC equipment logs and the like.
The edge node remote control system is flexible in control, simple and convenient to operate, low in maintenance cost, capable of completing some column debugging and program upgrading works without on-site support, and capable of reducing personnel business trip cost.
Fig. 2 is a flow chart of the edge node remote control method of the present invention. As shown in fig. 2, the present invention further provides a method for remotely controlling an edge node, which adopts the above-mentioned remote control system for an edge node, and includes the following steps:
s110, the server identifies and drives the equipment connected with the SOC chip.
S120, a server configures parameter instructions to enable the SOC chip to configure data of the BAR space.
S120, resetting protocol bits of the BAR space and analyzing parameter instructions. and
S130, feeding back the instruction execution state to the server, and confirming the instruction execution state by the server and adaptively updating the parameter instruction.
Fig. 3 is a flow chart of the data flow of the PC application layer in the process of implementing the edge node remote control method of the present invention. As shown in fig. 3, in a preferred embodiment, the data flow of the PC application layer in the present invention includes the following steps:
s201, creating a parameter acquisition channel, and designating an SOC slave ID;
s202, reading a state address of a BAR space;
s203, writing an instruction for operating the slave chip;
s204, mapping a virtual memory;
s205, judging whether to upgrade the SOC slave slice program, if so, executing a step S206, and if not, executing a step S210;
s206, reading the corresponding file to the memory;
s207, deleting the slave slice program;
s208, segmenting the data length, and sequentially transmitting 6M data each time;
s209, when the transmission is finished, checking whether the version number is sure, if so, executing a step S210, and if not, executing a step S206;
s210, releasing the mapped virtual memory, and returning to the step S202.
Fig. 4 is a flowchart of a data flow of the SOC chip driver layer in the process of implementing the edge node remote control method of the present invention. As shown in fig. 4, in a preferred embodiment, the data flow of the SOC chip driver layer in the present invention includes the following steps:
s301, accessing a bar space;
s302, checking whether the PC terminal is configured with parameters, if so, executing a step S303, and if not, returning to the step S301;
s303, allocating a DMA (direct memory access) carrying address;
s304, obtaining a destination address of DMA (direct memory access) transportation;
s305, inquiring the DMA, judging whether the DMA is operating, if so, returning to the step S301, and if not, executing the step S306;
s306, if the DMA is currently idle, executing the carrying task.
Fig. 5 is a flowchart of a data flow of the SOC chip service layer in the process of implementing the edge node remote control method of the present invention. As shown in fig. 5, in a preferred embodiment, the data flow of the SOC chip service layer in the present invention includes the following steps:
s401, accessing bar space data;
s402, judging whether the instruction state is valid, if so, executing step S403, and if not, returning to step S401;
s403, judging whether upgrading is needed, if yes, executing a step S405, and if not, executing a step S404;
s404, judging whether the command is a console command, if so, executing a step S406, and if not, returning to the step S401;
s405, receiving DMA data, and executing step S408;
s406, analyzing the instruction type;
s407, executing corresponding instruction operation; and
s408, resetting an instruction status bit, wherein the instruction status bit is used for identifying whether instruction information in an instruction segment is valid.
The edge node remote control method can realize a series of management operations such as inputting, starting, closing, program upgrading, IP configuration inquiry, version updating and the like of the control instructions of the chips, has high transmission speed and flexible operation, can manage a plurality of chips simultaneously, has high efficiency and flexibility, reduces the peripheral dependence of the SOC chips, has low maintenance cost, can complete some column debugging and program upgrading works without on-site support, and reduces personnel business trip cost.
The embodiment of the invention also provides edge node remote control equipment which comprises a processor. A memory having stored therein executable instructions of a processor. Wherein the processor is configured to perform the steps of the method for edge node remote control via execution of executable instructions.
As described above, the edge node remote control device of the invention can realize a series of management operations such as inputting, starting, closing, program upgrading, IP configuration inquiry, version updating and the like of control instructions of chips, has high transmission speed and flexible operation, can manage a plurality of chips simultaneously, has high efficiency and flexibility, reduces the peripheral dependence of the SOC chips, has low maintenance cost, can complete some column debugging and program upgrading work without on-site support, and reduces personnel business trip cost.
Those skilled in the art will appreciate that the various aspects of the invention may be implemented as a system, method, or program product. Accordingly, aspects of the invention may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" platform.
Fig. 6 is a schematic structural diagram of the edge node remote control device of the present invention. An electronic device 600 according to this embodiment of the invention is described below with reference to fig. 6. The electronic device 600 shown in fig. 6 is merely an example, and should not be construed as limiting the functionality and scope of use of embodiments of the present invention.
As shown in fig. 6, the electronic device 600 is in the form of a general purpose computing device. Components of electronic device 600 may include, but are not limited to: at least one processing unit 610, at least one memory unit 620, a bus 630 connecting the different platform components (including memory unit 620 and processing unit 610), a display unit 640, etc.
Wherein the storage unit stores program code executable by the processing unit 610 such that the processing unit 610 performs the steps according to various exemplary embodiments of the present invention described in the above-described electronic prescription flow processing method section of the present specification. For example, the processing unit 610 may perform the steps as shown in fig. 1.
The storage unit 620 may include readable media in the form of volatile storage units, such as Random Access Memory (RAM) 6201 and/or cache memory unit 6202, and may further include Read Only Memory (ROM) 6203.
The storage unit 620 may also include a program/utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
The electronic device 600 may also communicate with one or more external devices 700 (e.g., keyboard, pointing device, bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 600, and/or any device (e.g., router, modem, etc.) that enables the electronic device 600 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 650. Also, electronic device 600 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through network adapter 660. The network adapter 660 may communicate with other modules of the electronic device 600 over the bus 630. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 600, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage platforms, and the like.
The embodiment of the invention also provides a computer readable storage medium for storing a program, and the steps of the edge node remote control method are realized when the program is executed. In some possible embodiments, the aspects of the present invention may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the invention as described in the electronic prescription stream processing method section of this specification, when the program product is run on the terminal device.
As described above, when the program of the computer readable storage medium of this embodiment is executed, a series of management operations such as inputting, starting, closing, program upgrading, IP configuration query, version updating, etc. of control instructions of the chip can be implemented, and the transmission speed is fast, the operation is flexible, and the program can be simultaneously managed for a plurality of chips, and the program is efficient and flexible, reduces the peripheral dependency of the SOC chip, and has low maintenance cost, and can complete some column debugging and program upgrading operations without on-site support, thereby reducing personnel business trip cost.
Fig. 7 is a schematic structural view of a computer-readable storage medium of the present invention. Referring to fig. 7, a program product 800 for implementing the above-described method according to an embodiment of the present invention is described, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable storage medium may also be any readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
In summary, the edge node remote control system, the method, the equipment and the storage medium can realize a series of management operations such as inputting, starting, closing, program upgrading, IP configuration inquiry, version updating and the like of control instructions of chips, have high transmission speed and flexible operation, can manage a plurality of chips simultaneously, have high efficiency and flexibility, reduce the peripheral dependence of the SOC chips, have low maintenance cost, can complete some column debugging and program upgrading work without on-site support, and reduce personnel business trip cost.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (11)
1. An edge node remote control system, comprising: the system comprises a server and an SOC chip, wherein the SOC chip is connected with the server;
the server initializes PCI-E resources, identifies and drives equipment connected with the SOC chip, configures parameter instructions, enables the SOC chip to configure data of a BAR space, resets protocol bits of the BAR space, analyzes the parameter instructions, feeds back instruction execution states to the server, confirms instruction execution states, adaptively updates the parameter instructions, sends control instructions to a PCI-E interface of the server, receives input of the control instructions of the SOC chip, comprises a PC application layer and a PC driving layer, runs PCI-E driving development, encapsulates the PCI-E interface, communicates with the SOC chip, and inputs the control instructions to the SOC chip through the PCI-E interface, wherein the control instructions at least comprise: starting, closing, program upgrading, abnormal log tracking, chip debugging, IP configuration query and version updating, wherein the PC application layer encapsulates a calling interface of a PC end and performs DMA memory access and BAR space parameter issuing.
2. The edge node remote control system according to claim 1, wherein the SOC chip comprises the SOC chip driving layer and an SOC chip service layer, the SOC chip driving layer is connected with the server to realize data interaction between the SOC slave chip and the server, and the SOC chip driving layer performs output transmission and reading and writing of parameters of BAR space.
3. The edge node remote control system of claim 1, wherein the PC application layer identifies hardware devices, accesses device file handles under dev, distinguishes and identifies the SOC chip.
4. The edge node remote control system of claim 1, wherein the PC application layer configures Bar space, inputs instruction data, and sends the instruction data to the slave SOC device side through the PCI-E interface.
5. The edge node remote control system of claim 1, wherein the operation instructions of the SOC chip traffic layer at least comprise: deleting files, designating file folder addresses, acquiring program version numbers, acquiring IP addresses of the SOC chips, restarting the SOC equipment, starting related program process control, and acquiring an SOC equipment log.
6. An edge node remote control method, characterized in that the edge node remote control system according to claim 1 is used, comprising the steps of:
s110, the server identifies and drives equipment connected with the SOC chip;
s120, the server configures parameter instructions to enable the SOC chip to configure data of a BAR space;
s120, resetting protocol bits of the BAR space and analyzing the parameter instruction; and
s130, feeding back the instruction execution state to the server, and confirming the instruction execution state by the server and adaptively updating the parameter instruction.
7. The edge node remote control method according to claim 6, wherein the PC application layer operates as follows:
s201, creating a parameter acquisition channel, and designating an SOC slave ID;
s202, reading a state address of a BAR space;
s203, writing an instruction for operating the slave chip;
s204, mapping a virtual memory;
s205, judging whether to upgrade the SOC slave slice program, if so, executing a step S206, and if not, executing a step S210;
s206, reading the corresponding file to the memory;
s207, deleting the slave slice program;
s208, segmenting the data length, and sequentially transmitting 6M data each time;
s209, when the transmission is finished, checking whether the version number is sure, if so, executing a step S210, and if not, executing a step S206;
s210, releasing the mapped virtual memory, and returning to the step S202.
8. The edge node remote control method according to claim 6, wherein the SOC chip driver layer operates as follows:
s301, accessing a bar space;
s302, checking whether the PC terminal is configured with parameters, if so, executing a step S303, and if not, returning to the step S301;
s303, allocating a DMA (direct memory access) carrying address;
s304, obtaining a destination address of DMA (direct memory access) transportation;
s305, inquiring the DMA, judging whether the DMA is operating, if so, returning to the step S301, and if not, executing the step S306;
s306, if the DMA is currently idle, executing the carrying task.
9. The edge node remote control method according to claim 6, wherein the SOC chip driver layer operates as follows:
s401, accessing bar space data;
s402, judging whether the instruction state is valid, if so, executing step S403, and if not, returning to step S401;
s403, judging whether upgrading is needed, if yes, executing a step S405, and if not, executing a step S404;
s404, judging whether the command is a console command, if so, executing a step S406, and if not, returning to the step S401;
s405, receiving DMA data, and executing step S408;
s406, analyzing the instruction type;
s407, executing corresponding instruction operation; and
s408, resetting an instruction status bit, wherein the instruction status bit is used for identifying whether instruction information in the instruction segment is valid.
10. An edge node remote control device, comprising:
a processor;
a memory having stored therein executable instructions of a processor;
wherein the processor is configured to perform the steps of the edge node remote control method of claim 6 via execution of executable instructions.
11. A computer-readable storage medium storing a program, characterized in that the program is executed to implement the steps of the edge node remote control method of claim 6.
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| CN115297093B (en) * | 2022-08-02 | 2024-06-25 | 北京至为恒通企业管理有限公司 | Edge device data access method, related device and computer program product |
| CN118865648A (en) * | 2023-04-28 | 2024-10-29 | 荣耀终端有限公司 | Remote control method, PC, chip system and storage medium |
| CN117093161B (en) * | 2023-10-19 | 2024-01-26 | 之江实验室 | Memory management system, method, medium and equipment based on optical transceiver chip |
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