CN112968822A

CN112968822A - One-master multi-slave real-time communication system and method based on Ethernet PHY

Info

Publication number: CN112968822A
Application number: CN202110278016.9A
Authority: CN
Inventors: 万燕英; 曹众佳; 刘文波
Original assignee: Guangzhou Railway Polytechnic
Current assignee: Guangzhou Railway Polytechnic
Priority date: 2021-03-15
Filing date: 2021-03-15
Publication date: 2021-06-15

Abstract

The present invention relates to a motion control real-time communication system and method, and more particularly, to a one-master multi-slave real-time communication system and method based on an ethernet PHY. The system comprises a main node and a slave node, wherein the main node comprises an industrial control computer and an NIC network card unit, and the slave node comprises an FPGA main control unit, a PHY unit, a network transformer unit and an RJ45 network port. The main node connects the NIC to the input port of the slave node through the network cable, the output port of the slave node is connected to the input port of the next slave node, and a main multi-slave communication network is formed in sequence. By means of a physical layer communication link provided by a gigabit Ethernet PHY and by writing FPGA control logic, data transmission with strong real-time performance, large throughput and high reliability can be realized; the method has the advantages of simple implementation mode, multi-node communication, high reliability, high real-time performance and capability of realizing data transmission with strong real-time performance, large throughput and high reliability.

Description

One-master multi-slave real-time communication system and method based on Ethernet PHY

Technical Field

The present invention relates to a motion control real-time communication system and method, and more particularly, to a one-master multi-slave real-time communication system and method based on an ethernet PHY.

Background

In the field of industrial motion control, data interaction between devices is often required to be performed in real time at high speed. When the distance between the devices is long, RS485, CAN, Ethernet and other transmission media CAN be adopted, and the reliability of data interaction is ensured by combining with upper-layer protocols. RS485 and CAN buses are generally suitable for occasions with small data volume and low requirements on refresh cycles; and the common Ethernet communication has no real-time performance and can not be directly used in the occasions with strict requirements on the real-time performance of industrial communication, such as robots, motion control systems and the like.

Some communication protocols, such as EtherCAT, Powerlink, PROFINET, etc., have been derived based on ethernet transmission media. On one hand, such protocols are generally complex and have certain requirements on hardware, which increases the difficulty of application. On the other hand, the Ethernet technology has specificity and closure, and a certain royalty needs to be paid to the Ethernet technology during application. However, in the field of partial motion control, a complete routing mechanism and flow control are not needed, but a high real-time data interaction mode is needed.

Disclosure of Invention

The present invention provides a primary-multi-slave real-time communication system and method based on ethernet PHY, which has the advantages of high reliability, high real-time performance, and multi-node communication.

In order to solve the technical problems, the invention adopts the technical scheme that: a one-master multi-slave real-time communication system based on an Ethernet PHY comprises a master node and slave nodes; the main node comprises an industrial control computer and an NIC network card unit; the slave node comprises an FPGA main control chip, a first physical layer PHY chip, a second physical layer PHY chip, a first network transformer, a second network transformer, a first RJ45 network port and a second RJ45 network port; the industrial control computer is connected with the NIC network card through a PCI or PCIe bus; the FPGA main control chip is electrically connected with one end of a first physical layer PHY chip, the other end of the first physical layer PHY chip is electrically connected with one end of a first network transformer, and the other end of the first network transformer is electrically connected with a first RJ45 network port; the FPGA main control chip is also electrically connected with one end of a second physical layer PHY chip, the other end of the second physical layer PHY chip is electrically connected with one end of a second network transformer, and the other end of the second network transformer is electrically connected with a second RJ45 network port; the master node and the slave node are connected through a network cable.

In one embodiment, the host node further includes a NIC driving unit and a first data exchange format defining unit; the slave node also comprises a slave node control unit and a second data exchange format definition unit; the NIC driving unit and the first data exchange format defining unit are respectively in communication connection with the industrial personal computer; and the slave node control unit and the second data exchange format definition unit are respectively in communication connection with the FPGA main control chip.

In one embodiment, the FPGA master control chip is connected to the first physical layer PHY chip and the second physical layer PHY chip through RMII interfaces, respectively.

In one embodiment, the first RJ45 port and the second RJ45 port are full duplex, and the communication rate is 100Mbps or 1000 Mbps.

In one embodiment, the network card unit of the master node NIC is communicatively connected to the first RJ45 network port of the slave node through a network cable.

In one embodiment, the slave nodes are provided with a plurality of groups, and the plurality of groups of slave nodes are connected in series through a network cable.

In one embodiment, the second RJ45 port of a slave node is communicatively connected to the first RJ45 port of another slave node via a network cable.

In one embodiment, the number of the slave nodes is less than or equal to 65535, and the distance between two adjacent slave nodes is less than or equal to 100 meters.

In one embodiment, the first RJ45 port is an input port; the second RJ45 port is an output port.

The invention also provides a master-slave real-time communication method based on the Ethernet PHY, which uses the master-slave real-time communication system based on the Ethernet PHY and specifically comprises the following steps: when a data updating period comes, the NIC driving unit packages data to be sent into a package according to the definition of an agreed data exchange format, the NIC driving unit fills the data sending buffer area, and the data is sent to an input network port of a first slave node through a network transformer; and the slave node FPGA main control chip receives data flow from the input network port, defines, analyzes and secondarily packages the data flow according to an agreed data exchange format, then sends the data flow to the input network port of the next slave node from the slave node output network port, and so on until the data exchange of all the nodes in the network is completed.

Compared with the prior art, the beneficial effects are: according to the one-master multi-slave real-time communication system and method based on the Ethernet PHY, provided by the invention, by means of a physical layer communication link provided by the gigabit Ethernet PHY, the FPGA control logic is compiled, so that the data transmission with strong real-time performance, large throughput and high reliability can be realized; the invention has simple realization mode, multi-node communication, high reliability and real-time performance, and can realize data transmission with strong real-time performance, large throughput and high reliability.

Drawings

FIG. 1 is a schematic diagram of the system of the present invention.

Fig. 2 is a block diagram of a slave node communication unit of the present invention.

Fig. 3 is a flow chart of real-time communication data interaction according to the present invention.

Detailed Description

The drawings are for illustration purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.

Example 1

The embodiment provides a master-slave real-time communication system based on an Ethernet PHY, which comprises a master node and slave nodes; the main node comprises an industrial control computer and an NIC network card unit; the slave node comprises an FPGA main control chip, a first physical layer PHY chip, a second physical layer PHY chip, a first network transformer, a second network transformer, a first RJ45 network port and a second RJ45 network port; the industrial control computer is connected with the NIC network card through a PCI or PCIe bus; the FPGA main control chip is electrically connected with one end of the first physical layer PHY chip, the other end of the first physical layer PHY chip is electrically connected with one end of the first network transformer, and the other end of the first network transformer is electrically connected with the first RJ45 port; the FPGA main control chip is also electrically connected with one end of a second physical layer PHY chip, the other end of the second physical layer PHY chip is electrically connected with one end of a second network transformer, and the other end of the second network transformer is electrically connected with a second RJ45 network port; the master node and the slave node are connected through a network cable.

In one embodiment, the master node further includes a NIC driving unit and a first data exchange format defining unit; the slave node further comprises a slave node control unit and a second data exchange format definition unit; the NIC driving unit and the first data exchange format defining unit are respectively in communication connection with the industrial personal computer; and the slave node control unit and the second data exchange format definition unit are respectively in communication connection with the FPGA main control chip.

In one embodiment, the slave nodes are provided with a plurality of groups, and the plurality of groups of slave nodes are connected in series through the network cable.

Example 2

The embodiment provides a master-slave real-time communication method based on an ethernet PHY, and the method for implementing the master-slave real-time communication system based on the ethernet PHY in embodiment 1 specifically includes the following steps: when a data updating period comes, the NIC driving unit packages data to be sent into a package according to the definition of an agreed data exchange format, the NIC driving unit fills the data sending buffer area, and the data is sent to an input network port of a first slave node through a network transformer; and the slave node FPGA main control chip receives data flow from the input network port, defines, analyzes and secondarily packages the data flow according to an agreed data exchange format, then sends the data flow to the input network port of the next slave node from the slave node output network port, and so on until the data exchange of all the nodes in the network is completed.

The NIC driving unit works in a kernel mode and performs data interaction with the real-time task layer in a memory sharing mode; the NIC driving unit removes an interface interacted with an upper layer protocol stack and increases an interaction interface with a real-time task layer; the NIC driving unit turns off the functions of power management, dormancy and the like so as to enhance the real-time performance; the NIC driving unit comprises a hardware initialization function, a cache initialization function, a data sending processing function, a data receiving processing function, a state updating function and a data packaging and analyzing function; the data transmission flow is that a data encapsulation and analysis function encapsulates data transmitted by a real-time task layer in a shared memory mode according to a data exchange format, then a descriptor is assigned and transmitted according to skb through a data transmission processing function, and then a hardware transmission register is enabled to directly transmit the data out; the data receiving process comprises the steps that an interrupt mechanism is set by an initialization function to receive a data packet, when the interrupt is received, a data receiving processing function copies data from a receiving descriptor according to skb, and then a data analysis function is called to transmit effective data to a real-time task layer in a shared memory mode; the state update function in the NIC driving unit may report the number of the transceiving packets, the network connection state, the number of the slave nodes, the transmission and reception rates, and the like to the user layer.

The slave node FPGA main control chip is configured with control programs including PYH initialization functions, data transceiving processing functions, data packaging and analyzing functions; the PHY initialization function comprises auto-negotiation mode configuration, rate configuration, RMII reset and RMII enabling; the slave nodes can automatically arrange address codes according to the physical connection sequence in the network; the data receiving and transmitting processing function receives the data stream from the first network port and carries out CRC (cyclic redundancy check) check; the slave node reads data from the corresponding data segment according to the address code of the slave node, inserts new data to be sent, accumulates the counter in the data packet by 1, performs integral CRC (cyclic redundancy check) on the new data packet, and fills the new check data into the data packet; the slave nodes send out the newly processed data packets from the second network port according to the bit stream until the data packets processed by the last node in the network are returned to the master node one by one through each slave node; as shown in fig. 3, the whole communication process is operated in a full-duplex mode, and each slave node implements update processing on a data packet in a pure hardware manner.

The data exchange format protocol unit comprises an Ethernet lead code, a frame start delimiter, a slave node address code, data length, user data, a data packet counter, a synchronous clock, data verification and the like; the preamble is 7 bytes 0x55, a series of 1 and 0 interval data streams, which represents signal synchronization; the start of frame delimiter is 1 byte 0xD5, indicating the start of valid data; the slave node address code is 2 bytes and is automatically filled according to the position of the slave node in the network; the data length is 2 bytes; the data packet counter is 2 bytes, represents the number of times of the present data packet is processed, is used for the network communication to diagnose; the synchronous clock is 4 bytes and represents the time sequence synchronization of each slave node; the data is checked for 4 bytes and the CRC32 checks all data from the start delimiter of the frame to the last byte of the sync clock and fills in the end of the packet.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A master-multi-slave real-time communication system based on Ethernet PHY, characterized in that it includes a master node and a slave node; the master node includes an industrial control computer, a NIC network card unit; the slave node includes an FPGA master control chip, the first physical layer PHY chip, the second physical layer PHY chip, the first network transformer, the second network transformer, the first RJ45 network port and the second RJ45 network port; the industrial control computer and the NIC network card pass through the PCI or PCIe bus connection; the FPGA main control chip is electrically connected to one end of the first physical layer PHY chip, the other end of the first physical layer PHY chip is electrically connected to one end of the first network transformer, the The other end of the first network transformer is electrically connected to the first RJ45 network port; the FPGA main control chip is also electrically connected to one end of the second physical layer PHY chip, and the second physical layer PHY chip The other end is electrically connected to one end of the second network transformer, and the other end of the second network transformer is electrically connected to the second RJ45 network port; the master node and the slave node are connected through a network cable.

2. The Ethernet PHY-based one-master multi-slave real-time communication system according to claim 1, wherein the master node further comprises a NIC drive unit and a first data exchange format definition unit; the slave node It also includes a slave node control unit and a second data exchange format definition unit; the NIC drive unit and the first data exchange format definition unit are respectively connected to the industrial computer in communication; the slave node control unit and the second data exchange format The definition units are respectively connected with the FPGA main control chip in communication.

3. The Ethernet PHY-based one-master multi-slave real-time communication system according to claim 1, wherein the FPGA main control chip communicates with the first physical layer PHY chip and the second physical layer PHY through the RMII interface respectively chip connection.

4. The one-master-multiple-slave real-time communication system based on Ethernet PHY according to claim 1, wherein the first RJ45 network port and the second RJ45 network port are both full-duplex, and the communication rate is 100Mbps or 1000Mbps.

5 . The Ethernet PHY-based one-master multi-slave real-time communication system according to claim 1 , wherein the master node NIC network card unit is connected to the first RJ45 network port of the slave node through a network cable. 6 .

6. The Ethernet PHY-based one-master multi-slave real-time communication system according to any one of claims 1 to 4, wherein the slave nodes are provided with multiple groups, and the multiple groups of slave nodes are connected in series through network cables connect.

7 . The Ethernet PHY-based one-master multi-slave real-time communication system according to claim 6 , wherein the second RJ45 network port of the slave node is communicatively connected to the first RJ45 network port of another slave node through a network cable. 8 .

8. The Ethernet PHY-based one-master-multiple-slave real-time communication system according to claim 7, wherein the number of the slave nodes is less than or equal to 65535, and the distance between two adjacent slave nodes is less than or equal to 100 Meter.

9. The Ethernet PHY-based one-master multi-slave real-time communication system according to claim 7, wherein the first RJ45 network port is an input port; the second RJ45 network port is an output port.

10. An Ethernet PHY-based one-master multi-slave real-time communication method, characterized in that, using the Ethernet PHY-based one-master multi-slave real-time communication system according to any one of claims 2 to 9, specifically comprising the following steps : When the data update cycle arrives, the NIC drive unit encapsulates the data to be sent into packets according to the agreed data exchange format definition, which is filled by the NIC drive unit into the data sending buffer, and sent to the input of the first slave node through the network transformer Network port; the slave node FPGA main control chip receives the data stream from the input network port, parses it according to the agreed data exchange format definition and repackages it into a packet, and then sends it from the output network port of the slave node to the input network port of the next slave node , and so on until the data exchange of all nodes in the network is completed.