CN112953562B - Signal processing device and signal processing method - Google Patents

Abstract

A signal processing device comprises a memory device and a processor. The memory device stores at least one phase shift matrix. The processor reads the phase shift matrix from the memory device and generates an output sequence according to an input sequence and the phase shift matrix. The phase shift matrix is generated according to a basic matrix and a preset phase shift amount (k), the basic matrix is used for generating a code sequence, and the output sequence is the result of the input sequence after being subjected to phase shift for k cycles.

Description

Signal processing device and signal processing method

Technical field

The present invention relates to a signal processing device, and in particular to a signal processing device capable of performing fast sequence rearrangement.

Background technique

During the data transmission process of the communication system, the timing and frequency of the transmitting end and the receiving end must be synchronized before subsequent data transmission can be performed. Pseudorandom Noise (PN for short) or PseudoNoise (PN for short) code sequence is a sequence often used when performing timing and frequency synchronization. The transmitting end and the receiving end can use the same initial value (also called seed) to generate a PN code sequence according to the same mechanism. The transmitting end embeds this PN code sequence in the signal and transmits it to the receiving end. The receiving end performs a correlation operation on the PN code sequence and one or more phase-shifted results of the sequence and the received signal to estimate the timing offset and frequency offset caused by the transmission channel effect. . After compensating the timing offset and frequency offset, the receiving end can successfully decode the correct data.

Since the PN code sequence is a cyclic sequence, it is generated sequentially by inputting the seed into a Linear Feedback Shift Register (LFSR) circuit, in which the output bit is usually based on the previous stage. Or the values of multi-stage shift registers are generated. Therefore, in the prior art, the phase-shifted PN code sequence actually needs to be derived by moving the values of the shift register to the next stage in sequence. For example, if it is necessary to deduce the PN code sequence relative to the time index (n+k) based on the current time index (n) (ie, phase shifted by k clock cycles), then the time index (n) must be The PN code sequence can be obtained by pushing k cycles forward, in which the LFSR circuit can derive one bit of the PN code sequence at each frequency cycle.

However, when the above k is a large value, the receiver must wait for a large number of frequency cycles to obtain the required PN code sequence, thus causing a problem of poor efficiency.

Contents of the invention

The object of the present invention is to provide a signal processing method and related signal processing device to solve the above problem of poor efficiency. According to the signal processing method and signal processing device proposed by the present invention, the PN code sequence can be quickly rearranged (permutation) according to the required phase shift amount, without having to wait for several frequency cycles to obtain the required phase shift as in the prior art. PN code sequence, which effectively solves the problem of poor efficiency in the existing technology.

An embodiment of the present invention provides a signal processing method for a signal processing device. The signal processing device includes a processor. The signal processing method includes the following steps performed by the processor: generating a signal based on at least one set of basic coefficients. a basic matrix, wherein the basic coefficient is used to generate at least one bit of a code sequence; generate a phase shift matrix according to a preset phase shift amount and the basic matrix; and generate an output sequence according to an input sequence and the phase shift matrix, wherein The output sequence is the result of the input sequence being phase-shifted by k cycles, where k is the preset phase shift amount.

Another embodiment of the present invention provides a signal processing method for a signal processing device. The signal processing device includes a processor and a memory device. The signal processing method includes the following steps executed by the processor: in the memory device Store multiple phase shift matrices, wherein the phase shift matrix is generated based on a basic matrix and different phase shift amounts. The basic matrix is used to generate a code sequence; select the corresponding phase shift matrix according to a preset phase shift amount. a phase shift matrix; and generate an output sequence based on an input sequence and the corresponding phase shift matrix, where the output sequence is the result of the input sequence being phase shifted for k cycles, where k is the preset phase shift amount.

Another embodiment of the present invention provides a signal processing device, including a memory device and a processor. The memory device stores at least one phase shift matrix. The processor is coupled to the memory device, reads the phase shift matrix from the memory device, and generates an output sequence according to an input sequence and the phase shift matrix. The phase shift matrix is generated based on a basic matrix and a preset phase shift amount. The basic matrix is used to generate a code sequence, and the output sequence is the result of the input sequence being phase shifted by k cycles, where k is the preset phase. Shift amount.

Description of drawings

FIG. 1 is an example block diagram illustrating a signal processing apparatus according to an embodiment of the present invention.

Figure 2 is an example circuit diagram illustrating a linear feedback shift register circuit according to one embodiment of the present invention.

Figure 3 is a schematic diagram illustrating an example of a fundamental matrix according to an embodiment of the present invention.

Figure 4 is a schematic diagram illustrating an example of a phase shift matrix according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating an example of a fundamental matrix according to another embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating an example of a phase shift matrix according to another embodiment of the present invention.

FIG. 7 is an example flowchart illustrating the signal processing method according to the first embodiment of the present invention.

FIG. 8 is an example flowchart illustrating a signal processing method according to the second embodiment of the present invention.

FIG. 9 is an example flowchart illustrating a signal processing method according to a third embodiment of the present invention.

Detailed ways

FIG. 1 is an example block diagram illustrating a signal processing apparatus according to an embodiment of the present invention. The signal processing device 100 may at least include a processor 110 and a memory device 120 . According to an embodiment of the present invention, the processor 110 can directly generate an output sequence according to an input sequence and a preset phase shift amount (k), where the output sequence is the result of the input sequence being phase-shifted by k frequency cycles, where k is a positive integer.

Generally speaking, a cyclic sequence (Cyclic sequence), such as a PN code sequence, is generated through a linear feedback shift register (LFSR) circuit. According to the design of the feedback mechanism and connection relationship of each level of buffer in the LFSR circuit, the The generated cyclic sequence will have a corresponding period N. That is, after the input sequence has been pushed through N frequency cycles, the output sequence will begin to produce a repeating bit pattern.

In embodiments of the present invention, the output sequence is no longer generated by feeding the input sequence into the LFSR circuit and continuously pushing several frequency cycles, but can be quickly derived directly from matrix operations. More specifically, in embodiments of the present invention, the processor 110 may derive a sequence generation matrix (the fundamental matrix) based on a mechanism (eg, at least one polynomial) used to generate a code sequence, where the The polynomial can be derived based on the circuit design of the LFSR circuit used to generate the code sequence (ie, the design of the feedback mechanism of the circuit and the connection relationship between various stages). The processor 110 may then directly derive the desired output sequence based on multiplying the input sequence by a power of the underlying matrix. Assuming that the required output sequence is the result of the input sequence being phase-shifted by k frequency cycles, the processor 110 can directly obtain the required output sequence by multiplying the input sequence by the kth power of the basic matrix. .

Figure 2 is an example circuit diagram illustrating a linear feedback shift register circuit according to one embodiment of the present invention. Linear feedback shift register (LFSR) circuit 200 includes 10-bit shift registers SR(0)˜SR(9). The shift registers SR(0)˜SR(9) can each be assigned an initial value first, where the initial value of the shift register is called a seed. Then, the LFSR circuit 200 sequentially generates output bits in response to clock ticks of the frequency signal CLK to become the output sequence Seq_Out. Assuming that the current time index is n, the following relationship formula can be derived based on the circuit design of the LFSR circuit 200 circuit:

x0(n+1)＝x2(n)+x9(n) Formula (1)

x1(n+1)＝x0(n) Formula (2)

x2(n+1)＝x1(n) Formula (3)

x3(n+1)＝x2(n) Formula (4)

x4(n+1)＝x3(n) Formula (5)

x5(n+1)＝x4(n) Formula (6)

x6(n+1)＝x5(n) Formula (7)

x7(n+1)＝x6(n) Formula (8)

x8(n+1)＝x7(n) Formula (9)

x9(n+1)＝x8(n) Formula (10)

Among them, x0(n)~x9(n) are the values of the shift registers SR(0)~SR(9) at time point n, respectively, and x0(n+1)~x9(n+1) are the values of the shift register SR respectively. The values of (0)~SR(9) at time point n+1.

Formulas (1) to (10) show the relationship between the values temporarily stored in the shift register when the bit data moves forward, where the forward direction refers to the direction in which the bit data is pushed, also It can be regarded as the direction of bit flow as the time index value increases (that is, the bit data will move to the next stage shift register as the time index value increases).

FIG. 3 is a schematic diagram illustrating an example of a fundamental matrix according to an embodiment of the present invention. The fundamental matrix 310 is generated based on polynomials derived based on the circuit design of the LFSR circuit 200 circuit, for example, the above-mentioned relational formulas (1) to (10). Therefore, in this embodiment, the basic matrix 310 is a forward sequence generating matrix. More specifically, the processor 110 can extract the coefficients of each item in the relational formulas (1) to (10) into a plurality of row vectors (row vectors), and then generate the fundamental matrix 310 based on the row vectors. As shown in FIG. 3 , the basic coefficient 300 is a row vector that constitutes the basic matrix 310 , and the basic coefficient 300 is generated according to the relational formula (1) to generate at least one bit of the code sequence. According to an embodiment of the present invention, the basic coefficient 300 is the first row vector (Top row vector) of the basic matrix 310, and other sets of coefficients generated according to the relational formulas (2) to (10) form the basic matrix 310 in sequence. The second to last row vector (Bottom row vector).

Figure 3 also shows a method of generating an output sequence based on the input sequence and the fundamental matrix. According to one embodiment of the present invention, the processor 110 may directly multiply the input sequence 320 by the basis matrix 310 to generate the output sequence 330.

According to an embodiment of the present invention, assuming that the required output sequence is the result of the input sequence being phase-shifted by k frequency cycles, the processor 110 multiplies the input sequence by the kth power of the basic matrix, then The desired output sequence can be obtained directly.

FIG. 4 is a schematic diagram illustrating an example of a phase shift matrix according to an embodiment of the present invention. In this embodiment, the processor 110 needs to generate the sequences x0(n+2)˜x9(n+2) based on the sequences x0(n)˜x9(n) that have been forward phase shifted by 2 frequency cycles. Therefore, The processor 110 can directly obtain the required output sequence 430 by multiplying the input sequence 420 by the phase shift matrix 410, where the phase shift matrix 410 is the second power of the basic matrix 310 (i.e., the phase shift matrix 410 The result of squaring the fundamental matrix 310).

In other words, in the embodiment of the present invention, if you want to generate a sequence with a phase shift of k frequency cycles, you only need to derive the kth power of the basic matrix as the phase shift matrix, and you can quickly convert the PN The code sequence is rearranged according to the required phase shift amount k, and there is no need to wait for the LFSR circuit to drive k frequency cycles according to the starting seed before obtaining the required PN code sequence as in the prior art.

The fundamental matrix 310 shown in FIG. 3 and the phase shift matrix 410 shown in FIG. 4 are both forward sequence generation matrices. In embodiments of the present invention, based on the same LFSR circuit, the relationship between the values of the shift registers at each stage when the bit data is moved backward can also be derived. Taking the circuit diagram shown in Figure 2 as an example, assuming that the current time index is n, the following relationship can also be derived based on the circuit design of the LFSR circuit 200 circuit:

x0(n-1)＝x1(n) Formula (11)

x1(n-1)＝x2(n) Formula (12)

x2(n-1)＝x3(n) Formula (13)

x3(n-1)＝x4(n) Formula (14)

x4(n-1)＝x5(n) Formula (15)

x5(n-1)＝x6(n) Formula (16)

x6(n-1)＝x7(n) Formula (17)

x7(n-1)＝x8(n) Formula (18)

x8(n-1)＝x9(n) Formula (19)

x9(n-1)＝x0(n)+x3(n) Formula (20)

Among them, x0(n-1)～x9(n-1) are the values of shift registers SR(0)～SR(9) at time point n-1 respectively.

Formulas (11) to (20) show the relationship between the values temporarily stored in the shift register when the bit data is moved in the reverse direction, where the reverse direction refers to the direction opposite to the direction in which the bit data is pushed.

FIG. 5 is a schematic diagram illustrating an example of a fundamental matrix according to another embodiment of the present invention. The fundamental matrix 510 is generated based on a polynomial derived based on the circuit design of the LFSR circuit 200 circuit, for example, the above-mentioned relational expressions (11) to (20). Therefore, in this embodiment, the fundamental matrix 510 is a reverse sequence generating matrix. More specifically, the processor 110 can extract the coefficients of each item in the relational expressions (11) to (20) into multiple row vectors, and then generate the fundamental matrix 510 based on the row vectors. As shown in Figure 5, the basic coefficient 500 is a row vector that constitutes the basic matrix 510, and the basic coefficient 500 is generated according to the relation (20) to generate at least one bit of the code sequence. According to an embodiment of the present invention, the basic coefficient 500 is the last vector of the basic matrix 510, and each set of coefficients generated according to the relational expressions (11) to (20) sequentially forms the first to last rows of the basic matrix 510. vector.

Figure 5 also shows a method of generating an output sequence according to the input sequence and the fundamental matrix. The processor 110 can directly multiply the input sequence 520 and the fundamental matrix 510 to generate the output sequence 530.

FIG. 6 is a schematic diagram illustrating an example of a phase shift matrix according to another embodiment of the present invention, in which the phase shift matrix 610 is also a reverse sequence generation matrix. In this embodiment, the processor 110 needs to generate the sequences x0(n-2)˜x9(n-2) based on the sequences x0(n)˜x9(n) that have been reversely phase-shifted by 2 frequency cycles. Therefore, The processor 110 can directly obtain the required output sequence 630 by multiplying the input sequence 620 by the phase shift matrix 610, where the phase shift matrix 610 is the second power of the basic matrix 510 (i.e., the phase shift matrix 610 The result of squaring the fundamental matrix 510).

Based on the above concepts, the present invention may further include a variety of different implementations. According to the first embodiment of the present invention, the memory device 120 can store a fundamental matrix derived according to a generation mechanism of a given code sequence. The processor 110 may read the fundamental matrix from the memory device 120 and generate an output sequence according to the input sequence and the fundamental matrix as described above. For example, to generate a sequence with a phase shift of k frequency cycles, the processor 110 only needs to multiply the input sequence by the kth power of the basic matrix to directly obtain the desired output sequence.

FIG. 7 is an example flowchart illustrating a signal processing method according to the first embodiment of the present invention, which includes the following steps performed by the processor 110:

Step S702: Generate a basic matrix based on at least one set of basic coefficients, where the basic coefficients are used to generate at least one bit of a code sequence.

Step S704: Store the basic matrix in the memory device 120.

Step S706: Generate a phase shift matrix according to the required phase shift amount (k) and the basic matrix.

Step S708: Generate an output sequence according to the input sequence and the phase shift matrix, where the output sequence is the result of the input sequence being phase shifted by k cycles.

Note that additional steps may be inserted or one or more steps may be omitted if substantially the same results are obtained. For example, if the fundamental matrix has been derived, or the memory device 120 already stores the fundamental matrix, step S702 can be omitted, and step S704 can be adjusted to read the fundamental matrix from the memory device 120 for the processor 110 to perform subsequent calculations. . In addition, it can be seen from formulas (2) to (10) that the future values of the 2nd to 10th level shift registers are the current values of the previous level shift register. Therefore, in step S702, only one set of values can be used. The basic coefficients are derived to derive the basic matrix, in which the remaining contents of the basic matrix (for example, the second to last row vectors when the basic matrix is a forward sequence generating matrix) only need to fill in the coefficients 0 and 1 correspondingly at this position. . However, if the mechanism used to generate a code sequence or the corresponding polynomial is relatively complex, in step S702, the basic matrix can be derived based on more than one set of basic coefficients, where the basic coefficients are also derived based on the generation mechanism of the code sequence. .

According to the second embodiment of the present invention, the memory device 120 may store one or more phase shift matrices derived according to the fundamental matrix. The processor 110 may read the required phase shift matrix from the memory device 120 according to the required phase shift amount (k), and generate an output sequence according to the input sequence and the phase shift matrix as described above. For example, to generate a sequence with a phase shift of k frequency cycles, the processor 110 only needs to multiply the input sequence by a phase shift matrix corresponding to the phase shift amount k to directly obtain the desired output sequence.

FIG. 8 is an example flowchart illustrating a signal processing method according to a second embodiment of the present invention, which includes the following steps performed by the processor 110:

Step S802: Store one or more phase shift matrices in the memory device 120, where the phase shift matrices are generated based on a basic matrix and different phase shift amounts as described above.

Step S804: Select a corresponding phase shift matrix according to a preset phase shift amount (k).

Step S806: Generate an output sequence according to the input sequence and the phase shift matrix, where the output sequence is the result of the input sequence being phase shifted by k cycles.

Note that additional steps may be inserted or one or more steps may be omitted if substantially the same results are obtained. For example, if the memory device 120 already stores the phase shift matrix, step S802 may be omitted. In addition, the selection in step S804 may include an operation of reading the memory device 120 .

In addition to the above embodiments of dynamically/real-time calculating the output sequence based on the input sequence, or dynamically/real-time deriving the phase shift matrix based on the basic matrix, the present invention can also store the calculation results in the memory device 120 in advance, and use the lookup table to calculate the output sequence. method to directly obtain the required output sequence.

According to the third embodiment of the present invention, the memory device 120 can also store various results of phase shifting an input sequence for different phase shift amounts (and/or for different input sequences). The processor 110 can directly read the corresponding output sequence from the memory device 120 according to the required phase shift amount (k) and the input sequence. For example, to generate a sequence with a phase shift of k frequency cycles, the processor 110 only needs to query a pre-established table based on the content of the input sequence and the corresponding phase shift amount k to learn what the corresponding output sequence is. The desired output sequence can be obtained directly.

FIG. 9 is an example flowchart illustrating a signal processing method according to a third embodiment of the present invention, which includes the following steps performed by the processor 110:

Step S902: Preliminarily derive the output sequences corresponding to one or more input sequences with respect to different phase shift amounts. The derivation method may adopt the above-mentioned matrix operation.

Step S904: Store the above derivation results in the memory device 120, and establish a lookup table accordingly. An independent lookup table can be established for an input sequence to record the output sequence corresponding to each phase shift amount.

Step S906: Query the lookup table according to the content of the input sequence and the required phase shift amount k to obtain the corresponding output sequence. More specifically, the processor 110 can know which address of the memory device 120 the corresponding output sequence is stored by querying the lookup table, and then accesses the corresponding address of the memory device 120 to obtain the required output sequence.

Please note that additional steps may be inserted or one or more steps may be omitted if substantially the same results are obtained. For example, after steps S902 and S904 are completed, and the generation mechanism of the input sequence and code sequence has not changed, subsequent operations only need to perform step S906.

To sum up, in the embodiments of the present invention, if you want to generate a sequence with a phase shift of k frequency cycles, you only need to perform matrix operations or table lookup to quickly obtain the required sequence. In this way, the PN code sequence can be quickly rearranged according to the required phase shift amount k and the corresponding sequence generation matrix, without having to wait for the LFSR circuit to push k frequency cycles according to the initial seed as in the prior art. Only in this way can the required PN code sequence be obtained, effectively solving the problem of poor efficiency in the existing technology.

In particular, when the value of k is very close to the period N of the cyclic sequence, for example, k = (N-1), if we can only wait for the LFSR circuit to operate for (N-1) frequency cycles according to the existing technology, it can generate The required output sequence must consume a lot of computing time. This problem is common in timing and frequency synchronization operations in communication systems, and is a great problem for system designers. This is because when performing timing and frequency synchronization, it is necessary to try the results of the seed sequence being phase-shifted by multiple different phase shifts, and perform a correlation operation with the received signal to accurately estimate the timing offset and frequency. Offset. In addition, the way the LFSR circuit generates the sequence in the prior art cannot generate the sequence in the opposite direction. Therefore, in the prior art, the synchronization operation may take too much time due to the large value of k. However, since forward phase shifting of the seed sequence by (N-1) cycles is equivalent to reverse phase shifting of the seed sequence by 1 cycle, in this case, applying the signal processing method and signal processing device proposed by the present invention, The required output sequence can be obtained directly by multiplying the seed sequence and the reverse sequence generation matrix. This can effectively solve the above-mentioned problem of taking too long to generate the required sequence.

The above are only preferred embodiments of the present invention. All equivalent changes and modifications made in accordance with the patent scope of the present invention shall fall within the scope of the present invention.

【Symbol Description】

100 signal processing device

110 processor

120 memory device

200 Linear feedback shift register circuit

300, 500 basic coefficient

310, 510 basic matrix

320, 420, 520, 620 input sequence

410, 610 phase shift matrix

CLK frequency signal

Seq_Out, 330, 430, 530, 630 output sequence

SR(0), SR(1), SR(2), SR(3), SR(4),

SR(5), SR(6), SR(7), SR(8), SR(9)x0(n),

x1(n), x2(n), x3(n), x4(n), x5(n), x6(n),

shift register value

x7(n), x8(n), x9(n), x0(n+1), x1(n+1),

x2(n+1), x3(n+1), x4(n+1), x5(n+1),

x6(n+1), x7(n+1), x8(n+1), x9(n+1)

Claims (4)

1. A signal processing method for a signal processing apparatus, the signal processing apparatus comprising a processor, the signal processing method comprising the steps performed by the processor of:

generating a base matrix according to a plurality of base coefficients, wherein the base coefficients are used for generating at least one bit of a code sequence;

generating a phase shift matrix according to a preset phase shift amount and the basic matrix; and

generating an output sequence based on an input sequence and the phase shift matrix,

wherein the output sequence is the result of the input sequence after being phase shifted by k cycles, wherein k is the preset phase shift amount,

wherein a set of said basis coefficients is a row of vectors constituting said basis matrix,

and wherein the phase shift matrix is to the power of the k of the base matrix, and the step of generating the output sequence from the input sequence and the phase shift matrix further comprises:

the input sequence is multiplied by the phase shift matrix to produce the output sequence.

2. A signal processing method for a signal processing apparatus, the signal processing apparatus comprising a processor and a memory device, the signal processing method comprising the steps of, performed by the processor:

storing a plurality of phase shift matrices in the memory device, wherein the phase shift matrices are generated according to a base matrix and different phase shift amounts, and the base matrix is used for generating a code sequence;

selecting a corresponding phase shift matrix from the plurality of phase shift matrices according to a preset phase shift amount; and

generating an output sequence according to an input sequence and the phase shift matrix,

wherein the output sequence is the result of the input sequence after being phase shifted by k cycles, wherein k is the preset phase shift amount,

wherein the base matrix is generated from a plurality of sets of base coefficients, the base coefficients being used to generate at least one bit of the code sequence, and a set of the base coefficients being a row of vectors constituting the base matrix,

and wherein the corresponding phase shift matrix is the k power of the base matrix, and the step of generating the output sequence from the input sequence and the corresponding phase shift matrix further comprises:

multiplying the input sequence with the corresponding phase shift matrix to produce the output sequence.

3. A signal processing apparatus comprising:

a memory device storing at least one phase shift matrix; and

a processor coupled to the memory device, reading the phase shift matrix from the memory device, and generating an output sequence based on an input sequence and the phase shift matrix,

wherein the phase shift matrix is generated according to a base matrix and a predetermined phase shift amount, the base matrix is used for generating a code sequence, and the output sequence is the result of the input sequence after being phase-shifted by k cycles, wherein k is the predetermined phase shift amount,

wherein the processor further generates the base matrix based on a plurality of sets of base coefficients, the base coefficients being used to generate at least one bit of the code sequence, and a set of the base coefficients being a row of vectors constituting the base matrix,

and wherein the phase shift matrix is the kth power of the base matrix, and the processor multiplies the input sequence with the phase shift matrix to produce the output sequence.

4. The signal processing device of claim 3 wherein the processor further generates a plurality of phase shift matrices based on the different amounts of phase shift and the base matrix and stores the phase shift matrices in the memory device.