[go: up one dir, main page]

CN112949251B - Design and use method based on ASIC main control chip pin customization - Google Patents

Design and use method based on ASIC main control chip pin customization Download PDF

Info

Publication number
CN112949251B
CN112949251B CN202110438271.5A CN202110438271A CN112949251B CN 112949251 B CN112949251 B CN 112949251B CN 202110438271 A CN202110438271 A CN 202110438271A CN 112949251 B CN112949251 B CN 112949251B
Authority
CN
China
Prior art keywords
main control
asic
control chip
chip
asic main
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110438271.5A
Other languages
Chinese (zh)
Other versions
CN112949251A (en
Inventor
黄思巍
刘敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Hongjingwei Technology Co ltd
Original Assignee
Zhongke Yixin Technology Shenzhen Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhongke Yixin Technology Shenzhen Co ltd filed Critical Zhongke Yixin Technology Shenzhen Co ltd
Priority to CN202110438271.5A priority Critical patent/CN112949251B/en
Publication of CN112949251A publication Critical patent/CN112949251A/en
Application granted granted Critical
Publication of CN112949251B publication Critical patent/CN112949251B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本发明公开了一种基于ASIC主控芯片管脚自定义的设计和使用方法,包括嵌入式存储芯片,嵌入式存储芯片包括ASIC主控芯片、闪存芯片和基板;ASIC主控芯片管脚自定义方法:S1,设计好所有可能用到的功能模块;S2,根据pad管脚数来定义ASIC主控芯片管脚数量;S3,ASIC主控芯片内部增加OTP单元;ASIC主控芯片使用方法:Q1,设计基板,保证ASIC主控芯片和闪存芯片pad管脚的金线连接不交叉;Q2,对ASIC主控芯片的pad管脚进行复用;Q3,PC端工具自动对OTP单元进行扫描;Q4,检测OTP单元内是否有数据;Q5,若是,正常使用ASIC主控芯片;Q6,若否,自定义pad管脚并写入OTP单元;再执行步骤Q5;一颗芯片根据不同用途自行配置成专有的ASIC芯片,达到需要多颗不同的ASIC芯片才能达到的功能和效果。

Figure 202110438271

The invention discloses a design and use method based on pin customization of an ASIC main control chip, comprising an embedded memory chip, the embedded memory chip includes an ASIC main control chip, a flash memory chip and a substrate; the pin customization of the ASIC main control chip Method: S1, design all possible functional modules; S2, define the number of pins of the ASIC main control chip according to the number of pad pins; S3, add an OTP unit inside the ASIC main control chip; ASIC main control chip usage: Q1 , Design the substrate to ensure that the gold wires of the ASIC main control chip and the flash chip pad pins do not cross; Q2, reuse the pad pins of the ASIC main control chip; Q3, the PC-side tool automatically scans the OTP unit; Q4 , check whether there is data in the OTP unit; Q5, if it is, use the ASIC main control chip normally; Q6, if not, customize the pad pins and write it into the OTP unit; then go to step Q5; a chip is configured according to different purposes. Proprietary ASIC chips to achieve functions and effects that require multiple different ASIC chips.

Figure 202110438271

Description

一种基于ASIC主控芯片管脚自定义的设计和使用方法A design and use method based on ASIC master chip pin customization

技术领域technical field

本发明涉及半导体芯片领域,尤其涉及一种基于ASIC主控芯片管脚自定义的设计和使用方法。The invention relates to the field of semiconductor chips, in particular to a design and use method based on pin customization of an ASIC main control chip.

背景技术Background technique

对于传统的ASIC主控芯片来说,因为芯片在流片时所有的芯片管脚功能已经被预先定义,不能更改,对于不同厂家的闪存芯片,为了不使金线交叉,只能不停的更换底下的基板设计,有时甚至需要常备几十款不同的基板,不仅浪费资源,增加设计复杂度,还大大影响客户的新产品推出时间和交期。For the traditional ASIC main control chip, because all chip pin functions have been pre-defined and cannot be changed when the chip is tape-out, for flash memory chips of different manufacturers, in order to prevent the gold wires from crossing, they can only be replaced continuously The underlying substrate design sometimes even requires dozens of different substrates to be kept, which not only wastes resources, increases the design complexity, but also greatly affects the customer's new product launch time and delivery time.

发明内容SUMMARY OF THE INVENTION

本发明的目的是为了解决现有技术中存在的缺点,而提出的一种基于ASIC主控芯片管脚自定义的设计和使用方法。The purpose of the present invention is to propose a design and use method based on pin customization of an ASIC main control chip in order to solve the shortcomings existing in the prior art.

为了实现上述目的,本发明采用了如下技术方案:In order to achieve the above object, the present invention adopts the following technical solutions:

一种基于ASIC主控芯片管脚自定义的设计和使用方法,包括嵌入式存储芯片,所述嵌入式存储芯片包括ASIC主控芯片、闪存芯片和基板;其特征在于,所述ASIC主控芯片管脚自定义方法包括以下步骤:A design and use method based on pin customization of an ASIC main control chip, comprising an embedded memory chip, the embedded memory chip comprising an ASIC main control chip, a flash memory chip and a substrate; characterized in that the ASIC main control chip The pin customization method includes the following steps:

步骤S1,所述ASIC主控芯片设计阶段设计好所有可能用到的功能模块;Step S1, in the design stage of the ASIC main control chip, all possible functional modules are designed;

步骤S2,根据最复杂应用需要的pad管脚数来定义所述ASIC主控芯片管脚数量;Step S2, define the number of pins of the ASIC main control chip according to the number of pad pins required by the most complex application;

步骤S3,在所述ASIC主控芯片内部增加OTP单元;Step S3, adding an OTP unit inside the ASIC main control chip;

所述ASIC主控芯片使用方法包括以下步骤:The method for using the ASIC main control chip includes the following steps:

步骤Q1,设计基板,根据要使用的功能,保证所述ASIC主控芯片和闪存芯片pad管脚的金线连接不交叉;Step Q1, design the substrate, according to the function to be used, ensure that the gold wire connection between the ASIC main control chip and the flash chip pad pin does not cross;

步骤Q2,根据最终产品的需求,对所述ASIC主控芯片的pad管脚进行复用;Step Q2, multiplexing the pad pins of the ASIC main control chip according to the requirements of the final product;

步骤Q3,第一次使用所述ASIC主控芯片时,PC端工具自动对OTP单元进行扫描;Step Q3, when using the ASIC main control chip for the first time, the PC-side tool automatically scans the OTP unit;

步骤Q4,检测OTP单元内是否有数据;Step Q4, detects whether there is data in the OTP unit;

步骤Q5,若是,存在数据,客户根据自己定义的pad管脚功能正常使用所述ASIC主控芯片;Step Q5, if there is data, the customer normally uses the ASIC main control chip according to the pad pin function defined by himself;

步骤Q6,若否,不存在数据,需要客户根据自己需求自定义pad管脚,并写入OTP单元;再执行步骤Q5。Step Q6, if no, there is no data, the customer needs to customize the pad pins according to their own needs, and write them into the OTP unit; then go to step Q5.

优选的,所述S2中,预先估算出所述ASIC主控芯片在终端客户应用时,最多需要使用到多少pad管脚,则所述ASIC主控芯片流片时预留的pad数等于最多需要使用到的pad管脚的数目,所述ASIC主控芯片其他的功能都采用pad复用方式。Preferably, in the step S2, it is estimated in advance how many pad pins the ASIC main control chip needs to use when the terminal customer is applied, and the number of pads reserved when the ASIC main control chip is taped out is equal to the maximum number of pads required. The number of pad pins used, and other functions of the ASIC main control chip adopt the pad multiplexing method.

优选的,所述S3中,所述OTP单元是efuse模块或eeprom模块。Preferably, in the S3, the OTP unit is an efuse module or an eeprom module.

优选的,所述模块的物理单元值容许写入一次,不可擦除,不可复写。Preferably, the physical unit value of the module can be written once, cannot be erased, and cannot be rewritten.

优选的,所述ASIC主控芯片和所述闪存芯片设置于所述基板上。Preferably, the ASIC main control chip and the flash memory chip are arranged on the substrate.

优选的,所述ASIC主控芯片和所述闪存芯片通过导线连接。Preferably, the ASIC main control chip and the flash memory chip are connected by wires.

优选的,所述导线为金线。Preferably, the wires are gold wires.

与现有技术相比,本发明的有益效果是:Compared with the prior art, the beneficial effects of the present invention are:

本发明设计一种基于ASIC主控芯片管脚自定义的设计和使用方法,等同于是一颗芯片可以根据不同用途自行配置成自己专有的ASIC芯片,ASIC芯片流片时,通过减少ASIC芯片的pad管脚数,使得终端客户在有限的管脚上,复用pad管脚,自定义适合自己的管脚功能,达到需要多颗不同的ASIC芯片才能达到的功能和效果;以前实现不同的应用需要多颗ASIC专用芯片,现在只需要一颗,一方面大大降低ASIC芯片的成本,二是大幅降低ASIC芯片下游终端客户备货成本,再也不需要设计和预备很多套的基板,增加他们产品设计灵活性,能快速将新产品推出市场。The present invention designs a design and use method based on the customization of the pins of the ASIC main control chip, which is equivalent to a chip that can be configured into its own proprietary ASIC chip according to different purposes. The number of pad pins enables end customers to reuse pad pins on a limited number of pins, and customize their own pin functions to achieve functions and effects that require multiple different ASIC chips. Multiple ASIC-specific chips are needed, and now only one is needed. On the one hand, the cost of ASIC chips is greatly reduced, and the other is to greatly reduce the stocking cost of downstream end customers of ASIC chips. It is no longer necessary to design and prepare many sets of substrates, increasing their product design. Flexibility to bring new products to market quickly.

附图说明Description of drawings

图1为本发明提出的基于ASIC主控芯片管脚自定义的设计方法;Fig. 1 is the design method based on ASIC main control chip pin self-definition proposed by the present invention;

图2为本发明提出的嵌入式存储芯片外形图;Fig. 2 is the outline drawing of the embedded memory chip proposed by the present invention;

图3为本发明提出的嵌入式存储芯片内部逻辑结构图;Fig. 3 is the internal logic structure diagram of the embedded memory chip proposed by the present invention;

图4为本发明提出的嵌入式存储芯片内部硬件打线图;4 is a wiring diagram of the internal hardware of the embedded memory chip proposed by the present invention;

图5为本发明提出的基于ASIC主控芯片管脚自定义的使用方法。FIG. 5 is a method of using pin customization based on the ASIC main control chip proposed by the present invention.

图例说明:illustration:

1、嵌入式芯片, 2、ASIC主控芯片,1. Embedded chip, 2. ASIC main control chip,

3、闪存芯片, 4、基板。3. Flash memory chip, 4. Substrate.

具体实施方式Detailed ways

下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

在本发明的描述中,需要说明的是,术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制;术语“第一”、“第二”、“第三”仅用于描述目的,而不能理解为指示或暗示相对重要性;此外,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本发明中的具体含义。In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limiting the invention; the terms "first", "second", "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; furthermore, unless otherwise Clearly stipulated and defined, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or a Electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

参照图1至图5,一种基于ASIC主控芯片管脚自定义的设计和使用方法,包括嵌入式存储芯片1,嵌入式存储芯片1包括ASIC主控芯片2、闪存芯片3和基板4;ASIC主控芯片2管脚自定义方法包括以下步骤:S1,ASIC主控芯片2设计阶段设计好所有可能用到的功能模块;S2,根据最复杂应用需要的pad管脚数来定义ASIC主控芯片2管脚数量;S3,在ASIC主控芯片2内部增加OTP单元;ASIC主控芯片2使用方法包括以下步骤:Q1,设计基板,根据要使用的功能,保证ASIC主控芯片2和闪存芯片3的pad管脚的金线连接不交叉;Q2,根据最终产品的需求,对ASIC主控芯片2的pad管脚进行复用;Q3,第一次使用ASIC主控芯片2时,PC端工具自动对OTP单元进行扫描;Q4,检测OTP单元内是否有数据;Q5,若是,存在数据,客户根据自己定义的pad管脚功能正常使用ASIC主控芯片2;Q6,若否,不存在数据,需要客户根据自己需求自定义pad管脚,并写入OTP单元;再执行步骤Q5。Referring to FIGS. 1 to 5 , a design and use method based on pin customization of an ASIC main control chip, including an embedded memory chip 1, and the embedded memory chip 1 includes an ASIC main control chip 2, a flash memory chip 3 and a substrate 4; The pin customization method of ASIC main control chip 2 includes the following steps: S1, design all possible functional modules in the design stage of ASIC main control chip 2; S2, define the ASIC main control according to the number of pad pins required by the most complex application The number of pins of chip 2; S3, add an OTP unit inside the ASIC main control chip 2; the use method of the ASIC main control chip 2 includes the following steps: Q1, design the substrate, and ensure the ASIC main control chip 2 and the flash memory chip according to the functions to be used The gold wires of the pad pins of 3 are not crossed; Q2, according to the needs of the final product, the pad pins of the ASIC main control chip 2 are multiplexed; Q3, when the ASIC main control chip 2 is used for the first time, the PC-side tool Automatically scan the OTP unit; Q4, check whether there is data in the OTP unit; Q5, if there is data, the customer can use the ASIC master chip 2 normally according to the pad pin function defined by himself; Q6, if no, there is no data, Customers need to customize the pad pins according to their own needs and write them into the OTP unit; then go to step Q5.

其中,S2中,预先估算出ASIC主控芯片2在终端客户应用时,最多需要使用到多少pad管脚,则该ASIC主控芯片2流片时预留的pad数等于最多需要使用到的pad管脚的数目,ASIC主控芯片2其他的功能都采用pad复用方式。Among them, in S2, it is estimated in advance how many pad pins the ASIC main control chip 2 needs to use in the end customer application, then the number of pads reserved when the ASIC main control chip 2 is taped out is equal to the pads that need to be used at most The number of pins, and other functions of the ASIC main control chip 2 use pad multiplexing.

S3中,OTP单元是efuse模块或eeprom模块;该模块的物理单元值容许写入一次,不可擦除,不可复写。In S3, the OTP unit is an efuse module or an eeprom module; the physical unit value of this module can be written once, but cannot be erased or rewritten.

ASIC主控芯片2和闪存芯片3设置于基板4上;ASIC主控芯片2和闪存芯片3通过导线连接,导线为金线;并且保证ASIC主控芯片2和闪存芯片3的pad管脚的金线连接不交叉。The ASIC main control chip 2 and the flash memory chip 3 are arranged on the substrate 4; the ASIC main control chip 2 and the flash memory chip 3 are connected by wires, and the wires are gold wires; and the gold of the pad pins of the ASIC main control chip 2 and the flash memory chip 3 is guaranteed. Wire connections do not cross.

由于主控制芯片一般是以未封装前的dies形式存在,所以终端客户在使用时一般会设计一套基板,把主控芯片的die和闪存芯片的一颗或多颗die绑定到该基板上,然后通过BGA或者其他封装方式做成最终的嵌入式存储芯片。Since the main control chip generally exists in the form of unpackaged dies, end customers usually design a set of substrates to bind the die of the main control chip and one or more dies of the flash memory chip to the substrate. , and then make the final embedded memory chip through BGA or other packaging methods.

ASIC主控芯片流片时,通过减少ASIC主控芯片的pad管脚数,使得终端客户在有限的管脚上,复用pad管脚,自定义适合自己的管脚功能,从而实现类似FPGA芯片才有的芯片管脚自由定义功能,以前实现不同的应用需要多颗ASIC主控专用芯片,现在只需要一颗,一方面大大降低ASIC主控芯片每块成本,二是大幅降低ASIC主控芯片下游终端客户备货成本的同时,还增加他们产品设计灵活性,能快速将新产品推出市场。When the ASIC main control chip is taped out, by reducing the number of pad pins of the ASIC main control chip, the end customer can reuse the pad pins on the limited pins, and customize the pin functions suitable for them, so as to achieve a similar FPGA chip. Only one chip pin can define functions freely. In the past, multiple ASIC main control chips were needed to realize different applications. Now only one is needed. On the one hand, the cost of each ASIC main control chip is greatly reduced, and the other is to greatly reduce the ASIC main control chip. While reducing the stocking cost of downstream end customers, it also increases their product design flexibility and can quickly introduce new products to the market.

以上,仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,根据本发明的技术方案及其发明构思加以等同替换或改变,都应涵盖在本发明的保护范围之内。The above are only preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Equivalent replacements or changes to the inventive concept shall all fall within the protection scope of the present invention.

Claims (7)

1. A design and use method based on ASIC main control chip pin self-definition comprises an embedded memory chip, wherein the embedded memory chip comprises an ASIC main control chip, a flash memory chip and a substrate; the method is characterized by comprising the following steps:
step S1, designing all functional modules possibly used in the ASIC main control chip design stage;
step S2, defining the pin number of the ASIC main control chip according to the pad pin number required by the most complex application;
step S3, adding an OTP unit inside the ASIC main control chip;
the application method of the ASIC main control chip comprises the following steps:
step Q1, designing a substrate, and ensuring that the gold wire connections of the ASIC main control chip and the pad pins of the flash memory chip are not crossed according to the functions to be used;
step Q2, multiplexing the pad pins of the ASIC main control chip according to the requirements of the final product;
step Q3, when the ASIC master control chip is used for the first time, the PC end tool automatically scans the OTP unit;
step Q4, detecting whether the OTP unit has data;
step Q5, if yes, data exist, and the client normally uses the ASIC main control chip according to the function of the pad pin defined by the client;
step Q6, if no, the client needs to self-define the pad pin according to the own requirement and write the pad pin into the OTP unit; step Q5 is then performed.
2. The method as claimed in claim 1, wherein in S2, it is estimated in advance how many pad pins the ASIC main control chip needs to use at most when it is applied by a terminal client, and the number of reserved pads in the ASIC main control chip streaming is equal to the number of the pad pins that need to be used at most, and other functions of the ASIC main control chip all use a pad multiplexing mode.
3. The ASIC master control chip pin customization based design and use method according to claim 1, wherein in S3, the OTP unit is an effect module or an eeprom module.
4. The ASIC host chip pin customization-based design and use method of claim 3, wherein the physical cell values of the module are write-once, non-erasable, non-rewritable allowed.
5. The method of claim 1, wherein the ASIC host chip and the flash memory chip are disposed on the substrate.
6. The method as claimed in claim 5, wherein the ASIC host chip and the flash memory chip are connected by wires.
7. The ASIC master control chip pin customization-based design and use method of claim 6, wherein the wires are gold wires.
CN202110438271.5A 2021-04-22 2021-04-22 Design and use method based on ASIC main control chip pin customization Active CN112949251B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110438271.5A CN112949251B (en) 2021-04-22 2021-04-22 Design and use method based on ASIC main control chip pin customization

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110438271.5A CN112949251B (en) 2021-04-22 2021-04-22 Design and use method based on ASIC main control chip pin customization

Publications (2)

Publication Number Publication Date
CN112949251A CN112949251A (en) 2021-06-11
CN112949251B true CN112949251B (en) 2022-05-06

Family

ID=76233288

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110438271.5A Active CN112949251B (en) 2021-04-22 2021-04-22 Design and use method based on ASIC main control chip pin customization

Country Status (1)

Country Link
CN (1) CN112949251B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106199177A (en) * 2016-08-26 2016-12-07 贵州电网有限责任公司电力科学研究院 General-purpose interface for electric energy meter
CN108388531A (en) * 2018-02-09 2018-08-10 深圳国微技术有限公司 A kind of chip and its pin multiplexing method
CN112492752A (en) * 2020-11-02 2021-03-12 苏州浪潮智能科技有限公司 Chip pin extension device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008051940A2 (en) * 2006-10-23 2008-05-02 Virident Systems, Inc. Methods and apparatus of dual inline memory modules for flash memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106199177A (en) * 2016-08-26 2016-12-07 贵州电网有限责任公司电力科学研究院 General-purpose interface for electric energy meter
CN108388531A (en) * 2018-02-09 2018-08-10 深圳国微技术有限公司 A kind of chip and its pin multiplexing method
CN112492752A (en) * 2020-11-02 2021-03-12 苏州浪潮智能科技有限公司 Chip pin extension device

Also Published As

Publication number Publication date
CN112949251A (en) 2021-06-11

Similar Documents

Publication Publication Date Title
JP7411633B2 (en) Logical transport over fixed PCIe physical transport network
US20190139592A1 (en) Apparatus, method and system for providing termination for multiple chips of an integrated circuit package
CN100444145C (en) Dynamic Reconfiguration of PCI Express Links
CN107463456A (en) A kind of system and method for lifting double netcard NCSI management system switching efficiencies
US9058458B2 (en) Structure for logic circuit and serializer-deserializer stack
US20160259746A1 (en) Usb type-c cable and method for reading/writing a chip in a usb type-c cable
CN108388531A (en) A kind of chip and its pin multiplexing method
US11552035B2 (en) Electronic package with stud bump electrical connections
CN112949251B (en) Design and use method based on ASIC main control chip pin customization
CN112988271A (en) System and method for dynamically configuring FPGA (field programmable Gate array) in passive SelectMAP (selectable MAP) mode
US10998014B2 (en) Semiconductor dies supporting multiple packaging configurations and associated methods
CN103890743B (en) The IO power managements of host computer control
US7484027B1 (en) Apparatus and method for configurable device pins
CN112204735B (en) Semiconductor chip and manufacturing method thereof
CN115632976A (en) PCIE transaction layer message generation method, device and storage medium
CN101303885A (en) Multi-chip package memory module
CN104123257B (en) Universal serial bus device, communication method and computer readable storage medium
CN110347435A (en) Automatically configure the BIOS and method of PCIe slot
CN116450242A (en) A system, method, device and storage medium for configuring FPGA
CN116467240A (en) SAS expander topology configuration method, SAS expander topology configuration device, SAS expander and storage medium
CN101387966A (en) Computer equipment with basic input and output system selection function
CN112582286B (en) Packaging method, device, equipment and medium
CN115729337A (en) DDR5 power management system
CN101995523A (en) Structure and method for testing interconnection active device
CN107634055A (en) Electrostatic discharge protection framework

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20250613

Address after: 518000 Guangdong Province Shenzhen City Bao'an District Xixiang Street Guxing Community Starlight Company Industrial Park Building 510

Patentee after: Shenzhen Hongjingwei Technology Co.,Ltd.

Country or region after: China

Address before: 518000 Guangdong Province Shenzhen City Pingshan Street Liulian Community Pingshan Avenue 2007 Innovation Plaza C2311-C2312

Patentee before: Zhongke Yixin Technology (Shenzhen) Co.,Ltd.

Country or region before: China

TR01 Transfer of patent right