CN1129329A - Programmed regulating-controlled interlace memory administration system - Google Patents
Programmed regulating-controlled interlace memory administration system Download PDFInfo
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- CN1129329A CN1129329A CN 95100337 CN95100337A CN1129329A CN 1129329 A CN1129329 A CN 1129329A CN 95100337 CN95100337 CN 95100337 CN 95100337 A CN95100337 A CN 95100337A CN 1129329 A CN1129329 A CN 1129329A
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- 230000001427 coherent effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000009471 action Effects 0.000 description 5
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Abstract
The programmable regulation-control interlace memory management system mainly includes a flating buffer, memory, program control network and a central controller. Its central controller is used for controlling the number of floating buffers of each access end, the movement of each floating buffer between the access ends and switch of each path of the program control network which is a complete network formed from several access ends, and each access end is made of several floating buffers, so that it uses one processor or bus main control unit to implement memory data access operation in a shorter time, and can raise the accuracy of data.
Description
The present invention relates to a kind of programmed regulating-controlled interlace memory administration system, be particularly related to a kind of electronic logic circuit that is applicable to computing machine, workstation and any need use storeies (Momery) etc., and adopt a plurality of special impact dampers (Buffer), the characteristic that requires for access according to each processor (Processor) or bus master controller (Bus Master), adapt to the resources allocation between impact damper and storer, make each processor or bus master controller in the short time, to finish the work of memory data access.
Traditional dynamic RAM Controller (Dynamic Random Accessmemory Controller) adopts passive mode of operation.Can only accept and handle the requirement of a processor or bus master controller within the same time to the storage access data.When second processor or bus master controller require the storage access data simultaneously, must wait for the end-of-job of previous access data after, just can proceed.In traditional computing machine or workstation system, most time, only have a processor or bus master controller requirement and use storer, therefore the work efficiency of Memory Controller is unimportant, make most conventional computer system design only emphasize the function of cache memory (CacheMemory), and ignored the efficient of Memory Controller.Now because computer technology is progressive fast and multimedia (the development of science and technology of Multi-Media).Multiprocessor (the computer system of Multi-Processor) or have the computing machine of a plurality of bus master controller peripherals, very general, these computer systems all have high chance to produce plurality of processors or bus master controller requires to make memory-aided phenomenon simultaneously.Therefore this computer system all requires high efficiency Memory Controller, becomes traffic bottlenecks to exempt because of storer uses path, and the problem that causes systemic-function to reduce.Present solution on the market, focus on the improvement of storer mostly, attempt reduces the required time of memory data access, just develops storer faster, or the design multiport (storer of Mulli-Port) solves the bottleneck problem that storer uses path.Synchronous Dynamic Random Access Memory (Synchronous DRAM) etc. for example, but often price is higher for these novel storeies.Some in addition require special operation circuit, therefore, but and do not meet economic benefit though novel storer can be dealt with problems.
Therefore, the object of the present invention is to provide a kind of programmed regulating-controlled interlace memory administration system, it utilizes special impact damper, and the system architecture of control able to programme (Ar-chitecture), effective allocate memory resource, make each action, from the access requirement in two different sources (Source), in the short time, finish especially simultaneously memory access.
Another object of the present invention is to provide a kind of programmed regulating-controlled interlace memory administration system, it can avoid working as a plurality of processors or bus master controller requires to use storer simultaneously, when making storer become traffic bottlenecks, the problem that causes system performance (Performance) to reduce.
Another object of the present invention is to provide a kind of programmed regulating-controlled interlace memory administration system, the hardware configuration of its use scalable (Scalable), make single port (SinglePort) storer can do with the requirement of access data simultaneously of a plurality of primary controllers, and need not use extra memory storage or special storer.
A further object of the present invention is to provide a kind of regulation and control interleave memory management system able to programme, it can be simplified to very economical logic, be applicable to the minicomputer system that two to three primary controllers are only arranged, or be extensible to complicated digital network, (DigitalNetwork), apply to large-scale matrix computer system (Vector machine).
In order to achieve the above object, the present invention mainly comprises unsteady impact damper, access terminals, program-controlled network and central controller, the number of the unsteady impact damper that it has with each access terminals of central controller controls, each unsteady impact damper moving between access terminals, and the switch in each path in the program-controlled network, and access terminals is constituted by several unsteady impact dampers, and access terminals also interconnects and constitutes a program-controlled network, it can deal with the requirement of access data simultaneously of a plurality of primary controllers, and need not use extra memory storage or special storer, simultaneously, and be extensible to complicated digital network, apply to the large-scale matrix computer system, and also reduce the processing time relatively.
As for detailed construction of the present invention, effect and effect then can be further understood with reference to the following explanation of being done in conjunction with the accompanying drawings:
Fig. 1 is unsteady buffer structure figure of the present invention.
Fig. 2 is the structural drawing of access terminals of the present invention.
Fig. 3 implements illustration for the program-controlled network of access terminals of the present invention.
Fig. 4 is another enforcement illustration of program-controlled network of access terminals of the present invention.
Fig. 5 is the normal running program flow diagram of the unsteady impact damper of the present invention.
Fig. 6 is the maintenance program process flow diagram of the unsteady impact damper of the present invention.
Fig. 7 wants the control program process flow diagram for what the present invention floated impact damper.
Fig. 8 is the unsteady buffer allocation program flow diagram of access terminals of the present invention.
The contrast of each parts label and title is as follows among the figure:
100. ... central controller connects 1001. ... central authorities' control signal
101. ... the primary controller flow joint
102. ... memory interface
1011.1021. ... data access 1012.1022. ... access control signal
103. ... control sluice 1031. ... write data
104. ... data register 1041. ... reading of data
200. ... access terminals 201. ... impact damper floats
202. ... primary controller 203. ... storer
400. ... unsteady impact damper is accepted instruction
4001. ... primary controller requires reading of data
4002. ... primary controller requires to write data
401. ... whether data are in register
402.…403.…404.…405.…406.… 407.…408.…409.…410.… 411.…500.…5001.…5002.…501.…502.… 503.…504.…505.…506.…507.…508.…509.…600.…6000.…6001.…601.…602.…603.…604.…605.…606.…
607. ... notice access terminals controller changes the impact damper that floats to original state
608. ... accepting central controller accept to set and to comprise virtual address translation tables and extracting rule in advance
700. ... the access terminals controller prepares to accept instruction
701. ... whether data are in arbitrary unsteady impact damper
702. ... requiring central controller to link up safeguards
703. ... link up and safeguard end
704. ... whether accept new unsteady impact damper
705. ... reception is from the unsteady impact damper of other access terminals in-migration
706. ... connect the access terminals data bus
707. ... start the impact damper that floats and accept the primary controller instruction
708. ... the selected least commonly used or vacant impact damper that floats
709. ... eliminate old data
710. ... set the impact damper that floats and accept the primary controller instruction
Regulation and control interleave Memory Management Unit able to programme of the present invention, hereinafter to be referred as program control interleave note pipe device (PIMMU), it can be divided into four main portions, is respectively unsteady impact damper, access terminals, program-controlled network and central controller, and each several part is described as follows:
(1) unsteady impact damper:
Unsteady impact damper is a numerical data register that floats, it back and forth migration in program-controlled network, and accept the instruction of central controller, in program-controlled network, float to the access terminals (Access Port) of appointment.Each access terminals is specific primary controller and has.In a single day unsteady impact damper arrives the access terminals of appointment, promptly become the register of this primary controller to the storage access data, in program control interleave note pipe device, primary controller is defined as follows: program control interleave note pipe device can require each to make memory-aided device (Device), be considered as an aggressive device (Active Device), and all aggressive devices that will use same address space (Address Space) and have same access (Access) characteristic, be considered as a primary controller, a primary controller may be a central logic arithmetic processor, or all are positioned at the bus master controller of regional bus, and program control interleave note pipe device can be via the control of program, or prior setting, determine some aggressive devices to range same primary controller.
(2) access terminals:
Each primary controller all has one's own access terminals, when primary controller during to the storage access data, all finishes the action of access by access terminals.Each access terminals all can have one to several unsteady impact dampers, and actual number is determined by central controller.When primary controller required writing data into memory, this batch data was waited for the permission of central controller with writing earlier in the impact damper that floats, real again write store.When primary controller requires from memory read data, this batch data will deposit unsteady impact damper in by storer earlier, allow primary controller to obtain this batch data again from the impact damper that floats.
(3) program-controlled network:
Program-controlled network is the complete network (CompleteNetwork) that a plurality of access terminals is formed, and it allows unsteady impact damper to move around on the track that is formed by complete network, advances to another different access terminals from an access terminals.The structure of program-controlled network can be via the instruction of central controller, controls the unlatching of each paths (Path) or closes.Under some special situation, central controller can cut out the path in some program-controlled networks, to limit the motion of the impact damper that floats.
(4) central controller:
The action of the whole program control interleave note pipe device of central controller controls.The project of its control comprises that each access terminals has the number of the impact damper that floats.The motion of each unsteady impact damper and access features, and the network structure of program-controlled network.Central controller must be safeguarded the continuity (Coherence) of all data simultaneously.When especially primary controller has exclusive high-speed buffer, central controller will prosecution each batch from the data of storage access, guarantee that same batch data has only a copy of revising (Modified Copy).
Figure 1 shows that the structural drawing of the unsteady impact damper of the present invention, central control interface 100, primary controller flow joint 101, memory interface 102, control sluice 103 and data register 104 have wherein been comprised, it connects central controller with central controller interface 100, and accept the instruction of central controller with primary controller floating interface 101, the data bus that connects different access terminals makes and floats the migration of impact damper energy in program-controlled network; Data register 104 is a memory storage, preserves the data that primary controller reads storer, and other has 102 storeies that connect the outside of a memory interface, is the output signal of the impact damper that floats.
As shown in Figure 2, it is the structural drawing of access terminals, in access terminals 200, formed by several unsteady impact dampers 201, and access terminals 200 is the data transfer media of 203 of primary controller 202 and storeies, and access terminals 200 mutually between and can do the transport flow (as shown in Figure 3, Figure 4) of data, the complete network of 200 compositions of its each access terminals, be considered as program-controlled network, each bar straight line is the path of network, unsteady impact damper can migration on every paths, and its path all set by the central controller switch, and the part of dotted line shown in the figure is the path for being closed then.
And program control interleave note pipe device comprises three groundwork programs, be followed successively by the buffer operation program (Folating Buffer Operating Procedure) of floating, the unsteady buffer allocation program (floatingBuffer Allocation Procedure) that access terminals controller (Access Port Controller) is carried out, and central controller is swept the coherent maintenance program (Data Coherence Maintainance Procedure) of capable data.Each working routine is described below:
(1) unsteady buffer operation program:
Unsteady impact damper is a most principal work device in the program control interleave note pipe device, and its basic operation is divided into three levels, and the bottom is the directly normal running program (Normal Uperating Procedure) when floating the buffer accesses data of primary controller.Last layer is the maintenance program (Maintainance Procedure) that the access terminals controller is set float impact damper duty (Operating Status) and data management work.The superiors are that the unsteady impact damper of central controller indication moves or set virtual address translation tables and the major control program (Main Controlling Procedure) of extracting data rule in advance.The working routine of higher level has higher execution sequence.After the working routine of high level is finished, just control can be given to the working routine of bottom.The action of each working routine is respectively as following narration.
(a) normal running program:
As shown in Figure 5, when primary controller required access data, each unsteady impact damper multilayer that is positioned at access terminals started the normal running program.The normal running program can be checked the virtual address sign (Virtual Address Tag) of the impact damper that floats earlier, if require the virtual address of access data to conform to, represent that then this batch data is positioned at data register and allows this batch data of primary controller direct read with primary controller.If primary controller is the requirement reading of data, the normal running program can be after the primary controller reading of data be finished, and the data address that prediction primary controller next group may read is carried out the work of extracting in advance according to need.If primary controller is that requirement writes data, the operate as normal program then can notify the central controller data to be modified, with the coherent maintenance program of the data that start central controller.
(b) maintenance program:
Unsteady impact damper can be accepted in the access terminals of its stop, the instruction of access terminals controller, the data of the register that clears data, or the data of extraction storer, or the state (status) of the unsteady impact damper of change.The state of relocation register comprises whether the virtual address sign is effective, and whether the data in the data register were modified is waited the relevant existing working condition of impact damper of floating.Fig. 6 is the process flow diagram of maintenance program.All above-mentioned actions are finished by maintenance.After maintenance program changes the state of the impact damper that floats at the access terminals controller, can whether require to conform to by the new state of check with the primary controller access that may wait the back to carry out, just the address in the virtual address sign requires the address of access identical with primary controller, if then start the normal running program.
(c) major control program:
Central controller can be controlled the motion of each unsteady impact damper, and can set the virtual address and the converting form between actual address (Address Map-ping Table) of each unsteady impact damper.All primary controllers send the virtual address of access requirement, all need just can find actual address in storer through virtual address translation tables.Extracting rule is a prediction rule of making according to the primary controller access features in advance, is used for predicting the data that the primary controller next group may extract and estimates prediction accuracy.The mode of extracting rule formulation in advance, be to require primary controller to carry out all program or tasks commonly used in advance, all are noted the requirement of storage access with it simultaneously, then this batch record is given statistical study, look for the access requirement of primary controller, and then make the rule that prediction primary controller next group may extract data, and the accuracy of this rule.When unsteady impact damper is handled primary controller access requirement, can check the access record in primary controller past and existing access requirement, predict data and this prediction accuracy that the primary controller next group may extract, if prediction accuracy reaches certain upper limit (for example 70 percent accuracy), unsteady impact damper will extract this batch data in advance.Fig. 7 is the process flow diagram of major control program.When central controller requires unsteady impact damper to move, unsteady impact damper can be notified the access terminals at present place earlier, the data bus that breaks away from this access terminals moves to the access terminals of appointment then, and requires new virtual address translation tables of input and access rule in advance to central controller.Notify new access terminals to connect data bus at last and accept the management of its access terminals controller.Central controller also can be in the setting of the unsteady impact damper of change any time, to adapt to the transformation of master controller access features.
(2) unsteady buffer allocation program:
When primary controller proposes the access requirement, and required data are in any one unsteady impact damper of access terminals the time, and the access terminals controller must be carried out the buffer allocation program of floating, and accepts the access requirement of primary controller to determine that unsteady impact damper.The buffer allocation program of floating is the notice central controller earlier, starts the coherent maintenance program of central controller, with continuity and the correctness that guarantees this batch data.Central controller can check that all are positioned at the unsteady impact damper of other access terminals then, if there is any one unsteady impact damper to have this batch data, as long as program-controlled network has transitable path, central controller can unconditionally move to this unsteady impact damper in the present access terminals, accepts the access requirement of primary controller.If have this batch data without any unsteady impact damper, central controller can be according to the access record or the characteristic of each primary controller, determine whether and to move a unsteady impact damper to present access terminals from other access terminals, increase the number of its unsteady impact damper, to deal with the requirement of primary controller access.If the instruction that the buffer allocation program of floating is received central controller.Receive the unsteady impact damper of bringing in from other access, this program can be controlled the access terminals data bus, connects the new impact damper that floats, and starts the impact damper that should float then, accepts the access requirement of primary controller.Not so, the buffer allocation program of floating must be found out the unsteady impact damper that a primary controller is of little use, and removes its old data, to accept the access requirement of primary controller.Fig. 8 is the process flow diagram of the buffer allocation program of floating.
(3) the coherent maintenance program of data:
The topmost function of central controller is to safeguard the continuity of all data.The mode of safeguarding, then according to the characteristic of each primary controller, for example whether primary controller has exclusive cache memory, or whether primary controller allow the data total identical with other primary controllers etc., decides the criterion that links up and safeguard.Basically, central controller is divided three classes data: the one, only can read the data of (Ready Only), and the one, can shared read-write data, be can not be shared but the data do not read and not write at last.To these three kinds of data of different types, the principle of the coherent maintenance program control of data is:
(a) readable data:
Allow any primary controller to duplicate the copy of oneself, be positioned in the unsteady impact damper of exclusive cache memory or access terminals, but must not change this batch data.
(b) can shared read-write data:
Allow all primary controllers to duplicate the copy of oneself, but any primary controller attempt is when changing this batch data, must notifies every other primary controller to upgrade or abandon this batch data.
(c) can not be shared but read-write data:
When primary controller was asked for these class data as if requirement, whether the every other primary controller of inquiry have identical data earlier.If have, must wait for that then the primary controller that has this batch data is given back this batch data after, just can extract.
The coherent maintenance program of data can the maintained data of search request be to belong to that type at first, again according to the handling procedure of the type data, does suitable maintenance.Except above-mentioned three working routines, central controller is the operation control maincenter of program control interleave note pipe device.Central controller not only is responsible for carrying out the coherent maintenance program of data, central controller can be according to the access features of first primary controller to storer simultaneously, determine its access terminals should have the number of unsteady impact damper, and in good time change according to each primary controller access features, or the requirement that links up and safeguard, commander is unsteady, and impact damper moves in program-controlled network, does suitable adjustment.Also acceptable programme instruction of central controller, the characteristic of change work is for example closed certain paths in the program-controlled network, or the extracting rule in advance of a certain primary controller, make program control interleave note pipe device can answer the transformation of working environment, constantly adjust, to obtain preferable task performance.
From the above mentioned as can be known, the present invention's programmed regulating-controlled interlace memory administration system, it can finish the work of memory data access for a processor or bus master controller in the short time, and promotes the correctness of data.
Claims (3)
1. programmed regulating-controlled interlace memory administration system, comprise unsteady impact damper, access terminals, program-controlled network and central controller, it is characterized in that, the number of the unsteady impact damper that has with each access terminals of central controller controls, each unsteady impact damper moving between access terminals, and the switch in each path in the program-controlled network, and access terminals is constituted by several unsteady impact dampers, and access terminals also constitutes a program-controlled network mutually in succession.
2. programmed regulating-controlled interlace memory administration system as claimed in claim 1 is characterized in that, this unsteady impact damper comprises central controller interface, primary controller floating interface, memory interface, control sluice and data register.
3. programmed regulating-controlled interlace memory administration system as claimed in claim 1 is characterized in that, access terminals is constituted by several unsteady impact dampers.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95100337A CN1077700C (en) | 1995-02-17 | 1995-02-17 | Programmed regulating-controlled interlace memory administration system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95100337A CN1077700C (en) | 1995-02-17 | 1995-02-17 | Programmed regulating-controlled interlace memory administration system |
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| CN1129329A true CN1129329A (en) | 1996-08-21 |
| CN1077700C CN1077700C (en) | 2002-01-09 |
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| CN95100337A Expired - Fee Related CN1077700C (en) | 1995-02-17 | 1995-02-17 | Programmed regulating-controlled interlace memory administration system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1081360C (en) * | 1996-11-18 | 2002-03-20 | 日本电气株式会社 | Virtual channel memory system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0296862B1 (en) * | 1987-06-24 | 1995-05-10 | Westinghouse Electric Corporation | Multiprocessor information exchange |
| CN2037080U (en) * | 1988-07-26 | 1989-05-03 | 成都科技大学 | Communication Interface for Parallel Solution Optimization of Multi-Microprocessor System |
| US5293603A (en) * | 1991-06-04 | 1994-03-08 | Intel Corporation | Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1081360C (en) * | 1996-11-18 | 2002-03-20 | 日本电气株式会社 | Virtual channel memory system |
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