CN1128893C - corrosion equipment - Google Patents

Abstract

An etching apparatus has a substrate holding chamber before processing, a substrate transfer chamber, a substrate holding chamber after processing, and an etching chamber. In the etching chamber, a halogen fluoride gas such as ClF is used₃The etching of gas, for example, etching of an active layer of a thin film transistor, is performed without ionizing a halogen fluoride gas or plasma-strengthening. Since no plasma damage occurs, occurrence of trap levels in the active layer side surface is prevented, and movement of carriers through the trap levels is suppressed, thereby reducing the off-current value in the thin film transistor.

Description

corrosion equipment

The invention relates to an etching device for etching a silicon semiconductor, in particular to an etching device for forming an active layer of a thin film transistor (TFT) by etching.

Recently, attention has been paid to active matrix type liquid crystal display devices. In these devices, more than 100×100 pixel electrodes are arranged in a matrix form, and each pixel electrode is connected to a TFT having a silicon thin film, so that the charge held in each pixel is controlled by the TFT.

Because the liquid crystal display device must be substantially light-transmissive, a material that can transmit visible light must be used as a substrate. Materials transparent to visible light include quartz substrates and glass substrates. Because quartz substrates are expensive, glass substrates are generally used instead of quartz. However, it is difficult to produce TFTs with high performance on glass substrates.

In order to improve the characteristics of the TFT, the most effective way is to increase the crystallinity of the silicon thin film to be used. However, when a glass substrate is used, it is difficult to obtain a single crystal or a single crystal corresponding to a silicon thin film because of the temperature resistance of glass. In general, silicon films called polycrystalline or microcrystalline are available with an insufficiently crystalline state. When producing TFTs using silicon thin films with polycrystalline or microcrystalline structures, crucial technical issues relate to off-current characteristics.

In general, when a TFT is manufactured with a silicon thin film having a polycrystalline or microcrystalline structure, it is a fact that the value of the off-state current is large. The off current represents the current flowing between the source and drain regions when the TFT is in the off state.

In a TFT arranged in a pixel electrode, when the source of the TFT is connected to a source line and the drain of the TFT is connected to the pixel electrode, by the conduction of the TFT, a desired amount of charge flows from the source line through the TFT to the pixel electrode. prime electrode. In addition, by turning off the TFT, a desired amount of charge is held in the pixel electrode. At this time, when the off-current value is extremely large, charges gradually flow from the pixel electrodes. In this state, since a desired amount of charge is not held in the pixel electrode for a desired period of time, necessary display cannot be performed. Problems related to off-current may arise from the movement of carriers across grain boundaries.

In an N-channel TFT, when a positive voltage is applied to the gate electrode, the channel becomes N-type, thus completing a conduction operation. In addition, when a negative voltage is applied to the gate electrode, the channel becomes P-type, thus completing a turn-off operation.

In the cut-off operation, since the source and drain regions become N-type and the channel becomes P-type, an NPN structure is formed between the source and drain regions. Therefore, ideally, no current should flow between the source and drain regions. However, this state is an ideal state obtained when the silicon thin film constituting the active layer has a single crystal structure. In fact, since the silicon thin film does not have a complete single crystal structure, the carriers may move through the trap levels in the grain boundaries. Due to this carrier movement, there may be an off-current flow.

As described above, a silicon semiconductor thin film having crystallization formed on a glass substrate has a polycrystalline or microcrystalline structure in which a large number of grain boundaries exist. There are a large number of trap levels in the grain boundaries.

The movement of carriers through the trap levels is prominent in regions where high electric fields are applied. This movement is remarkable especially at and near the interface between the channel region and the drain region. Thus, as a method of suppressing the movement of carriers through the trap levels in this region, it is known to form a lightly doped region and an offset region (electric field buffer region) between the channel region and the drain region. ). Generally, these two structures are called LDD (Lightly Doped Drain) structure and offset gate structure respectively.

Actually, when a crystalline silicon thin film is formed on a glass substrate and then a TFT is fabricated using this silicon thin film, the LDD structure and the offset gate structure are effective so that off-current can be reduced to some extent. However, it has also been difficult to obtain the necessary low off-current characteristics.

Generally, a resist is patterned through a photolithography process to form a desired pattern, and then dry etching using plasma is performed using the resist as a mask to complete the formation of the active layer.

From the results of studies on the off-current problem in the above TFT, the present inventors obtained the following knowledge.

In etching the active layer by dry etching, plasma damage occurs on both sides of the active layer. Due to this plasma damage, a high density of trap levels can be formed on both sides of the active layer. In particular, this phenomenon is remarkable because a crystalline silicon film having a polycrystalline or microcrystalline structure is a state in which trap levels are generated at high density.

When a large number of trap levels generated by such plasmonic damage exist at high density on both sides of the active layer, the movement of carriers through the trap levels can be surprising. That is, the off-state current increases. Such problems are serious especially in films having a large number of grain boundaries, such as polycrystalline silicon films or microcrystalline silicon films. That is, because trap levels easily exist in grain boundaries and are easily generated.

The trap level density formed on the side of the active layer is much higher than that formed inside the active layer (inside the thin film). Then, although the LDD structure or the offset gate structure is formed, the amount of charges moving through the trap levels formed at the sides of the active layer cannot be reduced much. That is, the off-current value cannot be lowered much.

The LDD structure and the offset structure suppress the carrier movement that affects the cut-off current by reducing the electric field intensity in the electric field concentration area. Specifically, these structures reduce the number of mobile carriers. However, when the density of trap levels affecting carrier movement is extremely high, the total amount of moving carriers cannot be reduced so much even if the electric field is reduced.

Problems related to off-current are improved by reducing the trap level density at the sides of the active layer. From the above, it can be seen that the plasma damage in etching mainly produces trap levels concentrated on the side of the active layer. Thus, by reducing plasma damage of dry etching, problems related to TFT off-current can be improved.

As a method of preventing plasma damage to the side surface of the active layer, a method of performing wet etching on the formation of the active layer has been proposed. However, the method using wet etching has the following problems.

(1) There is no suitable etchant that can selectively etch only the silicon film with good etch control and good reproducibility.

(2) It is difficult to control the temperature and corrosion conditions of the etchant.

An object of the present invention disclosed in the specification is to provide an etching apparatus capable of performing a process using dry etching without concentrating trap levels on the side of an active layer.

According to the present invention, there is provided an etching method comprising the steps of: holding at least one pre-processed substrate in a pre-processed substrate holding chamber; transferring the substrate from the pre-processed substrate holding chamber to the etching chamber; etching the substrate with a fluorinated halogen gas maintained in a non-plasma state; transferring the etched substrate from the etch chamber to the processed substrate holding chamber; and maintaining the etched substrate in the processed substrate holding chamber, wherein , forming an active layer of a thin film transistor on the substrate through an etching process.

According to the present invention, there is also provided a semiconductor processing method comprising the steps of: placing a substrate having a material formed on the substrate in a reaction chamber; introducing an etching gas into the reaction chamber; materials without converting the corrosion gas into plasma; light is irradiated from a light source located outside the reaction chamber to the substrate; light passing through or reflected on the substrate is sensed with a sensor to detect the result of corrosion, wherein the corrosion process is performed on the substrate The active layer of a thin film transistor is formed on it.

The present invention disclosed in the specification is characterized in that the apparatus has a chamber for an etching process using a fluorinated halogen gas without ionizing or plasma enhancing the fluorinated halogen gas. The fluorinated halogen gas includes at least one of ClF ₃ , ClF, BrF ₃ , IF ₃ , BrF, BrF ₅ and IF ₅ . In addition, it is not necessary to use 100% fluorinated halogen gas, but it can be diluted with an appropriate gas before use. There is no ionization of the fluorinated halogen gas or a plasma enhanced etch process, reducing plasma damage during the etch process.

Another structure according to the invention is characterized in that the apparatus comprises a first chamber for carrying out etching, a second chamber for holding a plurality of substrates, and a substrate transfer chamber arranged between the first and second chambers. The device and the third chamber capable of reducing pressure, wherein the use of fluorinated halogen gas without ionizing or plasma-enhanced etching process of the fluorinated halogen gas is carried out in the first chamber.

An example of the above structure is shown in FIG. 1 . In FIG. 1, an apparatus includes: an etching chamber 800 corresponding to the first chamber; a substrate holding chamber 702 corresponding to a second chamber holding a large amount of substrates; A substrate transfer chamber 701 is provided with a robot arm 710 corresponding to a device for transferring substrates.

Another structure according to the invention is characterized in that the apparatus comprises a chamber having means for introducing a fluorinated halogen gas, wherein the etching process using the fluorinated halogen gas without ionizing or plasma-enhancing the fluorinated halogen gas is performed at carried out in this chamber, which also has means for measuring the transmission of light by the material to be etched and determining the state of corrosion of the material.

An example of the above structure is shown in FIG. 1 . In FIG. 1, an apparatus includes an etch chamber 800 having a gas introduction system 812 for introducing a fluorinated halogen gas, wherein an etch process using a non-ionizing or non-plasma-enhanced fluorinated halogen gas is performed in the etch chamber 800 , also includes a device 806 for irradiating light to transmit the material to be etched and a device 804 for detecting the transmitted light.

Another structure according to the present invention is characterized in that the apparatus comprises: an unprocessed substrate holding chamber, a first substrate transfer chamber connected to the pre-processed substrate holding chamber, an etching chamber connected to the first substrate transfer chamber chamber, a second substrate transfer chamber connected to the etching chamber, and a processed substrate holding chamber connected to the second substrate transfer chamber, wherein the substrate holding chamber before processing and the substrate holding chamber after processing have holding The function of a large number of substrates, the first and second transfer chambers have a device for transferring substrates, and the etching chamber has the function of using non-ionized or non-plasma-enhanced fluorinated halogen gas as an etching gas for etching.

An example of the above structure is shown in FIG. 1 . In FIG. 1 , the pre-processing substrate holding chamber 702, the first substrate transfer chamber 701, the etching chamber 800, the second substrate transfer chamber 820, the post-processing substrate holding chamber 830, and the substrate corresponding to the transfer substrate are shown. The robotic arms 710 and 821 of the device. FIG. 10 shows a top view of the etching apparatus of FIG. 1 .

When the active layer of the TFT is formed using the apparatus of FIG. 1, plasma enhancement (ionization) of the fluorinated halogen gas must be prevented so that plasma damage to the active layer does not occur. Plasma enhancement is prevented when the gas is not excited and ionized. In addition, ionization is prevented when no electromagnetic energy is applied. Electromagnetic energy includes high frequency energy and microwave energy.

When no electromagnetic energy is applied to the fluorinated halogen gas, plasma enhancement and excitation and ionization of the gas are prevented. Because fluorinated halogen gas such as _C1F3 has a strong corrosion effect on silicon, silicon can be etched at a high rate without applying electromagnetic energy such as high frequency energy.

In order to prevent rapid processing of corrosion, it is expected that the corrosion pressure is 0.001-100 Torr, preferably 0.01-1 Torr. A suitable corrosion rate can be obtained in this pressure range.

Another structure according to the present invention is characterized in that the apparatus comprises a first chamber for etching using a fluorinated halogen gas without ionization or plasma enhancement of the fluorinated halogen gas, a second chamber for removing the resist and a chamber connected to the first and second chambers and having means for transferring the substrate.

In the above structure, it is effective to perform etching and heating simultaneously. This is because heating increases the corrosion rate. In addition, it is effective to perform etching while maintaining a desired temperature. This is because the corrosion rate using _C1F3 as the corrosion gas in the corrosion is high, the difference in the corrosion temperature is small, and the corrosion state is also greatly changed.

Fig. 1 represents the sectional view of the corrosion equipment of embodiment 1;

2A～2D and FIG. 3A～3C show the process of making the thin film transistor (TFT) of embodiment 2;

Fig. 4 is a schematic enlarged view representing the state of the active layer;

Figures 5A-5D and Figures 6A and 6B show the process of manufacturing the TFTs arranged in the peripheral drive circuit area and the pixel area of Embodiment 3;

7A to 7G show the process of manufacturing the TFT disposed in the pixel area in embodiment 4;

8A and 8B show cross-sectional views of an etching apparatus of Embodiment 5;

Fig. 9 shows the sectional view of the corrosion equipment of embodiment 6;

FIG. 10 is a top view of the etching apparatus of FIG. 1 .

Implementation 1

FIG. 1 shows a sectional view of the etching apparatus of Embodiment 1, and FIG. 10 is a top view of the etching apparatus of FIG. 1. Referring to FIG. This etching equipment can process a large number of substrates (materials) one by one. A large number of substrates held in the cassette 712 held in the pre-processing substrate holding chamber 702 are processed by etching one by one in the etching chamber 800 . Processed substrates are held in cassettes 835 in processed substrate holding chamber 830 . Then, it is characterized in that a large number of substrates are processed by etching one after another. (Device Description)

A large amount of substrates (materials) to be processed are held in the substrate cassette 712 and brought into the pre-processing substrate holding chamber 702 from the outside. As for the substrate 711, a glass substrate and a quartz substrate are used, on which a silicon semiconductor layer to be etched is formed. In the chamber 702, a system for introducing nitrogen (or an inert gas) and an exhaust system (both not shown) are provided, and if necessary, it can be flushed with nitrogen. In particular, chamber 702 is not designed to achieve a reduced (low) pressure state.

A substrate cassette 712 holding a substrate 711 is set on a stage 754 moved by an elevator 753 in the up-down direction. The pre-processing substrate holding chamber 702 is connected to the substrate transfer chamber 701 having a robotic arm 710 through a gate valve 706 .

The substrate transfer chamber 701 has a gas introduction system 794 for introducing nitrogen or inert gas, and also has a high vacuum pumping system composed of a gate valve 790 and a high vacuum pump 791 . The flow of gas introduced from system 794 is controlled by valve 793 .

The substrate transfer chamber 701 is connected to the etching chamber 800 through a valve 801 . The etching chamber 800 is provided with a stage 803 (made of quartz) on which a substrate is placed, a laser light source 806, a reflection mirror 807, a quartz window 805 for introducing laser light into the chamber 800, and an optical detector for detecting the laser light.

The etching gas is introduced into the etching chamber 800 from the gas introduction system 812 through the valve 810 . Nitrogen or an inert gas is introduced from a gas introduction system 813 through a valve 811 . The chamber 800 is connected to a vacuum pump 809 through a valve 808 in order to evacuate unwanted gases and to obtain the desired low pressure in the etching chamber.

The etch chamber 800 is connected to the substrate transfer chamber 820 through a gate valve 814 . The substrate 822 on which the etching process has been completed is transferred from the chamber 800 to the chamber 820 by the robot arm 821 . In the chamber 820, a gas introduction system 827 for introducing nitrogen gas or an inert gas, and an exhaust system composed of a valve 825 and a vacuum exhaust pump 823 are provided. The flow of gas introduced from system 827 is controlled by valve 826 .

The substrate transfer chamber 820 is connected to the processed substrate holding chamber 830 through a gate valve 828 . In the chamber 830 , a substrate cassette 835 capable of holding a large amount of substrates (same as the substrate cassette 712 ) is provided on a stage moved vertically by an elevator 832 . (Example of operation process)

An example of an etching operation is now explained. All gate valves 706, 801, 814 and 828 are closed. Using the pumps 791, 809 and 823, the substrate transfer chambers 701, 820 and the etching chamber 800 are evacuated to obtain a high vacuum state. A substrate cassette 835 not holding a substrate is put into the pre-processing substrate holding chamber 830 . The chamber 830 is brought to a full state of nitrogen at one atmosphere.

In this state, a substrate cassette holding a desired number of substrates is brought into the pre-processing substrate holding chamber 702 from the outside. After loading the substrate cassette, the chamber 702 is filled with nitrogen at one atmosphere.

Then, nitrogen gas was introduced into the substrate transfer chamber 701 to reach an atmospheric pressure. When the chamber 701 becomes an atmospheric pressure state, the gate valve 706 is opened, and then a substrate 711 is taken out from the substrate cassette 712 by a robotic arm. At this time, the elevator moves up and down so that the robot arm is aligned with the position of the substrate 711 . After the substrate 711 is transferred to the chamber 701 with the robot arm 710, the gate valve 706 is closed.

Then, the substrate transfer chamber 701 is brought into a high vacuum state. When the chamber 701 becomes a high vacuum state, the gate valve 801 is opened, and the substrate is placed on the stage 803 . Then, the gate valve 801 is closed.

Next, CIF ₃ gas is introduced into the etching chamber 800, and the semiconductor thin film formed on the surface of the substrate is etched under the expected low pressure state. The state of corrosion can be verified from the state of transmission of laser light (having a short wavelength) irradiated from the light source 806 .

For example, in the case of a crystalline silicon thin film having a thickness of 500 nm, the transmittance of light having a wavelength of 500 nm is 50%, and in the case of a glass substrate or the stage 803 made of quartz, the transmittance is 80%. Thus, when the crystalline silicon film to be etched formed on the glass substrate is irradiated with light having a wavelength of 500 nm from the light source 806, after the etching of the crystalline silicon film is completed, the light intensity detected by the photodetector has a big change. Therefore, when the light intensity detected by the photodetector changes greatly, the introduction of the corrosion gas by the gas introduction system 812 is stopped, and at the same time, nitrogen gas is introduced from the gas introduction system 813, so that unnecessary corrosion (for example, in the lateral direction) can be prevented. delayed corrosion).

After the etching is completed, the etching chamber 800 is brought to a high vacuum state, the gate valve 814 is opened, and then the substrate 822 is taken out from the etching chamber 800 by a robot arm 821 . Then, the gate valve 814 is closed, and the substrate transfer chamber 820 is filled with nitrogen gas. When the chamber 820 becomes atmospheric pressure, the gate valve 828 is opened to hold the substrate 822 in the substrate cassette 835 . Then, after closing the gate valve 828, the chamber 820 is brought to a high vacuum state.

As a result, chambers 702 and 830 are filled with nitrogen to a state of one atmosphere, while chambers 701, 800, and 820 are still in a high vacuum state. Additionally, all valves 706, 801, 814 and 828 are closed. In this state, after the chamber 701 reaches an atmospheric pressure state again, the gate valve 706 is opened, and then the next substrate is taken out from the substrate box 712 by the mechanical arm 710 and sent into the chamber 701, so as to start the etching process of the next substrate, Repeat the above operation to etch the next substrate.

In this way, all the substrates held in the substrate cassette 712 are processed by etching one by one. This etching process can be carried out automatically under the control of a computer (not shown).

In the structure of FIG. 1, the state of corrosion is determined by measuring transmitted light using a short-wavelength laser. However, reflected light can also be measured. In this measurement, since the reflection state of light corresponding to a specific wavelength changes with the progress of etching of the silicon film, the completion of etching can be detected by observing changes in reflected light intensity and changes in interference fringes of reflected light. Embodiment 2

This embodiment represents a case where the present invention disclosed in the specification is suitable for a method of fabricating a thin film transistor (TFT) on a glass substrate. 2A to 2D show the fabrication process of the TFT in this embodiment.

A silicon oxide film 102 with a thickness of 3000 Å was formed as a base film on a glass substrate (Corning 1737 glass substrate or Corning 7059 glass substrate) 101 by plasma chemical vapor deposition (plasma CVD) or low-pressure thermal CVD. The film 102 serves to prevent the diffusion of impurities from the glass substrate 101, and to reduce stress between the glass substrate and an active layer subsequently formed thereon.

An amorphous silicon film 103 is formed on the silicon oxide film 102 to a thickness of 500 Å by plasma CVD or low-pressure thermal CVD. This film 103 is used as an original film constituting an active layer of a TFT formed in a subsequent process (FIG. 2A).

The formed amorphous silicon film 103 is crystallized by a desired method. As a method of crystallizing the film 103, there are known a heating method, a laser irradiation method, a heating combined with laser irradiation method, and the like. In this embodiment, a heated crystallization method is employed in which a metal element that promotes crystallization of silicon is used.

The crystallization method of this embodiment will be described below. Ni (nickel) is employed as a metal element that promotes crystallization of silicon. A nickel acetate solution containing a desired concentration of nickel element is applied to the surface of the amorphous silicon film 103 . The concentration of the nickel element contained in the nickel acetate solution is adjusted so that the concentration of the nickel element introduced into the amorphous silicon film 103 is set at about 1×10 ¹⁶ cm ^-3 to 5×10 ¹⁹ cm ^-3 . If a large amount of nickel is introduced, silicon becomes nickel silicide, and the characteristics as a semiconductor are damaged. In addition, if the amount of introduced nickel is too small, the effect of promoting crystallization cannot be achieved.

After coating the nickel acetate solution on the surface of the amorphous silicon film 103 to keep the nickel element in contact with the surface of the film 103, the crystallization of the film 103 is completed by heating at a temperature of 550° C. for 4 hours. In general, an amorphous silicon film can be crystallized even if the treatment is performed at about 550°C for several tens of hours or more. However, as described in the present embodiment, when nickel is used, crystallization can be achieved by heat treatment at a low temperature for a short period of time compared with the conventional process. In a conventional process, in order to crystallize an amorphous silicon film, heat treatment must be performed at 600° C. or higher for tens of hours.

In general, a crystalline silicon film obtained by heating an amorphous silicon film or irradiating it with laser light contains a high density of defects and has a high density of trap levels.

After the crystalline silicon film is obtained, it is patterned with the equipment shown in Figure 1 to form the active layer of the TFT. As shown in FIG. 2B, a mask 100 for forming an active layer is formed using a photoresist. Then, as shown in FIG. 2C, etching is performed using ClF ₃ gas to form the active layer 104 of the TFT. The etch can be performed at room temperature without plasma enhancement. Thus, plasma damage to the side surface of the active layer 104 can be almost completely prevented. The etching is carried out with the apparatus of FIG. 1 according to the process of the first embodiment.

Another feature of corroding CIF ₃ is that the resist is hardly damaged. When reactive ion etching (RIE) with plasma or wet etching is performed, since the damage to the resist is large, there are cases where the resist cannot be completely removed and a part of the resist remains. In the process of fabricating semiconductor devices, the remaining portion of the resist is not required. However, etching using ClF ₃ gas is convenient according to the present embodiment. It should be noted that etching using ClF ₃ gas is isotropic etching.

The etching conditions for forming the active layer 104 are as follows:

Corrosive gas: ClF ₃

Reaction pressure: 0.4Torr

Reaction temperature: room temperature

Corrosion rate: 500 Å/min

Mask : Photoresist

An example of etching at room temperature is now described. It is advantageous to heat the corrosive gas without ionizing it to improve the reaction rate.

After the etching is completed, the resist mask 100 is removed to obtain the structural state shown in FIG. 2D. After forming the active layer 104 in FIG. 2D, a gate insulating film 105 with a thickness of 1000 Å is formed by plasma CVD, as shown in FIG. 3A. A film mainly containing aluminum was formed by sputtering to a thickness of 6000 Å, and then the gate electrode 106 was formed by patterning. Next, using the gate electrode as an anode, anodic oxidation was performed in an electrolytic solution to form an anodized layer 107 with a thickness of 2000 Å (FIG. 3A).

After obtaining the structural state as shown in FIG. 3A , phosphorus (P) ions are implanted by plasma doping, and a source region 108 , a channel forming region 109 and a drain region 110 are formed in a self-aligned manner. At the same time, the offset region 111 is formed in a self-aligned manner because the anodized layer 107 surrounding the gate electrode 106 is used as a mask. Phosphorus ions are essentially intrinsic because they are not implanted into the offset region 111 . In addition, the offset region is not used as a channel, but is used as a buffer zone between the channel forming region 109 and the source and drain regions 108, 110 (FIG. 3B).

After the doping is completed, laser or intense light irradiation is performed to activate the source region 108 and the drain region 110 .

As shown in FIG. 3C, a silicon oxide film 112 is formed to a thickness of 7000 Å as an interlayer insulating film by plasma CVD. In addition, after the contact holes are formed, the source electrode 113 and the drain electrode 115 are formed using aluminum or other metals. Then, heat treatment is performed at 350° C. for 1 hour in a hydrogen-containing atmosphere to complete the TFT as shown in FIG. 3C .

FIG. 4 is a schematic diagram of the state of the active layer. In conventional dry etching with plasma (generally using RIE), since a high-density trap level is generated at the side surface 300 of the active layer by plasma damage, there is a path 302 along which carriers move. Carriers are transported along path 302 through the trap levels. Regardless of whether a channel is formed in the channel formation region 109, the path 302 always exists. Thus, although the offset region 111 is formed, when a voltage is applied between the source region 108 and the drain region 110, carriers move along the path 302. Due to this carrier movement, the off-state current increases.

In this embodiment, since the active layer is patterned by etching using ClF ₃ gas, damage to the active layer side surface 300 by ions can be prevented. The trap level density at the active layer side surface 300 due to plasma damage can thus be almost completely prevented. As a result, the number of carriers moving along path 302 may be reduced. In addition, the original carrier movement of the carriers moving along the path 301 is not suppressed, so the offset gate region 11 can be effectively used, and the characteristic of smaller off-current can be obtained. Embodiment 3

This embodiment shows a process for fabricating an active matrix type liquid crystal display device, particularly for simultaneously fabricating TFTs (pixel TFTs) formed in the active matrix region and for driving the periphery of the TFTs arranged in the active matrix region The process of driving the TFT of the circuit.

5A to 5D show the process of fabricating the TFT of this embodiment. A silicon oxide film 102 was formed as a base film on a glass substrate 101 to a thickness of 3000 Å by sputtering. A 500 Å thick amorphous silicon film was formed by plasma CVD or low-pressure thermal CVD, and then crystallized by heating or laser irradiation to obtain a crystalline silicon film 400 .

A resist mask 401 for forming the TFT active layer in the peripheral driver circuit and a resist mask 402 for forming the TFT active layer arranged in the active matrix region (pixel region) are formed (FIG. 5A) .

The active layers 403 and 404 are formed by etching using ClF ₃ using the apparatus of FIG. 1 . Corrosion conditions are as follows:

Corrosive gas: ClF ₃

Reaction pressure: 2Torr

Reaction temperature: room temperature

Corrosion rate: 1000 Å/min

Mask : Photoresist

The resist mask is removed after the etching is completed, whereby the structural state shown in FIG. 5B is obtained. In FIG. 5B, the active layer 403 is used for the TFTs constituting the peripheral driving circuit, and the active layer 404 is used for the TFTs arranged in the pixel area.

After the active layers 403 and 404 were formed, a film mainly containing aluminum was formed by electron beam evaporation to a thickness of 600 Å, and then patterned to form gate electrodes 405 and 406 . Then, using the gate electrodes 405 and 406 as anodes, anodization was performed in an electrolytic solution to form anodized layers 407 and 408 each having a thickness of 2000 Å. Using the anodized layers 407 and 408, an offset gate region can be formed by a subsequent impurity ion implantation process (FIG. 5C).

After the structural state of FIG. 5C is obtained, impurity ions for forming source and drain regions are implanted into the active layers 403 and 404 by ion implantation or plasma doping. To make N-channel TFTs, phosphorus ions are implanted by plasma doping.

By implanting phosphorus ions, source regions 409 and 413 and drain regions 412 and 416 can be formed in the active layers 403 and 404 according to self-alignment. In addition, regions where impurity ions are not implanted are defined as channel formation regions 411 and 415 and offset gate regions 410 and 414 (FIG. 5D).

After the implantation of impurity ions is completed, the region implanted with impurity ions is annealed by irradiating with laser or strong light. In this annealing process, the regions 409, 412, 413, and 416 that were amorphized by impurity ion implantation in the previous step are recrystallized, and the activation of the implanted impurities is completed at the same time (FIG. 6A).

After forming the regions 409, 412, 413 and 416, as shown in Fig. 6B, a silicon oxide film 501 is formed to a thickness of 6000 Å as an interlayer insulating film by plasma CVD. In addition, contact holes were formed, and then source electrodes 502 and drain electrodes 503 of TFTs arranged in the peripheral driver circuit region were formed with aluminum. At the same time, the source electrode 504 of the TFT arranged in the pixel area is formed.

A silicon oxide film 505 was formed to a thickness of 3000 Å by plasma CVD. After forming the contact hole, an indium tin oxide (ITO) electrode 506 constituting a pixel electrode is formed. The ITO electrode is directly connected to the drain electrode 416 of the TFT arranged in the pixel region (FIG. 6B).

Hydrogenation was performed at 350° C. for 1 hour in an atmosphere containing hydrogen to complete the structure shown in FIG. 6B . When the structure of this embodiment is formed, since the off current flowing along the side surface of the TFT active layer is greatly reduced, a great effect of reducing the off current due to the formation of the offset gate structure can be obtained. That is, a TFT with a small off-current can be obtained. Such a TFT with a small off-current is suitable as a TFT arranged in a pixel region in an active matrix type liquid crystal display device, as shown in FIG. 6B. Embodiment 4

This embodiment relates to a structure in which at least one TFT is provided for each pixel arranged in a matrix form in an active matrix type liquid crystal display device.

7A to 7G show the process of fabricating the TFT in this embodiment. In FIG. 7A, a silicon nitride film 602 is formed as an under film on a glass substrate by plasma CVD. In addition, a silicon oxide film 603 is formed by sputtering. An amorphous silicon film 604 is formed to a thickness of 500 Å by plasma CVD or low-pressure thermal CVD. A mask 605 made of a silicon oxide film is formed by a known photolithography process. Part of the amorphous silicon film 604 is exposed through the mask 605 .

A nickel acetate solution containing the desired concentration of nickel was applied by spin coating. Nickel element has a catalytic effect of promoting the crystallization of silicon. In this case, a nickel element layer or a layer 606 containing nickel element is formed (FIG. 7A).

Then heat treatment was performed at 550° C. for 4 hours. After this heat treatment, as shown in FIG. 7B , the crystal growth proceeds from the direct-introduced nickel element region 608 in the direction of the arrow 600 , thus forming the crystal growth region 607 . Regions 609 and 610 are the terminations of crystal growth. Crystal growth advances in needle or columnar directions parallel to the substrate. Regions 608 and 610 contain a high concentration of nickel.

The nickel concentration (maximum measurement concentration) of the crystal growth region 607 must be set at 1×10 ¹⁶ cm ⁻³ to 5×10 ¹⁹ cm ⁻³ . As such, the concentration of nickel element contained in the nickel acetate solution in the spin coating process of FIG. 7A is adjusted. The concentration of nickel is by definition the maximum measured value by a secondary ion mass spectrometer (SIMS).

With the present invention disclosed in the specification, a resist mask is formed by photolithography on the region where the active layer is to be formed, and then, the active layer 611 shown in FIG. 7C is formed by etching with ClF ₃ . The same detailed conditions as in Embodiment 1 or 2 can be set.

A silicon oxide film 612 is formed to a thickness of 1000 Å as a gate insulating film by plasma CVD. In addition, an aluminum film having a thickness of 6000 Å (including scandium) was formed by sputtering, and then etched using a photoresist mask 614. Although this step of the etching process has been completed. However, the resist mask 614 remains. Using the remaining photoresist mask 614, anodization was performed in an electrolytic solution using the remaining aluminum film as an anode to form a porous anodized layer 615 with a thickness of 5000 Å. The electrolyte contains 3-20% nitric acid (30°C). A voltage of 10 V was applied to the remaining aluminum in anodizing. After this process, the portion 613 where the aluminum is left is used as a gate electrode (FIG. 7C).

After removing the resist mask 614, use the gate electrode 613 as an anode, and carry out anodic oxidation in an ethylene glycol solution (pH=7) containing 1-3% tartaric acid to form a dense 2000 Å thick fine Anodized layer 616.

By dry etching of RIE, the exposed gate insulating film 612 is etched. In this process, the anodized layers 615 and 616 are hardly corroded due to the difference in corrosion rate. This etching continues until the active layer 611 is exposed. As shown in FIG. 7D, the gate insulating film 612' is left only at the lower portion of the gate electrode 613 and the anodized layers 615 and 616. As shown in FIG.

After obtaining the structural state shown in FIG. 7D, the porous anodized layer 615 is removed. Then, boron (B) ions were implanted into the active layer 611 at a low acceleration voltage of about 10 KV by plasma doping. Therefore, the introduction of boron ions is limited by the exposed portion 612 of the gate insulating film, so that boron ions are not implanted into the region 622 . Instead, boron ions are implanted into region 617 . As a result, the region 622 into which impurity ions are not implanted is defined as an offset region (FIG. 7E).

It was then heated at 500°C for 4 hours to activate the doped impurities. Furthermore, the annealing effect is improved by irradiating with KrF excimer laser. The interface between the regions 617 and 622 (where the PI junction is formed) is fully activated by laser light transmitted through the gate insulating film 612'. Since off-current is induced by trap levels in the interface between region 617 (corresponding to the source-drain region) and region 622 (corresponding to the offset region), activating or annealing this region is extremely effective in reducing the off-current.

A silicon oxide film 618 was formed to a thickness of 3000 Å as an interlayer insulating film by plasma CVD. After forming the contact hole, the source electrode 619 is formed using an aluminum film. In addition, a silicon nitride film 620 is formed to a thickness of 3000 Å as an interlayer insulating film. After the contact holes are formed, ITO electrodes 621 are formed as pixel electrodes. Thus, a P-channel type TFT having the offset region 622 can be obtained (FIGS. 7F and 7G).

When a crystalline silicon film is formed using a metal element that promotes crystallization of silicon, and then an active region is patterned, plasma damages the surface of the active region, thereby generating a trap level caused by the metal element. As described above, when the active layer was formed, plasma damage occurred on its side surface.

As described in this embodiment, when the active layer is formed by an etching method that does not cause plasma damage, although a metal element that promotes the crystallization of silicon is used in the formation of the crystalline silicon film constituting the active layer, in the active layer The trap level density of the side surface of the layer is not particularly high. Therefore, the movement of carriers through the side surface of the active layer can be suppressed, and a TFT with a small off-current can be obtained. In addition, since the movement of carriers through the side surface of the active layer can be suppressed, the formation of the offset region and the lightly doped region achieves a great effect. Embodiment 5

8A and 8B show an example of the etching apparatus disclosed in this specification. The etching equipment in FIGS. 8A and 8B includes: an etching chamber 902 , a substrate (material) transfer chamber 900 , a substrate holding chamber 903 before processing, and a substrate holding chamber 904 after processing. In the etching chamber 902, there is a stage 910 for placing the substrate (material) to be etched, and a heating and cooling mechanism for controlling the expected substrate temperature within an accuracy range of ±5°C.

The etching chamber 902 is connected to the substrate transfer chamber 900 through a gate valve 905 . In the chamber 900, a robot arm 908 for transferring a substrate 909 is provided. The chamber 900 is connected to a pre-processing substrate holding chamber 903 and a post-processing substrate holding chamber 904 through gate valves 906 and 907, respectively. In the chambers 903 and 904, substrate cassettes holding a large number of substrates are provided.

Fig. 8A is a top view of the device, and Fig. 8B shows a sectional view along A-A'. As shown in FIG. 8B , the high vacuum pumping systems 921 and 913 are connected to the etching chamber 902 and the substrate transfer chamber 900 through the vacuum pumping system valves 920 and 912 in the etching equipment, respectively.

The substrate transfer chamber 900 has a nitrogen or inert gas supply system 915 that can be purged if necessary. A nitrogen or inert gas supply system 918 and an etching gas (eg, ClF ₃ ) supply system 919 are connected to the etching chamber 902 through gas supply system valves 916 and 917 .

The substrate box 911 holding a large amount of substrates 909 is placed on the lift table 923, and then moves up and down by the lifter. This mechanism is used when the robot arm 908 is used to transfer the substrate 909 .

Not shown in the figure, a high vacuum evacuation system is provided in the chambers 903 and 904, and it is useful to perform high vacuum evacuation on these chambers. When this structure is used, the components of the etching gas from the etching chamber 902 can always be pumped out, so the etching accuracy can be improved and the stability of the process can be obtained. Embodiment 6

In FIG. 9, the etching equipment has a substrate holding chamber 1002 before processing, a substrate holding chamber 1006 after processing, chambers 1003-1005 including at least one etching chamber, a common substrate transfer chamber 1001, and a substrate holding chamber 1006. 1001 is a gate valve 1007-1001 connected to other chambers.

In the structural example of the etching apparatus of FIG. 9, the chamber 1003 can be used as an etching chamber using ClF ₃ , the chamber 1004 can be used as an ashing chamber for stripping the resist mask used in etching, and the chamber 1005 can be used as The chamber is irradiated with ultraviolet (UV) light to remove residual resist.

In the process of fabricating an insulated gate field effect transistor with a silicide gate, it is necessary to etch silicon after etching the silicide, and then etch the gate insulating film. In this case, the chamber 1003 can be used as an etching chamber using CIF ₃ , the chamber 1004 can be used as a chamber for etching a gate insulating film, and the chamber 1005 can be used as an ashing chamber for stripping a resist.

Alternatively, the chamber 1003 can be used as an etching chamber for etching silicide, the chamber 1004 can be used as a chamber for etching silicon, and the chamber 1005 can be used as an ashing chamber for stripping resist. In this case, the etching chambers 103 and 104 can be used as an etching chamber using CIF ₃ . Since the conditions for etching silicide are different from those for etching silicon, each chamber is used as an etching chamber in one condition to improve the efficiency of processing.

In the etching device of the present invention, since the etching without plasma damage is carried out in the formation of the active layer of the TFT, the occurrence of trap levels in the side surface of the active layer can be prevented, thereby suppressing the passage of carriers. Movement of trap levels in the side surface of the active layer. Therefore, a TFT with a small off-state current can be fabricated by means of the etching equipment of the present invention.

Claims (9)

1. A semiconductor processing method, comprising the following steps: maintaining at least one pre-processed substrate in the pre-processed substrate holding chamber; transferring the substrate from the pre-processing substrate holding chamber to the etch chamber; Etching the substrate with a fluorinated halogen gas maintained in a non-plasma state in the etch chamber; illuminating the substrate with light from a light source located outside the etching chamber; Sensing the light passing through or reflecting off the substrate with a sensor to detect the result of corrosion; transferring the etched substrate from the etch chamber to the processed substrate holding chamber; and maintaining the etched substrate in the processed substrate holding chamber, It is characterized by: Wherein, an active layer of a thin film transistor is formed on the substrate through an etching process. 2. The etching method according to claim 1, wherein said active layer comprises crystalline silicon. 3. A semiconductor processing method comprising the steps of: placing a substrate having a material formed on the substrate in the reaction chamber; introducing a corrosive gas into the reaction chamber; etching the material with the etching gas without converting the etching gas to a plasma; irradiating light to the substrate from a light source located outside the reaction chamber; It is characterized in that it also includes the following steps: Sensing the light passing through or reflecting from the substrate with a sensor to detect the result of corrosion, Wherein, an active layer of a thin film transistor is formed on the substrate through an etching process. 4. The semiconductor processing method according to claim 3, wherein said material comprises crystalline silicon. 5. The semiconductor processing method according to claim 3, wherein said etching gas includes halogen fluoride. 6. The semiconductor processing method according to claim 3, wherein said sensor and said light source are positioned such that said substrate is interposed therebetween. 7. The semiconductor processing method according to claim 6, wherein the substrate is supported on a quartz platform. 8. The semiconductor processing method according to claim 7, wherein said sensor is placed after said stage. 9. The semiconductor processing method according to claim 7, wherein said light source comprises a laser.

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