CN112836812A

CN112836812A - Neural Network Based on Floating Gate Transistor

Info

Publication number: CN112836812A
Application number: CN202011638469.XA
Authority: CN
Inventors: 王青; 陈静; 吕迎欢; 谢甜甜; 赵瑞勇
Original assignee: Shanghai Huali Microelectronics Corp; Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Huali Microelectronics Corp; Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-05-25
Anticipated expiration: 2040-12-31
Also published as: CN112836812B

Abstract

The present invention provides a floating gate transistor-based neuron network, including a multi-node input unit: the multi-node input unit includes a multi-input floating gate transistor, and a plurality of gate input terminals of the multi-input floating gate transistor are respectively Connect the input signals of multiple external bionic sensors, the source is grounded, and the drain is used as the output terminal of the neuron network. The invention provides a brand-new realization structure of electronic afferent neurons. This architecture is oriented to the application of hardware neuromorphic neural network, realizes the conversion of analog signal to neuron signal, has the advantages of simple structure, multiple functions, low power consumption, etc., and is more suitable for neuron network.

Description

Neural network based on floating gate transistor

Technical Field

The invention relates to the field of a neuron network, in particular to a neuron network based on a floating gate transistor.

Background

The neural network is an ideal choice for constructing a high-energy-efficiency storage and calculation integrated data processing center as a next-generation neural morphology calculation technology. To implement a perceptually computationally integrated intelligent processing system, an efficient perceptual information interface (known biologically as afferent nerves) needs to be constructed to establish real-time contact between the data processing center and the sensors. However, the electron afferent neurons constructed by adopting the CMOS in the prior art have the problems of high power consumption, complex circuit structure and process and the like, and are difficult to be applied to the novel neuromorphic neural network.

Disclosure of Invention

The invention aims to solve the technical problem of providing a floating gate transistor-based neuron network, solves the problems of high power consumption, complex circuit structure and process and the like, and is suitable for a novel neural morphological neural network.

In order to solve the above problems, the present invention provides a floating gate transistor-based neuron network, comprising a multi-node input unit: the multi-node input unit comprises a multi-input-end floating gate transistor, a plurality of grid input ends of the multi-input-end floating gate transistor are respectively connected with a plurality of external bionic sensor input signals, a source electrode is grounded, and a drain electrode is used as an output end of the neuron network.

The invention provides a brand-new electronic afferent neuron implementation framework. The architecture is applied to a hardware neural morphology neural network, realizes the conversion from analog signals to neuron signals, has the advantages of simple structure, multiple functions, low power consumption and the like, and is more suitable for the neuron network.

Drawings

Fig. 1 is a schematic structural diagram of a floating gate transistor-based neural network according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an architecture of an electron afferent neuron according to an embodiment of the present invention.

Fig. 3A and 3B are device structure diagrams of a floating gate transistor according to an embodiment of the present invention.

Detailed Description

The following describes in detail a specific embodiment of the floating gate transistor-based neuron network according to the present invention with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a floating-gate transistor-based neural network according to an embodiment of the present invention, which includes a multi-node input unit. The multi-node input unit comprises a multi-input-end floating gate transistor, and a plurality of grid input ends of the multi-input-end floating gate transistor are respectively connected with a plurality of external bionic sensor input signals V₀₁、V₀₂、……V_0NThe source electrode is grounded, and the drain electrode is used as the output end U of the neuron network_d(t)。

Input signal V of multi-node input unit to external bionic sensor₀₁～V_0NInformation integration is performed to obtain the floating gate voltage VF of the multi-input floating gate transistor, which is given by the combination of the following formula in combination with the structure shown in FIG. 1

Wherein V₀To V_NIs the floating gate voltage of each column of floating gate transistors, is a weighted average of the input voltage at each gate node, C₀₁～C_0NIs the parasitic capacitance between the floating gate and the gate oxide of the floating gate transistor of the first column, corresponding to C_N1～C_NNIs the parasitic capacitance between the floating gate and the gate oxide of the nth column of floating gate transistors. The weighted average is the floating gate voltage V of the floating gate transistor with multiple input ends_F，C₁～C_NIs the parasitic capacitance between the gate oxide and the top silicon of each column of floating gate transistors.

When the floating gate voltage V of the multi-input floating gate transistor_FLess than threshold voltage V_TWhen the multi-input end floating gate transistor is not conducted; when the floating gate voltage V_FTo the threshold voltage V of a multi-input floating gate transistor_TAt this time, the multi-input floating gate transistor begins to conduct. After the multi-input end floating gate transistor is conducted, the drain voltage is correspondingly increased, and therefore the information integration function of signals is achieved.

Based on the above principle, the present embodiment provides a novel architecture for implementing the electron afferent neuron, which is shown in fig. 2. The architecture is applied to a hardware neural morphology neural network, realizes the conversion from analog signals to neuron signals, has the advantages of simple structure, multiple functions, low power consumption and the like, and is more suitable for the neuron network.

In one embodiment, the multi-node input unit is a multi-input floating gate transistor with a substrate made of a fully depleted SOI material of a 22nm process node, and the device structure of the multi-input floating gate transistor is as shown in fig. 3A and fig. 3B. The transistor comprises a substrate (Subtrate), Buried Oxide (Buried Oxide) on the surface of the substrate and top silicon on the surface of the Buried Oxide, wherein the top silicon forms a Source (Source), a Drain (Drain) and a conductive channel formed by adopting a Thin film silicon (Thin Si-body) material between the Source and the Drain through doping. The surface of the conductive channel is provided with a Gate (Gate) and a Floating Gate (Floating Gate) on the surface of the Gate. The method has the advantages that the characteristics of the fully depleted SOI material can be utilized, the source, the drain and the conducting channel are directly formed on the top layer silicon through doping, the series connection between the transistors is directly formed, and the conducting isolation well does not need to be additionally manufactured, so the method is a low-cost and high-efficiency selection mode.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A floating gate transistor-based neuron network, comprising a multi-node input unit: the multi-node input unit comprises a multi-input-end floating gate transistor, a plurality of grid input ends of the multi-input-end floating gate transistor are respectively connected with a plurality of external bionic sensor input signals, a source electrode is grounded, and a drain electrode is used as an output end of the neuron network.

2. The floating-gate transistor-based neuron network of claim 1, wherein the multi-node input cell multi-input floating-gate transistor is a fully depleted SOI material-based multi-input floating-gate transistor.

3. The floating gate transistor-based pulse neuron network of claim 2, wherein the transistor comprises a substrate, a buried oxide on the surface of the substrate, and a top silicon on the surface of the buried oxide, wherein the top silicon forms a source, a drain, and a conductive channel between the source and the drain formed by a thin film silicon material by doping; the surface of the conductive channel is provided with a grid and a floating grid on the surface of the grid.

4. The floating-gate transistor-based spiking neuron network according to claim 2, wherein the fully depleted SOI material is applied as a 22nm node process for a multi-input floating-gate transistor on a substrate.