CN112818629A - Design rule of planar transistor and planar transistor - Google Patents

Abstract

The invention relates to a design rule of a planar transistor and the planar transistor, comprising: evaluating the key design criteria by using a priority method and dividing the key design criteria into 4 levels; the first level of prioritization of the design criteria is: a new rule; the second level of prioritization of the design criteria is: regional key rules; the third level of prioritization of the design criteria is: designing a key rule; the fourth level of prioritization of the design criteria is: yield key rules; the first level has the highest priority and the fourth level has the lowest priority; the design criteria and design architecture of the planar transistor are optimized using a priority approach to evaluate the design criteria and the innovative design layout of the design criteria design.

Description

Design Criteria for Planar Transistors and Planar Transistors

technical field

The present application relates to the technical field of design and manufacture of planar transistors, and in particular, to a design criterion for planar transistors and planar transistors.

Background technique

Over the past few decades of technological development, the size of planar transistors has continued to shrink, while performance has increased significantly and power consumption has been greatly reduced. Thanks to the advancement of planar transistor technology, electronic products have also become better, able to do more useful, more important and more valuable things in a faster, simpler and more efficient way. In 1999, Professor Hu Zhengming's research group aimed to expand CMOS technology to 25nm and below. Because when the gate length approaches the 20nm mark, the ability to control the current drops sharply, and the leakage rate increases accordingly. In the traditional planar MOSFET structure, it is no longer applicable. By 2010, Bulk CMOS (bulk silicon) process technology will come to an end at 20nm.

Professor Hu proposed two solutions: one is a three-dimensional structure of FinFET transistors (fin transistors, released in 1999), and the other is SOI-based ultra-thin silicon-on-insulator technology (UTB-SOI, which is FD-SOI Transistor Technology, released in 2000). The invention of FinFET and FD-SOI processes has enabled the 10nm/14nm/16nm Moore's Law to continue its legend today.

Numerous early electrical simulation results show that reducing both the BOX thickness of the FD-SOI substrate and the top silicon thickness can reduce the transistor's leakage-induced barrier lowering (DIBL). FD-SOI planar transistors continue to shrink down to below 14 nanometers, resulting in increasingly complex planar transistor designs. At present, how to provide a flexible design structure while reducing the area of planar transistors, improve the energy efficiency of planar transistors and reduce power consumption is an urgent problem to be solved.

SUMMARY OF THE INVENTION

Based on this, there are currently no design guidelines and design architectures for FD-SOI planar transistors below 14 nm.

In order to achieve the above object, the present invention provides a design criterion for a planar transistor, including: the design criterion divides the design rules into multiple levels by using a priority method, and prioritizes the multiple levels; wherein,

The first level after the priority sorting is: checking whether the design rule is a new rule;

The second level after the priority ordering is: regional key rules, checking whether the design rules design the size of the chip;

The third level after the priority ordering is: checking whether the design rule is related to the functional output of the prepared planar transistor;

The last fourth level of the priority ordering is: checking whether the design rule is related to the parameter yield of the prepared planar transistor;

Wherein, among the multiple levels, the priorities are sequentially decreased from the first level to the fourth level;

The design criteria are divided using a prioritization method, and the planar transistors are designed based on the prioritized design rules of the plurality of levels.

According to the design criteria for planar transistors provided by the embodiments of the present invention, in the first level of priority sorting, the new rules are defined as new layer rules that need to be described in design technical standards or new recommended rules for design and manufacturing Or a conditional rule that is divided into sub-rules.

According to the design criteria for planar transistors provided by the embodiments of the present invention, in the second level of priority sorting, checking whether the size of the chip is designed by the design rule includes checking whether the size of the chip is designed to be reduced by the design rule Amplitude.

According to the design criteria for planar transistors provided by the embodiments of the present invention, in the third level of the priority ordering, the functional output includes a functional yield, and the functional yield of the functional output is used to evaluate the functional yield. Functional defects caused by design guidelines.

According to the design criteria of the planar transistor provided by the embodiment of the present invention, in the fourth level of the priority ordering, the performance problem caused by the design criteria is evaluated by the parameter yield.

According to the design criteria for planar transistors provided by the embodiments of the present invention, among the multiple levels, the design rules of at least one of the levels are non-critical rules, the design rules of all levels are critical rules, or the design rules of all levels are all for non-critical rules.

According to the design criteria for planar transistors provided by the embodiments of the present invention, the divided design rules of the multiple levels are evaluated, the evaluation results are divided into multiple groups, and the multiple groups are divided into multiple risk levels.

According to the design criteria for planar transistors provided by the embodiment of the present invention, in the evaluation result, the highest risk level is: among the first level, the second level, the third level, and the fourth level The design rules of the first level, the second level, the third level and the fourth level are all non-critical rules with the lowest risk level.

According to the design criterion for a planar transistor provided by the embodiment of the present invention, in the evaluation result, the risk factor priority of the design rule in the first level is greater than the risk factor priority of the design rule in the second level, The risk factor priority of the design rules in the second level is greater than the risk factor priority of the design rules in the third level, and the risk factor priority of the design rules in the third level is higher than the fourth level The risk factor priority of the design rules in .

The present invention also provides a planar transistor using the design criteria of the planar transistor described in any one of the above embodiments.

The beneficial effects of the present invention are as follows: a design criterion for a planar transistor and a planar transistor provided by the present embodiment, by designing a design criterion for a planar transistor, the design criterion for a planar transistor is evaluated and divided into multiple parts by using a priority method. The design criteria of the planar transistor are sorted by risk factor through multiple criteria levels with different priorities. For the design criteria for planar transistors provided in this embodiment, only a few design rules need to be found, which can cover larger rule risks, and can greatly reduce the development cost and development time of the design rules. The design criteria for planar transistors provided in this embodiment use an innovative design criteria priority method and an innovative design layout to optimize the planar transistor design criteria and design architecture.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the traditional technology, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the traditional technology. Obviously, the drawings in the following description are only the For some embodiments of the application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is an evaluation diagram of a design criterion of a planar transistor provided by the present embodiment;

Figure 2 is a graph of the study of risk coverage and number of design criteria.

Detailed ways

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the related drawings. Embodiments of the present application are presented in the accompanying drawings. However, the application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are for the purpose of describing specific embodiments only, and are not intended to limit the application.

Fully depleted silicon-on-insulator (FD-SOI) is a planar process technology that relies on two major technological innovations. First, an ultra-thin insulating layer, also known as a buried oxide layer, is fabricated on the substrate. A very thin silicon film is used to make the transistor channel. Because the channel is very thin, there is no need to perform a doping process on the channel, and the depletion layer fills the entire channel region, that is, a fully depleted transistor. These two innovative technologies are collectively called "ultra-thin bulk silicon and buried oxide fully depleted silicon-on-insulator", or UTBB-FD-SOI for short. Structurally, the electrostatic properties of FD-SOI transistors are superior to those of conventional bulk silicon technology. The buried oxide layer can reduce the parasitic capacitance between the source and the drain, and can effectively suppress the flow of electrons from the source to the drain, thereby greatly reducing the leakage current that causes performance degradation. In addition, FD-SOI has many other unique advantages, including back-biasing capability, excellent transistor matching characteristics, low supply voltage close to threshold, ultra-low susceptibility to radiation, and very high The intrinsic working speed of the transistor, etc., these advantages make it work in the application of the millimeter wave band. Due to the limitations of advanced lithography and process technology, the current design criteria and layout design methods of planar FD-SOI transistors below 14 nm have become more complex.

This embodiment provides a design criterion for a planar transistor, including: the design criterion divides the design rules into multiple levels by using a priority method, and prioritizes the multiple levels; wherein, the prioritization After the first level is: new rules, check whether the design rules are new rules; the second level after the priority ordering is: regional key rules, check whether the design rules design the size of the chip; the The third level after prioritization is: design key rules, checking whether the design rules are related to the functional output of the prepared planar transistors; the fourth level after the prioritization is: yield key rules, checking all whether the design criterion is related to the parameter yield of the prepared planar transistor; wherein, among the multiple levels, the priorities are sequentially decreased from the first level to the fourth level; the priority method is used to divide the the design criteria, the planar transistors are designed based on the design rules of the multiple levels after the priority ordering, and the design criteria and design architecture of the planar transistors are optimized.

The priority method is a recursive construction method. In the construction of recursion theory, the following problems often arise: at a certain point in the construction process, there may be multiple requirements that have the opportunity to be satisfied at the same time, and even some requirements have been temporarily satisfied, but if a certain requirement is to be satisfied, Other needs cannot be met, or needs that have been temporarily met are impaired. This is where a decision needs to be made which needs to be prioritized. The so-called priority method is to assign priorities to all requirements. When there is a conflict between multiple requirements, the requirements with the highest priority are given priority. Prioritized approaches often produce impairments, ie, the satisfaction of high-priority needs undermines established satisfaction of lower-priority needs, but not all prioritization approaches are necessarily impairments.

As shown in FIG. 1 , an evaluation diagram of a design criterion of a planar transistor provided in this embodiment is shown. The planar transistor design criteria provided in this embodiment are divided into four levels according to the priority method, wherein the first level is a new rule; the first level of prioritizing the design rules is to check whether the design rules are new rules. The new rules are defined as new layer rules that need to be described in design technical standards (especially a completely new technology) or new recommended rules for design and manufacture or more complex conditional rules divided into several sub-rules. Of these, most rules can be discovered and scaled down from previous techniques; however, new rules are generated for new layers of new processes. During early process development, planar transistor fabs had no concept or experience with this new rule because they had never run the new process. Nor do they know what the potential risks or weaknesses of the rule are. The second level is regional key rules; the second level of prioritizing the design rules is to check whether the design rules design the size of the chip, including checking whether the design rules design the size of the chip can be reduced magnitude. This is called the critical area, and a key purpose of designing a new design criterion is to examine how much the size of the fabricated chips can be reduced by the production technology developed based on the design criterion. For example, multi-pitch is a key design rule that defines the chip size of a front end of line (FEOL) planar transistor, which covers and designs a single device, including transistors, resistors, and capacitors. The spacing between the metal lines is a key design rule in the backend of line (BEOL) process, and the metal line spacing rules design the interconnection between the metal lines and the device. In the subsequent process, several layers of conductive metal lines need to be established, and the metal lines of different layers are connected by columnar metal. The third level hierarchy is the design key rules; the third level of prioritizing the design rules is to check whether the design rules are related to the functional yield of the fabricated planar transistors. The functional output includes the functional yield, and the functional yield of the functional output is used to evaluate the functional defects caused by the design criteria. The functional yield of the functional output is used to evaluate the functional yield of the design criteria. An important indicator of functional defects caused by planar transistors. The fourth level hierarchy is yield critical rules; the fourth level of prioritization of the design rules is to check whether the design rules are related to the parametric yield of the planar transistors produced. Parametric yield is an important metric for evaluating performance issues caused by the design criteria.

Among the multiple levels provided in this embodiment, the design rules of at least one of the levels are non-critical rules, the design rules of all levels are critical rules, or the design rules of all levels are non-critical rules; After evaluating the design rules of the multiple levels, the evaluation results are divided into multiple groups, and the multiple groups are divided into multiple risk levels; in the evaluation results, the highest risk level is: the first The design rules in the level, the second level, the third level and the fourth level are all key rules; the lowest risk level is: the first level, the second level, the third level Levels and the design rules in the fourth level are non-critical rules.

Specifically, as shown in FIG. 1 , the design criteria for planar transistors provided in this embodiment are divided into four levels through a priority method evaluation, including the new rules, the regional key rules, the design key rules, and the Production key rules, wherein, among the new rules, the regional key rules, the design key rules, and the production key rules, at least one of the design rules of the level is a non-critical rule, and the design rules of all levels are Critical rules or design rules at all levels are non-critical rules. According to the four-level evaluation of the design criteria and two categories including critical rules and non-critical rules in each level, in this embodiment, the key rule in the design criteria is denoted as 1, and the design The non-critical rules in the guidelines are recorded as 0 and can be divided into 16 groups. Of the 16 groups evaluated in the four-level rating of the design criteria, some groups had different risk levels, and some groups had the same risk level. The 16 groups include:

The first group: the new rules are non-critical rules (0), the regional key rules are non-critical rules (0), the design key rules are non-critical rules (0), and the production key rules are non-critical Rule (0), that is, (0000) in the four-level evaluation of the first group; the risk level coefficient of the first group is 1;

The second group: the new rules are non-critical rules (0), the regional key rules are non-critical rules (0), the design key rules are non-critical rules (0), and the production key rules are critical rules (1), that is, (0001) in the four-level evaluation of the second group; the risk level coefficient of the second group is 2;

The third group: the new rules are non-critical rules (0), the regional key rules are non-critical rules (0), the design key rules are critical rules (1), and the production key rules are non-critical rules (0), that is, (0010) in the four-level evaluation of the third group; the risk level coefficient of the third group is 2;

The fourth group: the new rule is a non-critical rule (0), the regional key rule is a non-critical rule (0), the design key rule is a key rule (1), and the output key rule is a key rule ( 1), that is, (0011) in the four-level evaluation of the fourth group; the risk level coefficient of the fourth group is 3;

The fifth group: the new rule is a non-critical rule (0), the regional key rule is a key rule (1), the design key rule is a non-critical rule (0), and the production key rule is a non-critical rule (0), that is, (0100) in the four-level evaluation of the fifth group; the risk level coefficient of the fifth group is 4;

The sixth group: the new rules are non-critical rules (0), the regional key rules are key rules (1), the design key rules are non-critical rules (0), and the production key rules are key rules ( 1), that is, (0101) in the four-level evaluation of the sixth group; the risk level coefficient of the sixth group is 5;

Seventh group: the new rule is a non-critical rule (0), the regional key rule is a key rule (1), the design key rule is a key rule (1), and the yield key rule is a non-critical rule ( 0), that is, (0110) in the fourth-level evaluation of the seventh group; the risk level coefficient of the seventh group is 5;

Eighth group: the new rules are non-critical rules (0), the regional key rules are key rules (1), the design key rules are key rules (1), and the yield key rules are key rules (1) ), that is, (0111) in the four-level evaluation of the eighth group; the risk level coefficient of the eighth group is 6;

Ninth group: the new rules are key rules (1), the regional key rules are non-critical rules (0), the design key rules are non-critical rules (0), and the production key rules are non-critical rules (0), that is, (1000) in the fourth-level evaluation of the ninth group; the risk level coefficient of the ninth group is 7;

Tenth group: the new rules are key rules (1), the regional key rules are non-critical rules (0), the design key rules are non-critical rules (0), and the production key rules are key rules ( 1), that is, (1001) in the four-level evaluation of the tenth group; the risk level coefficient of the tenth group is 8;

The eleventh group: the new rules are key rules (1), the regional key rules are non-critical rules (0), the design key rules are key rules (1), and the yield key rules are non-critical rules (0), that is, (1010) in the four-level evaluation of the eleventh group; the risk level coefficient of the eleventh group is 8;

The twelfth group: the new rules are key rules (1), the regional key rules are non-critical rules (0), the design key rules are key rules (1), and the yield key rules are key rules ( 1), that is, (1011) in the four-level evaluation of the twelfth group; the risk level coefficient of the twelfth group is 9;

Thirteenth group: the new rules are key rules (1), the regional key rules are key rules (1), the design key rules are non-critical rules (0), and the yield key rules are non-critical rules (0), that is, (1100) in the four-level evaluation of the thirteenth group; the risk level coefficient of the thirteenth group is 10;

Group 14: The new rules are key rules (1), the regional key rules are key rules (1), the design key rules are non-critical rules (0), and the yield key rules are key rules ( 1), that is, (1101) in the four-level evaluation of the fourteenth group; the risk level coefficient of the fourteenth group is 11;

Group 15: The new rules are key rules (1), the regional key rules are key rules (1), the design key rules are key rules (1), and the yield key rules are non-critical rules ( 0), that is, (1110) in the four-level evaluation of the fifteenth group; the risk level coefficient of the fifteenth group is 11;

Sixteenth group: the new rules are key rules (1), the regional key rules are key rules (1), the design key rules are key rules (1), and the yield key rules are key rules (1) ), that is, (1111) in the four-level evaluation of the sixteenth group; the risk level coefficient of the sixteenth group is 12.

Wherein, in the 16 groups in the four-level evaluation of the design criteria, in the evaluation result, the priority of the risk factor of the design rule in the first level is higher than the risk of the design rule in the second level coefficient priority, the risk coefficient priority of the design rules in the second level is greater than the risk coefficient priority of the design rules in the third level, and the risk coefficient priority of the design rules in the third level is greater than the risk coefficient priority of the design rules in the third level The risk factor priority of the design rules in the fourth level described above. Among the 16 groups in the four-level evaluation of the design criteria provided in this embodiment, the sixteenth group has the highest risk level coefficient, that is, the new rule is the key rule (1), and the regional key rule is the key Rule (1), the key design rule is the key rule (1), and the key production rule is the key rule (1); the lowest risk level coefficient is the first group, that is, the new rule is the non-critical rule (0 ), the regional key rule is a non-critical rule (0), the design key rule is a non-critical rule (0), and the output key rule is a non-critical rule (0);

Among the 16 groups in the four-level evaluation of the design criteria provided in this embodiment, the risk level coefficients of the second group (0001) and the third group (0010) are the same, both being 2; The risk level coefficients of the sixth group (0101) and the seventh group (0110) are the same, both are 5; the risk level coefficients of the tenth group (1001) and the eleventh group (1010) are the same, both are 8; the fourteenth group (1101) and the fifteenth group (1110) have the same risk level coefficients, both being 11. In the four-level evaluation of the design criteria provided in this embodiment, if only one of the key design rules and the key production rules is satisfied, then the key design rules and the key production rules The degree of risk level impact on the design criteria is the same.

As shown in Figure 2, it is the research graph of the risk coverage ratio and the number of design criteria. It can be seen from FIG. 2 that the number of design criteria is proportional to the risk coverage ratio, and the greater the number of the design criteria, the higher the corresponding risk coverage ratio. And the risk coverage rate increases with the increase of the number of the design criteria, and the risk coefficient increases logarithmically. For the design criteria for planar transistors provided in this embodiment, it is only necessary to find a few design criteria to cover larger rule risks. The design criteria for planar transistors provided in this embodiment can greatly reduce the development of design criteria. cost and development time.

This embodiment also provides a planar transistor, and the planar transistor is designed and manufactured according to the design criteria for planar transistors provided by this embodiment. The related structure of the planar transistor will not be repeated here.

The present embodiment provides a design criterion for a planar transistor and a planar transistor. By designing a design criterion for a planar transistor, a priority method is used to evaluate and divide the design criterion for a planar transistor into multiple levels. The design criteria of the planar transistors are sorted by risk coefficients at different levels of criteria. For the design criteria for planar transistors provided in this embodiment, only a few design rules need to be found, which can cover larger rule risks, and can greatly reduce the development cost and development time of the design rules. The design criteria for planar transistors provided in this embodiment use an innovative design criteria priority method and an innovative design layout to optimize the planar transistor design criteria and design architecture.

In the description of this specification, reference to the description of the terms "some embodiments," "other embodiments," "ideal embodiments," etc. means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in the present specification. at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features of the above-described embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, it should be It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (10)

1. A design criterion for a planar transistor, comprising: the design criterion uses a priority method to divide design rules into multiple levels, and prioritizes the multiple levels; wherein, The first level after the priority sorting is: checking whether the design rule is a new rule; The second level after the priority ordering is: checking whether the design rule designs the size of the chip; The third level after the priority ordering is: checking whether the design rule is related to the functional output of the prepared planar transistor; The fourth level after the priority ordering is: checking whether the design rule is related to the parameter yield of the prepared planar transistor; Wherein, among the multiple levels, the priorities are sequentially decreased from the first level to the fourth level; The design criteria are divided using a prioritization method, and the planar transistors are designed based on the prioritized design rules of the plurality of levels. 2 . The design criterion for planar transistors according to claim 1 , wherein, in the first level of the prioritization, the new rule is defined as a new layer rule or design that needs to be described in a design technical standard. 3 . Created new recommended rules or conditional rules divided into sub-rules. 3 . The design criterion for planar transistors according to claim 2 , wherein, in the second level of the priority ordering, checking whether the design rule designs the size of the chip comprises checking whether the design rule designs the size of the chip. 4 . The size of the chip can be reduced. 4 . The design criterion for a planar transistor according to claim 3 , wherein, in the third level of the priority ordering, the functional output includes a functional yield, and the functional finished product produced by the function. 5 . rate to evaluate functional defects caused by the design criteria. 5 . The design criterion of the planar transistor according to claim 4 , wherein in the fourth level of the priority ordering, the performance problem caused by the design criterion is evaluated by the parameter yield. 6 . 6 . The design criterion for planar transistors according to claim 1 , wherein, among the multiple levels, at least one of the design rules of the level is a non-critical rule, all levels of the design rules are critical rules or all The design rules at the level are all non-critical rules. 7. The design criterion for a planar transistor according to claim 6, wherein the divided design rules of the multiple levels are evaluated, the evaluation results are divided into multiple groups, and the multiple groups are divided into Multiple risk levels. 8 . The design criterion for a planar transistor according to claim 7 , wherein among the evaluation results, the highest risk level is: the first level, the second level, the third level and the The design rules in the fourth level are all critical rules; the lowest risk level is: the design rules in the first level, the second level, the third level and the fourth level are all non-critical rule. 9 . The design criterion for a planar transistor according to claim 8 , wherein, in the evaluation result, a risk factor priority of the design rule in the first level is higher than that of the design rule in the second level. 10 . Risk factor priority, the risk factor priority of the design rules in the second level is greater than the risk factor priority of the design rules in the third level, and the risk factor priority of the design rules in the third level is greater than The risk factor priority of the design rules in the fourth level. 10. A planar transistor, characterized in that, the planar transistor adopts the design criteria of the planar transistor according to any one of claims 1-9.

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