CN112818354A - Architecture and method for implementing SOC card measurement double BIOS - Google Patents
Architecture and method for implementing SOC card measurement double BIOS Download PDFInfo
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- CN112818354A CN112818354A CN202110223396.6A CN202110223396A CN112818354A CN 112818354 A CN112818354 A CN 112818354A CN 202110223396 A CN202110223396 A CN 202110223396A CN 112818354 A CN112818354 A CN 112818354A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention particularly relates to an implementation framework and a method for measuring double BIOS by an SOC card. The SOC card measurement dual BIOS realization architecture and method comprises an SOC card and a CPLD chip, wherein the SOC card and the CPLD chip are both connected with an electronic switch 1, and the CPLD chip is also connected with an electronic switch 2 and an electronic switch 3; the dual-way CPU is respectively connected to the BIOS through an electronic switch 2 and an electronic switch 3, and the electronic switch 1 is respectively connected to the BIOS1 and the BIOS2 through the electronic switch 2 and the electronic switch 3. The realization framework and the realization method of the SOC card measurement double BIOS can realize double BIOS measurement, prevent the BIOS information from being falsified and ensure the normal starting of the double-channel CPU computer.
Description
Technical Field
The invention relates to the technical field of data security, in particular to an implementation architecture and a method for measuring double BIOS by an SOC card.
Background
With the rise and development of the information industry, data security becomes the focus of people's attention. To some extent, data security is the core of computer security.
Previously, the SOC card could not connect 2 BIOS's over one SPI path, selecting which BIOS to measure. So only one BIOS can be accessed, measuring 1 BIOS. However, on a two-way CPU computer, both BIOS's are at risk of tampering, requiring measurement prior to power-up.
However, in the current technical solution, the SOC card can only measure 1 BIOS, and cannot switch to read the BIOS channel on one channel. Based on the situation, the invention provides an implementation framework and a method for measuring double BIOS by an SOC card.
Disclosure of Invention
In order to make up for the defects of the prior art, the invention provides a simple and efficient SOC card measurement dual BIOS implementation framework and method.
The invention is realized by the following technical scheme:
an implementation architecture of dual BIOS for SOC card measurement is characterized in that: the system comprises an SOC card and a CPLD chip, wherein the SOC card and the CPLD chip are both connected with an electronic switch 1, and the CPLD chip is also connected with an electronic switch 2 and an electronic switch 3; the dual-way CPU is respectively connected to the BIOS through an electronic switch 2 and an electronic switch 3, and the electronic switch 1 is respectively connected to the BIOS1 and the BIOS2 through the electronic switch 2 and the electronic switch 3.
The electronic switch 1, the electronic switch 2 and the electronic switch 3 adopt the same structure and comprise an S pin, an A pin, a B1 pin and a B2 pin; the pin A is connected with the pin B1 when the level signal received by the pin S is 0, and is connected with the pin B2 when the level signal received by the pin A is 1.
The CPLD chip is respectively connected to the S pins of the electronic switch 1, the electronic switch 2 and the electronic switch 3 through a CPLD signal bus.
Pins A, B1 and B2 of the electronic switch 1, the electronic switch 2 and the electronic switch 3 are all connected to an SPI signal bus and are connected to a target chip through the SPI signal bus;
the SPI signal bus includes an SDO (data out) pin, an SDI (data in) pin, a CS (chip select signal) pin, and a CLK (SPI clock) pin.
The electronic switch 1 is used for selecting the SOC card to be connected with the BIOS1 or the BIOS2, a pin A of the electronic switch 1 is connected with 4 pins of an SPI of the SOC card, a pin B1 is connected with 4 pins of an SPI of the BIOS1, and a pin B2 is connected with 4 pins of an SPI of the BIOS 2;
the electronic switch 2 is used for selecting whether the BIOS1 is connected with the CPU1 or the SOC card, a pin A of the electronic switch 2 is connected with 4 pins of the SPI of the BIOS1, a pin B1 is connected with 4 pins of the SPI of the CPU1, and a pin B2 is connected with 4 pins of the SPI of the SOC card;
the electronic switch 3 is used for selecting whether the BIOS2 is connected with the CPU2 or the SOC card, a pin A of the electronic switch 3 is connected with 4 pins of the SPI of the BIOS2, a pin B1 is connected with 4 pins of the SPI of the CPU2, and a pin B2 is connected with 4 pins of the SPI of the SOC card.
According to the method for realizing the measurement of the double BIOS of the SOC card, the CPLD is used for controlling the level signal to switch the paths of the electronic switch 1, the electronic switch 2 and the electronic switch 3, the SOC card is controlled to start measuring the BIOS1 when being electrified for the first time, and the BIOS1 measurement value stored in the SOC card is compared with the actual BIOS1 measurement value; if the measurement result of the BIOS1 is normal, measuring the BIOS2, and comparing the BIOS2 measurement value stored by the SOC card with the actual BIOS2 measurement value; if the measurement result of the BIOS2 is normal, a reset signal is sent out, so that the BIOS1 is selectively connected with the CPU1, the BIOS2 is selectively connected with the CPU2, the CPU reads the BIOS, and the machine is normally powered on.
When the power is firstly switched on, the SOC is firstly connected with the BIOS1 channel in a clamping way, and the specific flow is as follows:
s1, the SOC card always sends out reset to prevent the machine from starting, and the measurement state is 1;
s2, the CPLD chip sends level signals to the electronic switch 1, the electronic switch 2 and the electronic switch 3 respectively to enable the S1 state of the S pin of the electronic switch 1 to be 0, and the SOC card switch is selectively connected with a path in the direction of the BIOS 1; the S pin S2 of the electronic switch 2 is in a state of 1, and the BIOS1 is selected to be connected with an SOC card passage; the S pin S3 of the electronic switch 3 is in a state of 1, and the BIOS2 is selected to be connected with an SOC card passage;
s3, the SOC card starts to measure the BIOS1, and the BIOS1 measured value stored by the SOC card is compared with the measured value of the actual BIOS 1;
if the measurement is normal, the measurement state is 0;
if the measurement fails, the SOC card is powered off, the machine is powered off, and the starting fails.
When measuring the BIOS2, the SOC card is connected with the BIOS2 channel, the received measurement state is 0, and at the moment
The level signal received by the S pin S1 of the electronic switch 1 is 1, and the SOC card switch is selectively connected to the BIOS2 directional path;
the level signal received by the S pin S2 of the electronic switch 2 is 1, and the BIOS1 selects to connect to the SOC card channel;
the level signal received by the S pin S3 of the electronic switch 3 is 1, and the BIOS2 selects to connect to the SOC card channel;
the SOC card starts to measure the BIOS2, and the BIOS2 measured value stored by the SOC card is compared with the measured value of the actual BIOS 2;
if the measurement is normal, the measurement state is 0, and the reset signal is 1;
if the measurement fails, the SOC card is powered off, the machine is powered off, and the starting fails.
When the reset signal is 1, the reset is started, and at this time
The S pin S1 state of electronic switch 1 is not limiting,
the level signal received by the S pin S2 of the electronic switch 2 is 1, and the BIOS1 is selectively connected to the CPU1, so that the CPU1 is connected to the BIOS1 path;
the level signal received by the S pin S3 of the electronic switch 3 is 1, and the BIOS2 is selectively connected to the CPU2, so that the CPU2 is connected to the BIOS2 path;
the CPU reads the BIOS, and the machine is powered on normally.
The invention has the beneficial effects that: the realization framework and the realization method of the SOC card measurement double BIOS can realize double BIOS measurement, prevent the BIOS information from being falsified and ensure the normal starting of the double-channel CPU computer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a method for implementing SOC card measurement dual BIOS of the present invention.
Fig. 2 is a schematic diagram of the structure of the electronic switch pin of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the embodiment of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The SOC card measurement dual-BIOS implementation framework comprises an SOC card and a CPLD chip, wherein the SOC card and the CPLD chip are both connected with an electronic switch 1, and the CPLD chip is also connected with an electronic switch 2 and an electronic switch 3; the dual-way CPU is respectively connected to the BIOS through an electronic switch 2 and an electronic switch 3, and the electronic switch 1 is respectively connected to the BIOS1 and the BIOS2 through the electronic switch 2 and the electronic switch 3.
The electronic switch 1, the electronic switch 2 and the electronic switch 3 adopt the same structure and comprise an S pin, an A pin, a B1 pin and a B2 pin; the pin A is connected with the pin B1 when the level signal received by the pin S is 0, and is connected with the pin B2 when the level signal received by the pin A is 1.
The CPLD chip is respectively connected to the S pins of the electronic switch 1, the electronic switch 2 and the electronic switch 3 through a CPLD signal bus.
Pins A, B1 and B2 of the electronic switch 1, the electronic switch 2 and the electronic switch 3 are all connected to an SPI signal bus and are connected to a target chip through the SPI signal bus;
the SPI signal bus includes an SDO (data out) pin, an SDI (data in) pin, a CS (chip select signal) pin, and a CLK (SPI clock) pin.
The electronic switch 1 is used for selecting the SOC card to be connected with the BIOS1 or the BIOS2, a pin A of the electronic switch 1 is connected with 4 pins of an SPI of the SOC card, a pin B1 is connected with 4 pins of an SPI of the BIOS1, and a pin B2 is connected with 4 pins of an SPI of the BIOS 2;
the electronic switch 2 is used for selecting whether the BIOS1 is connected with the CPU1 or the SOC card, a pin A of the electronic switch 2 is connected with 4 pins of the SPI of the BIOS1, a pin B1 is connected with 4 pins of the SPI of the CPU1, and a pin B2 is connected with 4 pins of the SPI of the SOC card;
the electronic switch 3 is used for selecting whether the BIOS2 is connected with the CPU2 or the SOC card, a pin A of the electronic switch 3 is connected with 4 pins of the SPI of the BIOS2, a pin B1 is connected with 4 pins of the SPI of the CPU2, and a pin B2 is connected with 4 pins of the SPI of the SOC card.
The method for realizing the measurement of the double BIOS of the SOC card comprises the steps of switching the paths of an electronic switch 1, an electronic switch 2 and an electronic switch 3 through a CPLD control level signal, controlling the SOC card to start measuring the BIOS1 when the SOC card is electrified for the first time, and comparing a BIOS1 measurement value stored in the SOC card with a measurement value of an actual BIOS 1; if the measurement result of the BIOS1 is normal, measuring the BIOS2, and comparing the BIOS2 measurement value stored by the SOC card with the actual BIOS2 measurement value; if the measurement result of the BIOS2 is normal, a reset signal is sent out, so that the BIOS1 is selectively connected with the CPU1, the BIOS2 is selectively connected with the CPU2, the CPU reads the BIOS, and the machine is normally powered on.
When the power is firstly switched on, the SOC is firstly connected with the BIOS1 channel in a clamping way, and the specific flow is as follows:
s1, the SOC card always sends out reset to prevent the machine from starting, and the measurement state is 1;
s2, the CPLD chip sends level signals to the electronic switch 1, the electronic switch 2 and the electronic switch 3 respectively to enable the S1 state of the S pin of the electronic switch 1 to be 0, and the SOC card switch is selectively connected with a path in the direction of the BIOS 1; the S pin S2 of the electronic switch 2 is in a state of 1, and the BIOS1 is selected to be connected with an SOC card passage; the S pin S3 of the electronic switch 3 is in a state of 1, and the BIOS2 is selected to be connected with an SOC card passage;
s3, the SOC card starts to measure the BIOS1, and the BIOS1 measured value stored by the SOC card is compared with the measured value of the actual BIOS 1;
if the measurement is normal, the measurement state is 0;
if the measurement fails, the SOC card is powered off, the machine is powered off, and the starting fails.
When measuring the BIOS2, the SOC card is connected with the BIOS2 channel, the received measurement state is 0, and at the moment
The level signal received by the S pin S1 of the electronic switch 1 is 1, and the SOC card switch is selectively connected to the BIOS2 directional path;
the level signal received by the S pin S2 of the electronic switch 2 is 1, and the BIOS1 selects to connect to the SOC card channel;
the level signal received by the S pin S3 of the electronic switch 3 is 1, and the BIOS2 selects to connect to the SOC card channel;
the SOC card starts to measure the BIOS2, and the BIOS2 measured value stored by the SOC card is compared with the measured value of the actual BIOS 2;
if the measurement is normal, the measurement state is 0, and the reset signal is 1;
if the measurement fails, the SOC card is powered off, the machine is powered off, and the starting fails.
When the reset signal is 1, the reset is started, and at this time
The S pin S1 state of electronic switch 1 is not limiting,
the level signal received by the S pin S2 of the electronic switch 2 is 1, and the BIOS1 is selectively connected to the CPU1, so that the CPU1 is connected to the BIOS1 path;
the level signal received by the S pin S3 of the electronic switch 3 is 1, and the BIOS2 is selectively connected to the CPU2, so that the CPU2 is connected to the BIOS2 path;
the CPU reads the BIOS, and the machine is powered on normally.
The above describes in detail an implementation architecture and method of a dual BIOS for SOC card measurement in the embodiment of the present invention. While the present invention has been described with reference to specific examples, which are provided to assist in understanding the core concepts of the present invention, it is intended that all other embodiments that can be obtained by those skilled in the art without departing from the spirit of the present invention shall fall within the scope of the present invention.
Claims (9)
1. An implementation architecture of dual BIOS for SOC card measurement is characterized in that: the system comprises an SOC card and a CPLD chip, wherein the SOC card and the CPLD chip are both connected with an electronic switch 1, and the CPLD chip is also connected with an electronic switch 2 and an electronic switch 3; the dual-way CPU is respectively connected to the BIOS through an electronic switch 2 and an electronic switch 3, and the electronic switch 1 is respectively connected to the BIOS1 and the BIOS2 through the electronic switch 2 and the electronic switch 3.
2. The SOC card metric dual BIOS implementation architecture of claim 1, wherein: the electronic switch 1, the electronic switch 2 and the electronic switch 3 adopt the same structure and comprise an S pin, an A pin, a B1 pin and a B2 pin; the pin A is connected with the pin B1 when the level signal received by the pin S is 0, and is connected with the pin B2 when the level signal received by the pin A is 1.
3. The implementation architecture of the SOC card metric dual BIOS of claim 2, wherein: the CPLD chip is respectively connected to the S pins of the electronic switch 1, the electronic switch 2 and the electronic switch 3 through a CPLD signal bus.
4. The implementation architecture of the SOC card metric dual BIOS of claim 2, wherein: pins A, B1 and B2 of the electronic switch 1, the electronic switch 2 and the electronic switch 3 are all connected to an SPI signal bus and are connected to a target chip through the SPI signal bus;
the SPI signal bus includes an SDO pin, an SDI pin, a CS pin, and a CLK pin.
5. The SOC card metrology dual BIOS implementation architecture of claim 4 wherein: the electronic switch 1 is used for selecting the SOC card to be connected with the BIOS1 or the BIOS2, a pin A of the electronic switch 1 is connected with 4 pins of an SPI of the SOC card, a pin B1 is connected with 4 pins of an SPI of the BIOS1, and a pin B2 is connected with 4 pins of an SPI of the BIOS 2;
the electronic switch 2 is used for selecting whether the BIOS1 is connected with the CPU1 or the SOC card, a pin A of the electronic switch 2 is connected with 4 pins of the SPI of the BIOS1, a pin B1 is connected with 4 pins of the SPI of the CPU1, and a pin B2 is connected with 4 pins of the SPI of the SOC card;
the electronic switch 3 is used for selecting whether the BIOS2 is connected with the CPU2 or the SOC card, a pin A of the electronic switch 3 is connected with 4 pins of the SPI of the BIOS2, a pin B1 is connected with 4 pins of the SPI of the CPU2, and a pin B2 is connected with 4 pins of the SPI of the SOC card.
6. A realization method of dual BIOS for SOC card measurement is characterized in that: switching the paths of the electronic switch 1, the electronic switch 2 and the electronic switch 3 through the CPLD control level signal, controlling the SOC card to start measuring the BIOS1 when the SOC card is electrified for the first time, and comparing the BIOS1 metric value stored by the SOC card with the actual BIOS1 metric value; if the measurement result of the BIOS1 is normal, measuring the BIOS2, and comparing the BIOS2 measurement value stored by the SOC card with the actual BIOS2 measurement value; if the measurement result of the BIOS2 is normal, a reset signal is sent out, so that the BIOS1 is selectively connected with the CPU1, the BIOS2 is selectively connected with the CPU2, the CPU reads the BIOS, and the machine is normally powered on.
7. The method of claim 6, wherein the SOC card metric dual BIOS comprises: when the power is firstly switched on, the SOC is firstly connected with the BIOS1 channel in a clamping way, and the specific flow is as follows:
s1, the SOC card always sends out reset to prevent the machine from starting, and the measurement state is 1;
s2, the CPLD chip sends level signals to the electronic switch 1, the electronic switch 2 and the electronic switch 3 respectively to enable the S1 state of the S pin of the electronic switch 1 to be 0, and the SOC card switch is selectively connected with a path in the direction of the BIOS 1; the S pin S2 of the electronic switch 2 is in a state of 1, and the BIOS1 is selected to be connected with an SOC card passage; the S pin S3 of the electronic switch 3 is in a state of 1, and the BIOS2 is selected to be connected with an SOC card passage;
s3, the SOC card starts to measure the BIOS1, and the BIOS1 measured value stored by the SOC card is compared with the measured value of the actual BIOS 1;
if the measurement is normal, the measurement state is 0;
if the measurement fails, the SOC card is powered off, the machine is powered off, and the starting fails.
8. The method for implementing the SOC card metric dual BIOS of claim 6 or 7, wherein: when measuring the BIOS2, the SOC card is connected with the BIOS2 channel, the received measurement state is 0, and at the moment
The level signal received by the S pin S1 of the electronic switch 1 is 1, and the SOC card switch is selectively connected to the BIOS2 directional path;
the level signal received by the S pin S2 of the electronic switch 2 is 1, and the BIOS1 selects to connect to the SOC card channel;
the level signal received by the S pin S3 of the electronic switch 3 is 1, and the BIOS2 selects to connect to the SOC card channel;
the SOC card starts to measure the BIOS2, and the BIOS2 measured value stored by the SOC card is compared with the measured value of the actual BIOS 2;
if the measurement is normal, the measurement state is 0, and the reset signal is 1;
if the measurement fails, the SOC card is powered off, the machine is powered off, and the starting fails.
9. The method of claim 6, wherein the SOC card metric dual BIOS comprises: when the reset signal is 1, the reset is started, and at this time
The S pin S1 state of electronic switch 1 is not limiting,
the level signal received by the S pin S2 of the electronic switch 2 is 1, and the BIOS1 is selectively connected to the CPU1, so that the CPU1 is connected to the BIOS1 path;
the level signal received by the S pin S3 of the electronic switch 3 is 1, and the BIOS2 is selectively connected to the CPU2, so that the CPU2 is connected to the BIOS2 path;
the CPU reads the BIOS, and the machine is powered on normally.
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