CN112816888B - Terminal awakening method, detection circuit and terminal - Google Patents
Terminal awakening method, detection circuit and terminal Download PDFInfo
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- CN112816888B CN112816888B CN201911129876.5A CN201911129876A CN112816888B CN 112816888 B CN112816888 B CN 112816888B CN 201911129876 A CN201911129876 A CN 201911129876A CN 112816888 B CN112816888 B CN 112816888B
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000001514 detection method Methods 0.000 title claims abstract description 24
- 230000002618 waking effect Effects 0.000 claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims description 55
- 238000005070 sampling Methods 0.000 claims description 46
- 230000009977 dual effect Effects 0.000 claims description 45
- 238000007599 discharging Methods 0.000 claims description 9
- 239000000523 sample Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013068 control sample Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/385—Arrangements for measuring battery or accumulator variables
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16557—Logic probes, i.e. circuits indicating logic state (high, low, O)
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Secondary Cells (AREA)
Abstract
The application discloses a method for waking up a terminal and a detection circuit for battery charging, wherein the method for waking up the terminal comprises the following steps: acquiring a stored battery voltage; acquiring the current battery voltage of the terminal; comparing the current battery voltage with the stored battery voltage; and if the current battery voltage is larger than the stored battery voltage, judging that the battery is in a charging state, and waking up the terminal. The application can effectively detect and identify the charging state of the battery in the shutdown state, and wake up the terminal when detecting the charging.
Description
Technical Field
The present application relates to the field of communications, and in particular, to a method for waking up a terminal, a detection circuit, and a terminal.
Background
In the prior art, the terminal is not provided with a charging management module, and then the terminal is additionally provided with a sensor or an intelligent battery built-in MCU (Micro Controller Unit, a main control chip), and the sensor or the intelligent battery built-in MCU is communicated with the terminal through an interface, so that the terminal obtains the charging state of the battery, and the cost is high.
Disclosure of Invention
The application provides a terminal awakening method, a detection circuit and a terminal, and aims to solve the problem of high cost in the prior art.
In order to solve the technical problems, the application adopts a technical scheme that: a method of waking up a terminal is provided, the method comprising obtaining a stored battery voltage; acquiring the current battery voltage of the terminal; comparing the current battery voltage with the stored battery voltage; if the current battery voltage is greater than the stored battery voltage, judging that the battery is in a charging state, and waking up the terminal.
Wherein the terminal includes an adjustable timing control circuit and a sampling comparison circuit coupled to the adjustable timing control circuit, the step of obtaining the stored battery voltage comprising: controlling the charging time of the adjustable timing control circuit so that the adjustable timing control circuit generates a first control signal at intervals of the charging time; the voltage of the battery is stored by the sampling comparison circuit according to the first control signal so as to obtain the stored battery voltage.
Wherein the step of comparing the current battery voltage with the stored battery voltage comprises: the current battery voltage is compared with the stored battery voltage by a sample comparison circuit.
Wherein the terminal further comprises a logic control circuit coupled to the sampling comparison circuit, the method further comprising, after the step of if the current battery voltage is greater than the stored battery voltage: generating a second control signal by the sampling comparison circuit; the step of waking up the terminal includes the steps of: judging that the battery is in a charging state according to the second control signal; and waking up the terminal according to the second control signal through the logic control circuit.
In order to solve the technical problems, the application adopts another technical scheme that: the detection circuit comprises a sampling comparison circuit and a logic control circuit, wherein the sampling comparison circuit is coupled with the logic control circuit; the sampling comparison circuit is used for acquiring the stored battery voltage and the current battery voltage of the terminal and comparing the current battery voltage with the stored battery voltage; if the current battery voltage is greater than the stored battery voltage, the sampling comparison circuit judges that the battery is in a charging state, and the logic control circuit is used for waking up the terminal.
The detection circuit further comprises an adjustable timing control circuit coupled to the sampling comparison circuit, the adjustable timing control circuit is used for controlling the charging time of the adjustable timing control circuit so that the adjustable timing control circuit can generate a first control signal at intervals of the charging time, and the sampling comparison circuit further stores the voltage of the battery according to the first control signal to obtain the stored battery voltage.
The adjustable timing control circuit comprises a first double-operation amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first diode and a first capacitor, wherein one end of the first resistor receives a first battery voltage, the other end of the first resistor is connected with one end of the second resistor and the third end of the first double-operation amplifier, the other end of the second resistor is grounded, the third end of the first double-operation amplifier is connected with the first end of the first double-operation amplifier through the third resistor, the fourth end of the first double-operation amplifier is connected with the positive electrode of the first diode and one end of the first capacitor, the other end of the first capacitor is grounded, the negative electrode of the first diode is connected with one end of the fourth resistor, and the other end of the fourth resistor is connected with the first end of the first double-operation amplifier.
The sampling comparison circuit comprises a second double-operation amplifier, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second capacitor, a third capacitor, a fourth capacitor and a first switch tube, wherein one end of the fifth resistor is connected with the other end of the fourth resistor, the other end of the fifth resistor is connected with one end of the sixth resistor, one end of the second capacitor is connected with the grid electrode of the first switch tube, the other end of the second resistor is grounded, the other end of the sixth resistor receives a second battery voltage, the other end of the sixth resistor is connected with the source electrode of the first switch tube, the drain electrode of the first switch tube is connected with one end of the seventh resistor, one end of the third capacitor is connected with the third end of the second double-operation amplifier, the other end of the seventh resistor is connected with the other end of the third capacitor, one end of the eighth resistor is further grounded, the other end of the eighth resistor is connected with one end of the ninth resistor, one end of the fourth capacitor is connected with the fourth end of the fourth double-operation amplifier, and the other end of the fourth capacitor is further grounded.
The logic control circuit comprises a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a second diode, a third diode, a fifth capacitor and a second switching tube, wherein the negative electrode of the second diode is connected with one end of the tenth resistor and the first end of the second dual-operation amplifier, the positive electrode of the second diode is connected with the other end of the tenth resistor, one end of the fifth capacitor and one section of the eleventh resistor, the other end of the fifth capacitor is grounded, one end of the eleventh resistor is connected with the first end of the second switching tube, the other end of the twelfth resistor is grounded, the second end of the second switching tube is grounded, the third end of the second switching tube is connected with one end of the thirteenth resistor and the positive electrode of the third diode, and the other end of the thirteenth resistor receives voltage.
In order to solve the technical problems, the application adopts another technical scheme that: there is provided a terminal comprising the detection circuit described above.
The beneficial effects of the application are as follows: in contrast to the prior art, the method for waking up a terminal of the present application includes obtaining a stored battery voltage; acquiring the current battery voltage of the terminal; comparing the current battery voltage with the stored battery voltage; if the current battery voltage is greater than the stored battery voltage, judging that the battery is in a charging state, and waking up the terminal. Therefore, the application can directly detect the voltage of the battery to judge whether the battery is in a charging state, and wake up the terminal when judging that the battery is in the charging state, without additionally arranging a sensor or an intelligent battery built-in MCU, thereby reducing the cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of one embodiment of a method of waking up a terminal in accordance with the present application;
FIG. 2 is a flow chart of another embodiment of a method of waking up a terminal in accordance with the present application;
FIG. 3 is a schematic circuit diagram of an embodiment of the detection circuit of the present application;
FIG. 4 is a schematic circuit diagram of the adjustable timing control circuit of FIG. 3;
FIG. 5 is a circuit schematic of the sample comparison circuit of FIG. 3;
FIG. 6 is a circuit schematic of the logic control circuit of FIG. 3;
Fig. 7 is a circuit schematic of an embodiment of the terminal of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 is a flowchart of a method for waking up a terminal according to an embodiment of the present application. The method for waking up the terminal in this embodiment is applied to a terminal, and the terminal may be a terminal with a battery, such as an interphone, a mobile phone, and the like.
As shown in fig. 1, the method for waking up a terminal includes the following steps:
S101, acquiring the stored battery voltage.
As shown in fig. 3, the detection circuit 3 of the terminal may include an adjustable timing control circuit 31, a sampling comparison circuit 32, and a logic control circuit 33, the sampling comparison circuit 32 being coupled to the adjustable timing control circuit 31, the logic control circuit 33 being coupled to the sampling comparison circuit 32.
Wherein the terminal obtains the stored battery voltage. That is, the terminal controls the charging time of the adjustable timing control circuit 31 such that the adjustable timing control circuit 31 generates the first control signal at intervals of the charging time; for example, the adjustable timing control circuit 31 includes a charging process and a discharging process, the adjustable timing control circuit 31 outputs a first level during the charging process, the adjustable timing control circuit 31 outputs a first control signal during the discharging process, the first control signal is a second level, and the first level is different from the second level.
The terminal stores the voltage of the battery according to the first control signal through the sampling comparison circuit 32 to obtain the stored battery voltage. That is, when the sampling comparison circuit 32 receives the first control signal, the sampling comparison circuit 32 charges and stores the voltage of the battery, and the terminal acquires the stored battery voltage.
And S102, acquiring the current battery voltage of the terminal.
The terminal obtains the current battery voltage of the terminal. I.e., the terminal control sample comparison circuit 32 obtains the current battery voltage of the terminal.
And S103, comparing the current battery voltage with the stored battery voltage.
Wherein the terminal compares the current battery voltage with the stored battery voltage. I.e. the terminal compares the present battery voltage with the stored battery voltage via the sample comparison circuit 32. When the terminal determines that the current battery voltage is greater than the stored battery voltage, it proceeds to step S104.
And S104, if the current battery voltage is larger than the stored battery voltage, judging that the battery is in a charging state, and waking up the terminal.
And the terminal judges that the battery is in a charging state and wakes up the terminal. For example, when the terminal is in a power-off state or a sleep state and the terminal judges that the battery is in a charging state, the terminal is awakened to enable the terminal to be in a power-on state or a working state so as to remind the user that the terminal is being charged.
The terminal generates a second control signal through the sampling comparison circuit 32, and judges that the battery is in a charging state according to the second control signal through the logic control circuit 33, so as to wake up the terminal.
According to the embodiment, whether the battery is in the charging state or not is judged by comparing the current battery voltage with the stored battery voltage, and when the battery is judged to be in the charging state, the terminal is awakened, a sensor or an intelligent battery built-in MCU is not required to be additionally arranged, and the cost is reduced.
Referring to fig. 2, fig. 2 is a flowchart of another embodiment of a method for waking up a terminal according to the present application.
S201, acquiring the stored battery voltage.
And S202, acquiring the current battery voltage of the terminal.
And S203, comparing the current battery voltage with the stored battery voltage.
Steps S201 to S203 are the same as steps S101 to S103 in the above embodiment, and are not described here again.
And S204, if the current battery voltage is smaller than the stored battery voltage, judging that the battery is in a non-charging state.
When the terminal determines that the current battery voltage is smaller than the stored battery voltage, the terminal generates a third control signal through the sampling comparison circuit 32, and the logic control circuit 33 determines that the battery is in a non-charging state according to the third control signal.
The present application further provides a detection circuit 3, as shown in fig. 3, the detection circuit 3 includes an adjustable timing control circuit 31, a sampling comparison circuit 32 and a logic control circuit 33, the adjustable timing control circuit 31 is coupled to the sampling comparison circuit 32, and the sampling comparison circuit 32 is coupled to the logic control circuit 33.
The sampling comparison circuit 32 is configured to obtain a stored battery voltage and a current battery voltage of the terminal, and compare the current battery voltage with the stored battery voltage; if the current battery voltage is greater than the stored battery voltage, the sampling comparison circuit 32 determines that the battery is in a charged state, and the logic control circuit 33 is configured to wake up the terminal.
The adjustable timing control circuit 31 is configured to control a charging time of the adjustable timing control circuit 31, so that the adjustable timing control circuit 31 generates a first control signal at intervals of the charging time, and the sampling comparison circuit 32 further stores a voltage of the battery according to the first control signal to obtain the stored battery voltage.
The detection circuit 3 of the embodiment compares the current battery voltage with the stored battery voltage through the sampling comparison circuit 32 to judge whether the battery is in a charging state, and wakes up the terminal when judging that the battery is in the charging state, so that a sensor or an intelligent battery built-in MCU is not required to be additionally arranged, and the cost is reduced.
Referring to fig. 4, the adjustable timing control circuit 31 includes a first dual operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first diode D1 and a first capacitor C1.
One end of the first resistor R1 receives the first battery voltage U 1, the other end of the first resistor R1 is connected with one end of the second resistor R2 and the third end of the first double operational amplifier U1, the other end of the second resistor R2 is grounded, the third end of the first double operational amplifier U1 is connected with the first end of the first double operational amplifier U1 through the third resistor R3, the fourth end of the first double operational amplifier U1 is connected with the positive electrode of the first diode D1 and one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, the negative electrode of the first diode D1 is connected with one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected with the first end of the first double operational amplifier U1. The fifth end of the first dual operational amplifier U1 receives the supply voltage U 4, and the second end of the first dual operational amplifier U1 is grounded, i.e., one end of the first resistor R1 and the fifth end of the first dual operational amplifier U1 may be connected to a battery of the terminal.
The third terminal of the first dual operational amplifier U1 is an in-phase terminal, and the fourth terminal of the first dual operational amplifier U1 is an anti-phase terminal.
When the adjustable timing control circuit 31 is charged, the reference voltage received by the fourth terminal of the first dual operational amplifier U1 is zero, the third terminal of the first dual operational amplifier U1 receives the first battery voltage U 1, at this time, the voltage of the third terminal of the first dual operational amplifier U1 is greater than the voltage of the fourth terminal of the first dual operational amplifier U1, the first terminal of the first dual operational amplifier U1 charges the first capacitor C1 through the fourth resistor R4 and the first diode D1, at this time, the first terminal of the first dual operational amplifier U1 outputs the first level, and the first level is the high level.
When the adjustable timing control circuit 31 completes charging, the voltage at the third terminal of the first dual operational amplifier U1 is smaller than the voltage at the fourth terminal of the first dual operational amplifier U1 (i.e., the voltage at which the charging of the first capacitor C1 is completed), the first dual operational amplifier U1 performs inversion, and the first terminal of the first dual operational amplifier U1 outputs the first control signal until the discharging of the first capacitor C1 is completed. The first control signal is at a second level, and the first control signal is at a low level.
In this embodiment, the first diode D1 is disposed between the fourth resistor R4 and the first capacitor C1, and because of the unidirectional conduction characteristic of the first diode D1, the first end of the first dual operational amplifier U1 has a long charging time for charging the fourth end of the first dual operational amplifier U1, and the discharging time of the fourth end of the first dual operational amplifier U1 is short, so that the first dual operational amplifier U1 outputs a second level for a short time after outputting a long first level, and then alternately outputs the first level and the second level. Alternatively, the charging time or the discharging time is adjusted by adjusting the first diode D1 and the first capacitor C1.
Referring to fig. 5, the sampling comparison circuit 32 includes a second dual operational amplifier U2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a first switching tube Q1.
One end of the fifth resistor R5 is connected to the other end of the fourth resistor R4, the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6, one end of the second capacitor C2 and the gate of the first switching tube Q1, the other end of the second capacitor C2 is grounded, the other end of the sixth resistor R6 receives the second battery voltage U 2, the other end of the sixth resistor R6 is connected to the source of the first switching tube Q1, the drain of the first switching tube Q1 is connected to one end of the seventh resistor R7, one end of the third capacitor C3 and the third end of the second dual operational amplifier U2, the other end of the seventh resistor R7 is connected to the other end of the third capacitor C3, the other end of the third capacitor C3 is further grounded, one end of the eighth resistor R8 receives the third battery voltage U 3, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9, one end of the fourth capacitor C4 and the fourth end of the fourth dual operational amplifier U2, the other end of the ninth resistor R9 is connected to the other end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is further grounded. The fifth terminal of the second dual operational amplifier U2 receives a fifth battery voltage U 5, the second terminal of the second dual operational amplifier U2 is grounded, and the fifth battery voltage U 5, the third battery voltage U 3, and the second battery voltage U 2 are all battery voltages.
The third terminal of the second dual operational amplifier U2 is an in-phase terminal, and the fourth terminal of the second dual operational amplifier U2 is an anti-phase terminal.
When the sampling comparison circuit 32 receives the first control signal generated by the adjustable timing control circuit 31, the first switching tube Q1 is turned on, and the second battery voltage U 2 is stored in a loop formed by the seventh resistor R7 and the third capacitor C3, that is, the third capacitor C3 is charged. The first switching tube Q1 may be a Pmos tube. In other embodiments, the first switching tube Q1 may be other switching tubes, such as Nmos tubes. When the third capacitor C3 is charged, the voltage at the third terminal of the second dual operational amplifier U2 is the second battery voltage U 2, which is equivalent to the voltage stored by the sampling comparison circuit 32 through the third capacitor C3 according to the first control signal, and the stored battery voltage is the second battery voltage U 2.
When the sampling comparison circuit 32 receives the first level generated by the adjustable timing control circuit 31, the first switching tube Q1 is turned off, at this time, the third capacitor C3 is discharged, and the voltage at the third terminal of the second dual operational amplifier U2 is the stored battery voltage. The third battery voltage U 3 is the current battery voltage, so the sampling comparison circuit 32 obtains the current battery voltage through the fourth terminal of the second dual operational amplifier U2. The sample comparison circuit 32 further compares the current battery voltage with the stored battery voltage; if the current battery voltage is greater than the stored battery voltage, that is, the voltage at the fourth terminal of the second dual operational amplifier U2 is greater than the voltage at the third terminal of the second dual operational amplifier U2, the sampling comparison circuit 32 determines that the battery is in a charged state; if the current battery voltage is smaller than the stored battery voltage, that is, the voltage at the fourth terminal of the second dual operational amplifier U2 is smaller than the voltage at the third terminal of the second dual operational amplifier U2, the sampling comparison circuit 32 determines that the battery is in a non-charged state.
When the sampling comparison circuit 32 determines that the battery is in a charged state, the first terminal of the second dual operational amplifier U2 outputs a second control signal, and the second control signal is at a low level.
Referring to fig. 6, the logic control circuit 33 includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a second diode D2, a third diode D3, a fifth capacitor C5, and a second switching tube Q2.
The negative pole of the second diode D2 is connected with one end of a tenth resistor R10 and the first end of a second double-operation amplifier U2, the positive pole of the second diode D2 is connected with the other end of the tenth resistor R10, one end of a fifth capacitor C5 and one end of an eleventh resistor R11, the other end of the fifth capacitor C5 is grounded, the other end of the eleventh resistor R11 is connected with one end of a twelfth resistor R12 and the first end of a second switching tube Q2, the other end of the twelfth resistor R12 is grounded, the second end of the second switching tube Q2 is grounded, the third end of the second switching tube Q2 is connected with one end of a thirteenth resistor R13 and the positive pole of a third diode D3, the negative pole of the third diode D3 is used for waking up a terminal, and the other end of the thirteenth resistor R13 receives a voltage U 6. The second switching tube Q2 may be an Nmos tube.
When the logic control circuit 33 receives the high level, the second switching tube Q2 is turned on, at this time, the thirteenth resistor R13 is grounded, the cathode of the third diode D3 is at the low level, and the terminal is kept in the off state or the sleep state. When the logic control circuit 33 receives the second control signal, the second switching tube Q2 is turned off, and the voltage U 6 is a wake-up signal for waking up the terminal.
The present application further provides a terminal, as shown in fig. 7, the terminal 7 includes a detection circuit 71 and a battery 72, the detection circuit 71 is used for determining whether the battery 72 is in a charging state, and the detection circuit 71 is the detection circuit and will not be described herein.
In summary, the detection circuit of the application compares the current battery voltage with the stored battery voltage through the sampling comparison circuit to judge whether the battery is in a charging state, and when the battery is judged to be in the charging state, the logic control circuit wakes up the terminal without additionally arranging a sensor or an intelligent battery built-in MCU, thereby reducing the cost.
The foregoing is only illustrative of the present application and is not to be construed as limiting the scope of the application, and all equivalent structures or equivalent flow modifications which may be made by the teachings of the present application and the accompanying drawings or which may be directly or indirectly employed in other related art are within the scope of the application.
Claims (8)
1. A method of waking up a terminal, the method comprising:
acquiring a stored battery voltage;
Acquiring the current battery voltage of the terminal;
comparing the current battery voltage with the stored battery voltage;
if the current battery voltage is larger than the stored battery voltage, judging that the battery is in a charging state, and waking up the terminal;
Wherein the terminal includes an adjustable timing control circuit and a sampling comparison circuit coupled to the adjustable timing control circuit, the step of obtaining the stored battery voltage includes:
Controlling the charging time of the adjustable timing control circuit so that the adjustable timing control circuit generates a first control signal at intervals of the charging time;
Storing the voltage of the battery according to the first control signal by the sampling comparison circuit so as to acquire the stored battery voltage;
the adjustable timing control circuit comprises a charging process and a discharging process, the adjustable timing control circuit outputs a first level in the charging process, and the adjustable timing control circuit outputs the first control signal in the discharging process, wherein the first control signal is a second level; the first level is different from the second level.
2. The method of claim 1, wherein the step of comparing the current battery voltage with the stored battery voltage comprises:
the current battery voltage is compared with the stored battery voltage by the sampling comparison circuit.
3. The method of claim 2, wherein the terminal further comprises a logic control circuit coupled to the sample comparison circuit, the method further comprising, after the step of if the current battery voltage is greater than the stored battery voltage:
generating a second control signal by the sampling comparison circuit;
The step of waking up the terminal after judging that the battery is in a charging state comprises the following steps:
judging that the battery is in a charging state according to the second control signal;
and waking up the terminal according to the second control signal through the logic control circuit.
4. A detection circuit for battery charging, which is characterized by comprising a sampling comparison circuit and a logic control circuit, wherein the sampling comparison circuit is coupled with the logic control circuit;
The sampling comparison circuit is used for acquiring the stored battery voltage and the current battery voltage of the terminal, and comparing the current battery voltage with the stored battery voltage;
If the current battery voltage is larger than the stored battery voltage, the sampling comparison circuit judges that the battery is in a charging state, and the logic control circuit is used for waking up the terminal;
The detection circuit further includes an adjustable timing control circuit coupled to the sampling comparison circuit, the adjustable timing control circuit configured to control a charging time of the adjustable timing control circuit such that the adjustable timing control circuit generates a first control signal at intervals of the charging time, the sampling comparison circuit further storing a voltage of the battery in accordance with the first control signal to obtain the stored battery voltage;
the adjustable timing control circuit comprises a charging process and a discharging process, the adjustable timing control circuit outputs a first level in the charging process, and the adjustable timing control circuit outputs the first control signal in the discharging process, wherein the first control signal is a second level; the first level is different from the second level.
5. The detection circuit according to claim 4, wherein the adjustable timing control circuit includes a first dual operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first diode, and a first capacitor, one end of the first resistor receives a first battery voltage, the other end of the first resistor is connected to one end of the second resistor, a third end of the first dual operational amplifier is grounded, the third end of the first dual operational amplifier is connected to a first end of the first dual operational amplifier through the third resistor, a fourth end of the first dual operational amplifier is connected to an anode of the first diode and one end of the first capacitor, the other end of the first capacitor is grounded, a cathode of the first diode is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the first end of the first dual operational amplifier; the third end of the first double operational amplifier is an in-phase end, and the fourth end of the first double operational amplifier is an anti-phase end; the first end of the first dual operational amplifier is an output end.
6. The detection circuit according to claim 5, wherein the sampling comparison circuit includes a second dual operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second capacitor, a third capacitor, a fourth capacitor, and a first switching tube, one end of the fifth resistor is connected to the other end of the fourth resistor, the other end of the fifth resistor is connected to one end of the sixth resistor, one end of the second capacitor, and a gate of the first switching tube, the other end of the second capacitor is grounded, the other end of the sixth resistor receives a second battery voltage, the other end of the sixth resistor is connected to a source of the first switching tube, a drain of the first switching tube is connected to one end of the seventh resistor, one end of the third capacitor, and a third end of the second dual operational amplifier, the other end of the seventh resistor is connected to the other end of the third capacitor, the other end of the third capacitor is further grounded, one end of the eighth resistor receives a second battery voltage, the other end of the eighth resistor receives a fourth battery voltage, the other end of the fourth resistor is connected to the other end of the fourth resistor, and the other end of the fourth capacitor is connected to the ninth resistor, and the other end of the fourth resistor is further connected to the ninth resistor; the third end of the second double-operation amplifier is an in-phase end, and the fourth end of the second double-operation amplifier is an anti-phase end.
7. The detection circuit according to claim 6, wherein the logic control circuit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a second diode, a third diode, a fifth capacitor, and a second switching tube, a negative electrode of the second diode is connected to one end of the tenth resistor and a first end of the second dual operational amplifier, a positive electrode of the second diode is connected to the other end of the tenth resistor, one end of the fifth capacitor, and one end of the eleventh resistor, the other end of the fifth resistor is grounded, the other end of the eleventh resistor is connected to one end of the twelfth resistor and the first end of the second switching tube, the other end of the twelfth resistor is grounded, a second end of the second switching tube is grounded, a third end of the second switching tube is connected to one end of the thirteenth resistor and a positive electrode of the third diode, and the other end of the thirteenth resistor receives a voltage; wherein the first end of the second double-operation amplifier is an output end; when the logic control circuit receives a high level, the second switching tube is conducted, and the thirteenth resistor is grounded; when the logic control circuit receives a low level, the second switching tube is opened.
8. A terminal comprising a detection circuit as claimed in any one of claims 4 to 7.
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