CN112803943B - Digital AND gate implementation method based on three-value memristor - Google Patents

Abstract

The invention discloses a digital AND gate implementation method based on a three-value memristor. The invention designs a forward-forward three-value AND gate circuit, a reverse-forward three-value AND gate circuit, a forward-reverse three-value AND gate circuit and a reverse-reverse three-value AND gate circuit, wherein a three-value memristor in the AND gate circuit is a voltage-controlled threshold three-value memristor. The invention has clear and simple structure and is easy to realize. The AND gate circuit model has important significance for application research in various fields such as multi-value digital logic operation and the like.

Description

Implementation method of digital AND gate based on ternary memristor

technical field

The invention belongs to the technical field of circuit design and relates to a method for realizing a digital AND gate based on a ternary memristor.

Background technique

In 1971, Professor Cai Shaotang proposed the fourth type of basic circuit element - memristor from the perspective of completeness of circuit theory. In 2008, Hewlett-Packard Labs successfully developed the first physical element of memristor, and this breakthrough triggered a research boom in related fields of memristor. After further research, it is found that memristors can be applied to non-volatile memory, logic operations, brain-like neuromorphic computing and other fields by virtue of their nanoscale and non-volatile characteristics, that is, in the development of information storage and computing fusion methods. Has great potential.

In recent years, memristors have made some progress in the realization of digital logic operations, but most of the current research focuses on binary logic. Compared with traditional binary logic, ternary logic carries a higher amount of information on a single signal line, and can effectively reduce circuit overhead such as interconnection and chip area, so it can achieve simple circuit structure and efficient energy utilization , which has attracted the attention of researchers.

Memristors can be divided into binary memristors and multi-valued memristors according to the number of resistance states they can hold. For example, the three-valued memristor has three different resistance states of high, low and medium, and can realize three different logic values in the three-valued logic without using any additional devices, which is better than the ordinary two-valued memristor. Three-valued logical operations have even greater advantages. Therefore, ternary memristors have broad prospects in the field of ternary digital logic gate circuit design, and also provide the possibility to realize the mode of in-situ fusion of ternary information storage and calculation.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention proposes a new realization method of a digital AND gate based on a ternary memristor.

The technical scheme adopted by the present invention to solve the technical problem is as follows: comprising a forward-forward three-value AND gate circuit (Forward-Forward-TAND, FF-TAND), three three-value AND gate circuits obtained through expansion: reverse -Forward three-valued AND gate circuit (Backward-Forward-TAND, BF-TAND), forward-reverse three-valued AND gate circuit (Forward-Backward-TAND, FB-TAND), reverse-reverse three-valued AND gate circuit Gate circuit (Backward-Backward-TAND, BB-TAND).

The input memristor and output memristor of FF-TAND are connected in a forward-forward direction. The circuit is composed of three three-valued memristors. The three resistance states of the memristor represent 0 and 1 of the three-valued logic respectively. ,2. The first memristor M1 is used as a first input memristor, the second memristor M2 is used as a second input memristor, and the third memristor M3 is used as an output memristor. The positive pole of the first memristor M1 is connected to the DC power supply V, the negative pole of the first memristor M1 is connected to the positive pole of the second memristor M2, the negative pole of the second memristor M2 is connected to the positive pole of the third memristor M3 connected, and the negative electrode of the third memristor M3 is grounded.

The connection mode of the input memristor and the output memristor of BF-TAND is reverse-forward, and the circuit is composed of three ternary memristors. 1, 2. The first memristor M1 is used as a first input memristor, the second memristor M2 is used as a second input memristor, and the third memristor M3 is used as an output memristor. The negative pole of the first memristor M1 is connected to the DC power supply V, the positive pole of the first memristor M1 is connected to the negative pole of the second memristor M2, the positive pole of the second memristor M2 is connected to the positive pole of the third memristor M3 connected, and the negative electrode of the third memristor M3 is grounded.

The connection between the input memristor and the output memristor of FB-TAND is forward-reverse. The circuit is composed of three three-valued memristors, and the three resistance states of the memristor represent 0 and 1 of the three-valued logic respectively. ,2. The first memristor M1 is used as a first input memristor, the second memristor M2 is used as a second input memristor, and the third memristor M3 is used as an output memristor. The positive pole of the first memristor M1 is connected to the DC power supply V, the negative pole of the first memristor M1 is connected to the positive pole of the second memristor M2, the negative pole of the second memristor M2 is connected to the negative pole of the third memristor M3 connected, and the anode of the third memristor M3 is grounded.

The input memristor and output memristor of BB-TAND are connected reverse-reversely. The circuit is composed of three ternary memristors. The three resistance states of the memristor represent 0, 1, 2. The first memristor M1 is used as a first input memristor, the second memristor M2 is used as a second input memristor, and the third memristor M3 is used as an output memristor. The negative pole of the first memristor M1 is connected to the DC power supply V, the positive pole of the first memristor M1 is connected to the negative pole of the second memristor M2, the positive pole of the second memristor M2 is connected to the negative pole of the third memristor M3 connected, and the anode of the third memristor M3 is grounded.

The present invention designs a new type of ternary digital logic AND gate circuit model based on ternary memristor, and expands it from the perspective of device connection in the circuit to obtain three additional novel AND gate circuits, with a clear and simple structure, Easy to implement. The AND gate circuit model is of great significance to the application research in many fields such as multi-valued digital logic operation.

Description of drawings

FIG. 1 is a forward-forward three-value AND gate circuit based on a three-value memristor of the present invention.

FIG. 2 is a reverse-forward three-value AND gate circuit based on a three-value memristor of the present invention.

FIG. 3 is a forward-reverse three-value AND gate circuit based on a three-value memristor of the present invention.

FIG. 4 is a reverse-reverse three-value AND gate circuit based on a three-value memristor of the present invention.

Detailed ways

The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

The ternary memristor model adopted in the design of the present invention is a voltage-controlled threshold type ternary memristor, and its mathematical model is described by the following formula:

In the formula, a, b, c, d, e are adjustable parameters in the model, x is the internal state variable of the system, v(t) represents the voltage across the memristor, i(t) represents the voltage flowing through the memristor Current, v _th1 and v _th2 represent two different threshold voltages, R _L , R _M , R _H correspond to three different resistance states from low to high of the model respectively.

Under the action of an applied voltage, the memristor model can exhibit threshold characteristics. When v>v _th2 , the memristor is set to _RL . When v _th1 <v<v _th2 , if the state of the memristor model is R _H at this time, it will quickly drop to R _M , otherwise the original state will remain unchanged. When -v _th1 <v<v _th1 , the model will always keep the original state. When -v _th2 <v<-v _th1 , if the resistance value of the memristor is smaller than _RM at this time, it will increase to _RM , otherwise it will not change. When v<-v _th2 , the model is set to R _H .

The four three-valued AND gate circuits designed in the present invention are composed of only three three-valued memristors, two of which are used as input memristors and the other is used as output memristors. The logic state of the three-valued AND gate is represented by the resistance value of the memristor, and R _H , R _M , and _RL represent "0", "1" and "2" of the three-valued logic respectively. In this design, both R _in1 and R _in2 are input memristors, R _out is an output memristor, and V is a DC power supply. The initial state of memristors R _in1 and R _in2 are the two inputs of this logic gate, and the initial state of R _out is R _H . The truth table of the three-valued AND gate logic is shown in the following table:

R _in1 R _in2 R _out R _H (0) R _H (0) R _H (0) R _H (0) R _M (1) R _H (0) R _H (0) R _L (2) R _H (0) R _M (1) R _H (0) R _H (0) R _M (1) R _M (1) R _M (1) R _M (1) R _L (2) R _M (1) R _L (2) R _H (0) R _H (0) R _L (2) R _M (1) R _M (1) R _L (2) R _L (2) R _L (2)

The four ternary AND gates involved in the present invention are all driven by an excitation voltage source V. Each operation of a logic gate can be divided into two phases, one is the initial phase, in this phase, V outputs a small measurement voltage V _MS for measuring the initial state of each memristor, by reading the memristor The voltage across the resistor and the current flowing through it are used to measure the resistance of the memristor. The value of this measured voltage should be small so that the divided voltage across each memristor does not exceed a set threshold voltage, so that the memristor does not change its state. The second stage is called the running stage, during which V outputs a larger operating voltage V _OP to complete logic operations. In all types of AND gate circuits described below, the measurement voltage V _MS is 0.5V, but for the operating voltage V _OP , different values need to be selected in different gate circuits. Since the parameters and positions of the two input memristors in this logic gate circuit are the same, some repeated results are omitted in the following analysis.

Preferably, for the designed four AND gate circuits, the relevant parameters of the above-mentioned ternary memristor model used are a=e=10, b=10000, c=d=0.2, and the threshold voltages v _th1 and v _th2 are respectively Set to 0.9V and 1.1V; R _H , R _M , _RL are 10kΩ, 1kΩ, 100Ω respectively.

As shown in FIG. 1 , it is a forward-forward three-valued AND gate circuit structure of the present invention. The operating voltage V _OP of the logic gate circuit is 1.5V.

In the operation phase, when the inputs are all logic "0", the resistance sum of the input memristor is 20kΩ, and the divided voltage across the output memristor R _out is 0.5V. When the input is "0" and "1", the resistance sum of the input memristor is 11kΩ, and the divided voltage across the output memristor R _out is 0.714V. When the input is "0" and "2", the resistance sum of the input memristor is 10.1kΩ, and the divided voltage across the output memristor R _out is 0.746V. In the above three cases, the voltage across the output memristor R _out does not exceed the threshold value of 0.9V, so R _out keeps the initial state R _H unchanged, that is, the output logic "0".

When the inputs are all logic "1", the resistance sum of the input memristor is 2kΩ, and the divided voltage across the output memristor is 1.25V. When the input is "1" and "2", the resistance sum of the input memristor is 1.1kΩ, and the divided voltage across the output memristor is 1.35V. In the above two cases, the voltage across the output memristor R _out exceeds the threshold voltage v _th1 =0.9V, so R _H is set to R _M . Because the resistance of the output memristor drops, the voltage divided across the device also decreases. The voltage drop across the output memristor was 0.5V in the former case and 0.714V in the latter case. In both cases, since the voltage across R _out does not exceed v _th2 =1.1V, the state of the memristor will not change further, so the logic gate outputs a logic “1”.

When the input is logic "2", the resistance sum of the input memristor is 200Ω, and the divided voltage across the output memristor is 1.47V, which is greater than the threshold voltage v _th1 = 0.9V, so that R _out is first set to R _M. After R _out is set to R _M , the divided voltage across the output memristor becomes 1.25V, which is still greater than the threshold voltage v _th2 = 1.1V, so the state of the output memristor finally switches to R _L , that is, the logic gate output logical "2".

As shown in FIG. 2 , the connection mode of the input and output memristors of the above-mentioned first three-value AND gate circuit is changed to obtain the reverse-forward three-value AND gate circuit structure of the present invention. Because the direction of the output memristor is the same as that of the FF-TAND, the operating voltage V _OP of the logic gate circuit is 1.5V.

In the operation phase, when the inputs are all logic "0", the resistance sum of the input memristor is 20kΩ, and the divided voltage across the output memristor R _out is 0.5V. When the input is "0" and "1", the resistance sum of the input memristor is 11kΩ, and the divided voltage across the output memristor R _out is 0.714V. When the input is "0" and "2", the resistance sum of the input memristor is 10.1kΩ, and the divided voltage across the output memristor R _out is 0.746V. In the above three cases, the voltage across the output memristor R _out does not exceed the threshold value of 0.9V, so R _out keeps the initial state R _H unchanged, that is, the output logic "0".

When the inputs are all logic "1", the resistance sum of the input memristor is 2kΩ, and the divided voltage across the output memristor is 1.25V. When the input is "1" and "2", the resistance sum of the input memristor is 1.1kΩ, and the divided voltage across the output memristor is 1.35V. In the above two cases, the voltage across the output memristor R _out exceeds the threshold voltage v _th1 =0.9V, so R _H is set to R _M . Because the resistance of the output memristor drops, the voltage divided across the device also decreases. The voltage drop across the output memristor was 0.5V in the former case and 0.714V in the latter case. In both cases, since the voltage across R _out does not exceed v _th2 =1.1V, the state of the memristor will not change further, so the logic gate outputs a logic “1”.

When the input is logic "2", the resistance sum of the input memristor is 200Ω, and the divided voltage across the output memristor is 1.47V, which is greater than the threshold voltage v _th1 = 0.9V, so that R _out is first set to R _M. After R _out is set to R _M , the divided voltage across the output memristor becomes 1.25V, which is still greater than the threshold voltage v _th2 = 1.1V, so the state of the output memristor finally switches to R _L , that is, the logic gate output logical "2".

As shown in FIG. 3, the forward-reverse three-valued AND circuit structure of the present invention is obtained by changing the connection mode of the input and output memristors of the above-mentioned first three-valued AND gate circuit. Because the direction of the output memristor is opposite to that of the FF-TAND, the operating voltage V _OP of the logic gate circuit is -1.5V.

In the operation phase, when the inputs are all logic "0", the resistance sum of the input memristor is 20kΩ, and the divided voltage across the output memristor R _out is 0.5V. When the input is "0" and "1", the resistance sum of the input memristor is 11kΩ, and the divided voltage across the output memristor R _out is 0.714V. When the input is "0" and "2", the resistance sum of the input memristor is 10.1kΩ, and the divided voltage across the output memristor R _out is 0.746V. In the above three cases, the voltage across the output memristor R _out does not exceed the threshold value of 0.9V, so R _out keeps the initial state R _H unchanged, that is, the output logic "0".

When the inputs are all logic "1", the resistance sum of the input memristor is 2kΩ, and the divided voltage across the output memristor is 1.25V. When the input is "1" and "2", the resistance sum of the input memristor is 1.1kΩ, and the divided voltage across the output memristor is 1.35V. In the above two cases, the voltage across the output memristor R _out exceeds the threshold voltage v _th1 =0.9V, so R _H is set to R _M . Because the resistance of the output memristor drops, the voltage divided across the device also decreases. The voltage drop across the output memristor was 0.5V in the former case and 0.714V in the latter case. In both cases, since the voltage across R _out does not exceed v _th2 =1.1V, the state of the memristor will not change further, so the logic gate outputs a logic “1”.

When the input is logic "2", the resistance sum of the input memristor is 200Ω, and the divided voltage across the output memristor is 1.47V, which is greater than the threshold voltage v _th1 = 0.9V, so that R _out is first set to R _M. After R _out is set to R _M , the divided voltage across the output memristor becomes 1.25V, which is still greater than the threshold voltage v _th2 = 1.1V, so the state of the output memristor finally switches to R _L , that is, the logic gate output logical "2".

As shown in FIG. 4 , the connection mode of the input and output memristors of the above-mentioned first three-valued AND gate circuit is changed to obtain the reverse-reverse three-valued AND gate circuit structure of the present invention. Because the direction of the output memristor is the same as that of the FF-TAND, the operating voltage V _OP of the logic gate circuit is 1.5V.

In the operation phase, when the inputs are all logic "0", the resistance sum of the input memristor is 20kΩ, and the divided voltage across the output memristor R _out is 0.5V. When the input is "0" and "1", the resistance sum of the input memristor is 11kΩ, and the divided voltage across the output memristor R _out is 0.714V. When the input is "0" and "2", the resistance sum of the input memristor is 10.1kΩ, and the divided voltage across the output memristor R _out is 0.746V. In the above three cases, the voltage across the output memristor R _out does not exceed the threshold value of 0.9V, so R _out keeps the initial state R _H unchanged, that is, the output logic "0".

When the inputs are all logic "1", the resistance sum of the input memristor is 2kΩ, and the divided voltage across the output memristor is 1.25V. When the input is "1" and "2", the resistance sum of the input memristor is 1.1kΩ, and the divided voltage across the output memristor is 1.35V. In the above two cases, the voltage across the output memristor R _out exceeds the threshold voltage v _th1 =0.9V, so R _H is set to R _M . Because the resistance of the output memristor drops, the voltage divided across the device also decreases. The voltage drop across the output memristor was 0.5V in the former case and 0.714V in the latter case. In both cases, since the voltage across R _out does not exceed v _th2 =1.1V, the state of the memristor will not change further, so the logic gate outputs a logic “1”.

When the input is logic "2", the resistance sum of the input memristor is 200Ω, and the divided voltage across the output memristor is 1.47V, which is greater than the threshold voltage v _th1 = 0.9V, so that R _out is first set to R _M. After R _out is set to R _M , the divided voltage across the output memristor becomes 1.25V, which is still greater than the threshold voltage v _th2 = 1.1V, so the state of the output memristor finally switches to R _L , that is, the logic gate output logical "2".

Those of ordinary skill in the art should recognize that the above embodiments are only used to verify the present invention, rather than as a limitation of the present invention, as long as they are within the scope of the present invention, changes and deformations to the above embodiments will fall within the scope of the present invention. within the protection scope of the present invention.

Claims (1)

1. The digital AND gate implementation method based on the three-value memristor is characterized by comprising the following steps of:

the adopted three-value memristor is a voltage-controlled threshold three-value memristor, and the mathematical model is described by the following formula:

wherein a, b, c, d, e are in the modelAn adjustable parameter, x is a system internal state variable, v (t) represents the voltage at two ends of the memristor, i (t) represents the current flowing through the memristor, v _th1 And v _th2 Representing two different threshold voltages, R _L 、R _M 、R _H Three different resistance states corresponding to the model from low to high respectively represent '0', '1', '2' of three-value logic respectively;

the digital AND gate is formed by adopting three-value memristors, wherein two of the three-value memristors are used as input memristors, and the other one of the three-value memristors is used as output memristors;

let R be _in1 And R is _in2 All are input memristors, R _out Is an output memristor, V is a dc power supply; memristor R _in1 And R is _in2 Is the initial state of the digital AND gate, R _out Is R in the initial state _H The method comprises the steps of carrying out a first treatment on the surface of the The truth table for digital AND gate logic is shown in the following table:

the operation of digital AND gates is divided into two phases:

the first phase is an initial phase in which the DC power supply V outputs a small measurement voltage V _MS The method comprises the steps of measuring initial states of all memristors, and measuring resistance values of the memristors by reading voltages at two ends of the memristors and current flowing through the memristors; the measurement voltage V _MS The voltage division on each memristor does not exceed the set threshold voltage, so that the memristor does not change the state;

the second stage is an operation stage, in which the DC power supply V outputs an operation voltage V _OP For completing logical operations;

case one: let a=e=10, b=10000, c=d=0.2, threshold voltage v in mathematical model _th1 And v _th2 Set to 0.9V and 1.1V, respectively; r is R _H 、R _M 、R _L The first memristor M1 is used as a first input memristor, the second memristor M2 is used as a second input memristor, and the third memristor M3 is used as an output memristor; the positive electrode of the first memristor M1 is connected with a direct-current power supply V, the negative electrode of the first memristor M1 is connected with the positive electrode of the second memristor M2, the negative electrode of the second memristor M2 is connected with the positive electrode of the third memristor M3, and the negative electrode of the third memristor M3 is grounded;

operating voltage V at digital AND gate _OP At 1.5V:

in the operation stage, when the inputs are all logic '0', the sum of the resistance values of the input memristors is 20kΩ, and the memristors R are output _out The partial pressure at the two ends is 0.5V; when the input is 0 and 1, the sum of the resistance values of the input memristors is 11k omega, and the memristor R is output _out The partial pressure at the two ends is 0.714V; when the input is 0 and 2, the sum of the resistance values of the input memristors is 10.1kΩ, and the memristor R is output _out The partial pressure at the two ends is 0.746V; in these three cases, the memristor R is output _out The voltage across both ends does not exceed the threshold value of 0.9V, therefore R _out Maintain the initial state R _H Unchanged, i.e. outputting a logic "0";

when the inputs are all logic '1', the sum of the resistance values of the input memristors is 2k omega, and the partial pressure at two ends of the output memristors is 1.25V; when the input is 1 and 2, the sum of the resistance values of the input memristors is 1.1kΩ, and the partial pressure at two ends of the output memristors is 1.35V; in both cases, the memristor R is output _out The voltage across both ends exceeds the threshold voltage v _th1 =0.9v, thus R _H All will be set as R _M The method comprises the steps of carrying out a first treatment on the surface of the Because the resistance of the output memristor is reduced, the partial voltage at two ends of the device is also reduced; in the former case, the voltage across the output memristor drops to 0.5V, in the latter case 0.714V; in both cases due to R _out The voltage across it does not exceed v _th2 =1.1v, so the state of the memristor does not change further, so the logic gate outputs a logic "1";

when the inputs are all logic "2", the resistance of the memristor is inputThe sum of the values is 200Ω, the voltage division at the two ends of the output memristor is 1.47V, which is larger than the threshold voltage V _th1 =0.9v, so that R _out Is first set as R _M The method comprises the steps of carrying out a first treatment on the surface of the At R _out Is set as R _M After that, the voltage division at the two ends of the output memristor is changed to 1.25V and is still greater than the threshold voltage V _th2 =1.1v, so the state of the output memristor eventually switches to R _L I.e. the logic gate outputs a logic "2";

and a second case: let a=e=10, b=10000, c=d=0.2, threshold voltage v in mathematical model _th1 And v _th2 Set to 0.9V and 1.1V, respectively; r is R _H 、R _M 、R _L The first memristor M1 is used as a first input memristor, the second memristor M2 is used as a second input memristor, and the third memristor M3 is used as an output memristor; the cathode of the first memristor M1 is connected with a direct-current power supply V, the anode of the first memristor M1 is connected with the cathode of the second memristor M2, the anode of the second memristor M2 is connected with the anode of the third memristor M3, and the cathode of the third memristor M3 is grounded;

operating voltage V at digital AND gate _OP At 1.5V:

in the operation stage, when the inputs are all logic '0', the sum of the resistance values of the input memristors is 20kΩ, and the memristors R are output _out The partial pressure at the two ends is 0.5V; when the input is 0 and 1, the sum of the resistance values of the input memristors is 11k omega, and the memristor R is output _out The partial pressure at the two ends is 0.714V; when the input is 0 and 2, the sum of the resistance values of the input memristors is 10.1kΩ, and the memristor R is output _out The partial pressure at the two ends is 0.746V; in these three cases, the memristor R is output _out The voltage across both ends does not exceed the threshold value of 0.9V, therefore R _out Maintain the initial state R _H Unchanged, i.e. outputting a logic "0";

when the inputs are all logic '1', the sum of the resistance values of the input memristors is 2k omega, and the partial pressure at two ends of the output memristors is 1.25V; when the input is 1 and 2, the sum of the resistance values of the input memristors is 1.1kΩ, and the partial pressure at two ends of the output memristors is 1.35V; in both cases, the memristor R is output _out The voltage across both ends exceeds the threshold voltage v _th1 =0.9v, thus R _H All will be set as R _M The method comprises the steps of carrying out a first treatment on the surface of the Because the resistance of the output memristor is reduced, the partial voltage at two ends of the device is also reduced; in the former case, the voltage across the output memristor drops to 0.5V, in the latter case 0.714V; in both cases due to R _out The voltage across it does not exceed v _th2 =1.1v, so the state of the memristor does not change further, so the logic gate outputs a logic "1";

when the inputs are all logic '2', the sum of the resistance values of the input memristors is 200Ω, the partial pressure at two ends of the output memristors is 1.47V, and the partial pressure is larger than the threshold voltage V _th1 =0.9v, so that R _out Is first set as R _M The method comprises the steps of carrying out a first treatment on the surface of the At R _out Is set as R _M After that, the voltage division at the two ends of the output memristor is changed to 1.25V and is still greater than the threshold voltage V _th2 =1.1v, so the state of the output memristor eventually switches to R _L I.e. the logic gate outputs a logic "2";

and a third case: let a=e=10, b=10000, c=d=0.2, threshold voltage v in mathematical model _th1 And v _th2 Set to 0.9V and 1.1V, respectively; r is R _H 、R _M 、R _L The first memristor M1 is used as a first input memristor, the second memristor M2 is used as a second input memristor, and the third memristor M3 is used as an output memristor; the positive electrode of the first memristor M1 is connected with a direct-current power supply V, the negative electrode of the first memristor M1 is connected with the positive electrode of the second memristor M2, the negative electrode of the second memristor M2 is connected with the negative electrode of the third memristor M3, and the positive electrode of the third memristor M3 is grounded;

operating voltage V at digital AND gate _OP at-1.5V:

in the operation stage, when the inputs are all logic '0', the sum of the resistance values of the input memristors is 20kΩ, and the memristors R are output _out The partial pressure at the two ends is 0.5V; when the input is 0 and 1, the sum of the resistance values of the input memristors is 11k omega, and the memristor R is output _out The partial pressure at the two ends is 0.714V; when the input is 0 and 2, the sum of the resistance values of the input memristors is 10.1kΩ, and the memristor R is output _out The partial pressure at the two ends is 0.746V; among these three typesIn the case of output memristor R _out The voltage across both ends does not exceed the threshold value of 0.9V, therefore R _out Maintain the initial state R _H Unchanged, i.e. outputting a logic "0";

when the inputs are all logic '1', the sum of the resistance values of the input memristors is 2k omega, and the partial pressure at two ends of the output memristors is 1.25V; when the input is 1 and 2, the sum of the resistance values of the input memristors is 1.1kΩ, and the partial pressure at two ends of the output memristors is 1.35V; in both cases, the memristor R is output _out The voltage across both ends exceeds the threshold voltage v _th1 =0.9v, thus R _H All will be set as R _M The method comprises the steps of carrying out a first treatment on the surface of the Because the resistance of the output memristor is reduced, the partial voltage at two ends of the device is also reduced; in the former case, the voltage across the output memristor drops to 0.5V, in the latter case 0.714V; in both cases due to R _out The voltage across it does not exceed v _th2 =1.1v, so the state of the memristor does not change further, so the logic gate outputs a logic "1";

when the inputs are all logic '2', the sum of the resistance values of the input memristors is 200Ω, the partial pressure at two ends of the output memristors is 1.47V, and the partial pressure is larger than the threshold voltage V _th1 =0.9v, so that R _out Is first set as R _M The method comprises the steps of carrying out a first treatment on the surface of the At R _out Is set as R _M After that, the voltage division at the two ends of the output memristor is changed to 1.25V and is still greater than the threshold voltage V _th2 =1.1v, so the state of the output memristor eventually switches to R _L I.e. the logic gate outputs a logic "2";

case four: let a=e=10, b=10000, c=d=0.2, threshold voltage v in mathematical model _th1 And v _th2 Set to 0.9V and 1.1V, respectively; r is R _H 、R _M 、R _L The first memristor M1 is used as a first input memristor, the second memristor M2 is used as a second input memristor, and the third memristor M3 is used as an output memristor; the cathode of the first memristor M1 is connected with a direct-current power supply V, the anode of the first memristor M1 is connected with the cathode of the second memristor M2, the anode of the second memristor M2 is connected with the cathode of the third memristor M3, and the anode of the third memristor M3 is grounded;

operating voltage V at digital AND gate _OP At 1.5V:

in the operation stage, when the inputs are all logic '0', the sum of the resistance values of the input memristors is 20kΩ, and the memristors R are output _out The partial pressure at the two ends is 0.5V; when the input is 0 and 1, the sum of the resistance values of the input memristors is 11k omega, and the memristor R is output _out The partial pressure at the two ends is 0.714V; when the input is 0 and 2, the sum of the resistance values of the input memristors is 10.1kΩ, and the memristor R is output _out The partial pressure at the two ends is 0.746V; in these three cases, the memristor R is output _out The voltage across both ends does not exceed the threshold value of 0.9V, therefore R _out Maintain the initial state R _H Unchanged, i.e. outputting a logic "0";

when the inputs are all logic '1', the sum of the resistance values of the input memristors is 2k omega, and the partial pressure at two ends of the output memristors is 1.25V; when the input is 1 and 2, the sum of the resistance values of the input memristors is 1.1kΩ, and the partial pressure at two ends of the output memristors is 1.35V; in both cases, the memristor R is output _out The voltage across both ends exceeds the threshold voltage v _th1 =0.9v, thus R _H All will be set as R _M The method comprises the steps of carrying out a first treatment on the surface of the Because the resistance of the output memristor is reduced, the partial voltage at two ends of the device is also reduced; in the former case, the voltage across the output memristor drops to 0.5V, in the latter case 0.714V; in both cases due to R _out The voltage across it does not exceed v _th2 =1.1v, so the state of the memristor does not change further, so the logic gate outputs a logic "1";

when the inputs are all logic '2', the sum of the resistance values of the input memristors is 200Ω, the partial pressure at two ends of the output memristors is 1.47V, and the partial pressure is larger than the threshold voltage V _th1 =0.9v, so that R _out Is first set as R _M The method comprises the steps of carrying out a first treatment on the surface of the At R _out Is set as R _M After that, the voltage division at the two ends of the output memristor is changed to 1.25V and is still greater than the threshold voltage V _th2 =1.1v, so the state of the output memristor eventually switches to R _L I.e. the logic gate outputs a logic "2".

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