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CN112768424B - A semiconductor device and a half-bridge circuit module using a power half-bridge stacking solution - Google Patents

A semiconductor device and a half-bridge circuit module using a power half-bridge stacking solution Download PDF

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Publication number
CN112768424B
CN112768424B CN202110079922.6A CN202110079922A CN112768424B CN 112768424 B CN112768424 B CN 112768424B CN 202110079922 A CN202110079922 A CN 202110079922A CN 112768424 B CN112768424 B CN 112768424B
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transistor
window region
electrode
semiconductor device
transistors
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CN112768424A (en
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喻辉洁
蔡坤明
周宗杰
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Xiamen Biyi Micro Electronic Technique Co ltd
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Xiamen Biyi Micro Electronic Technique Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device and a half-bridge circuit module employing a power half-bridge stack package scheme are disclosed, the semiconductor device including a package frame and at least two transistors stacked on a base of the package frame, wherein an upper transistor of two adjacent transistors is disposed in a first window region of an upper surface of a lower transistor, and a series or parallel connection is achieved in the first window region. The semiconductor device of the invention stacks at least two transistors on the base of the packaging frame, reduces the requirement on the number of base islands of the base, is convenient for compatibility with the common packaging frame, and reduces the packaging cost. According to the half-bridge circuit module, the first transistor and the second transistor are arranged on the base of the packaging frame in a stacked mode, and the first transistor and the second transistor are electrically connected in series through the conducting layer, so that the requirement on a base island of the base of the packaging frame is reduced, the half-bridge circuit module is convenient to be compatible with a common packaging frame, and the packaging cost is reduced.

Description

Semiconductor device adopting power half-bridge stacking and sealing scheme and half-bridge circuit module
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device adopting a power half-bridge stacking scheme and a half-bridge circuit module.
Background
In the field of high-voltage high-power supply application, it is a common method to implement various power topologies by using a high-voltage MOS (metal-oxide semiconductor, metal oxide semiconductor) half bridge and its driving technology.
The high-voltage MOS half-bridge is composed of an upper tube and a lower tube, which are NMOS (N-Metal-Oxide-Semiconductor) tubes, and referring to fig. 1, the drain end of the upper tube M1 is connected to the bus potential V1, the source end of the lower tube M2 is connected to the reference potential V2, and the source end of the upper tube M1 is connected to the drain end of the lower tube M2.
Referring TO the TO252 package structure of fig. 2, most NMOS transistors are three-terminal devices, and the pins include a source terminal S, a gate terminal G and a drain terminal D, and in the high voltage (voltage withstanding over 500V) MOS half-bridge structure, most of the two required high voltage NMOS transistors are combined structures of two separate packaged NMOS transistors, so that the integration level is low, or two separate NMOS transistors are integrated, a specially designed package structure is required, and the cost is high.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a semiconductor device and a half-bridge circuit module using a power half-bridge stack package scheme, so as to realize integrated packaging of at least two transistors in a conventional packaging architecture, and reduce integrated packaging cost of a multi-transistor.
According to an aspect of the present invention, there is provided a semiconductor device employing a power half-bridge stack package scheme, comprising:
the packaging frame comprises a base;
at least two transistors stacked on the base, wherein,
The upper surface of a lower transistor of adjacent transistors of the at least two transistors includes a first window region including at least one of a source electrode and a drain electrode of the lower transistor therein;
an upper transistor of adjacent transistors of the at least two transistors is disposed in the first window region of the lower transistor, and a lower surface of the upper transistor includes at least one of a source electrode and a drain electrode of the upper transistor and is connected in series or parallel with at least one of the source electrode and the drain electrode of the lower transistor.
Optionally, a transistor of the at least two transistors comprises a vertical double diffused metal oxide semiconductor tube.
Optionally, the at least two transistors include:
The first transistor is arranged on the base, the upper surface of the first transistor comprises a first windowing region and a second windowing region which are isolated through an insulating layer, the lower surface of the first transistor comprises a drain electrode, the first windowing region of the first transistor comprises a source electrode of the first transistor, and the second windowing region of the first transistor comprises a gate electrode of the first transistor;
A second transistor disposed on the first window region of the first transistor, the upper surface of the second transistor including a first window region and a second window region isolated by an insulating layer, the lower surface including a drain electrode electrically connected to the source electrode of the first transistor, the first window region of the second transistor including the source electrode of the second transistor, the second window region of the second transistor including the gate electrode of the second transistor,
The first transistor and the second transistor are both longitudinal double-diffused metal oxide field effect transistors.
Optionally, a conductive layer is disposed between the first window region of the first transistor and the lower surface of the second transistor, and the conductive layer includes a conductive adhesive.
Optionally, the first transistor and the second transistor are high voltage transistors.
Optionally, the first transistor and the second transistor are NMOS transistors.
Optionally, the area of the first window region of the first transistor is larger than the area of the lower surface of the second transistor.
Optionally, the package frame includes:
a first pin electrically connected to a drain electrode of the lower surface of the first transistor;
And the second pin is electrically connected with the source electrode of the first windowing region of the second transistor.
Optionally, the gate electrode of the first transistor and the gate electrode of the second transistor are electrically connected to two pins of the package frame or to the same pin of the package frame, respectively.
According to another aspect of the present invention, there is provided a half-bridge circuit module, characterized by comprising:
the packaging frame comprises a base;
the first transistor is arranged on the base, the upper surface of the first transistor comprises a first windowing region, and the first windowing region comprises a first electrode of the first transistor;
A second transistor disposed above the first transistor, a lower surface of the second transistor including a second electrode of the second transistor, and
And the conductive layer is provided with an upper surface and a lower surface, wherein the lower surface of the conductive layer is coupled with the first windowing region, and the upper surface of the conductive layer is coupled with the lower surface of the second transistor and is used for electrically connecting the first electrode of the first transistor and the second electrode of the second transistor.
The semiconductor device provided by the invention has the advantages that at least two transistors are arranged on the base of the packaging frame in a stacking way, so that the requirement on the number of base islands of the base is reduced, the semiconductor device is convenient to be compatible with a common packaging frame, and the packaging cost is reduced.
According to the half-bridge circuit module provided by the invention, the first transistor and the second transistor are arranged on the base of the packaging frame in a stacked manner, and the first electrode of the first transistor and the second electrode of the second transistor are electrically connected through the conductive layer, so that the requirement on the number of base islands of the base is reduced, the half-bridge circuit module is convenient to be compatible with a common packaging frame, and the packaging cost is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
Fig. 1 shows a schematic structural diagram of a half-bridge construction unit according to the prior art;
FIG. 2 shows a schematic diagram of a package structure according to the prior art;
Fig. 3 shows a schematic cross-sectional structure of a transistor according to the prior art;
Fig. 4 shows a schematic diagram of the upper surface structure of a transistor of a semiconductor device according to an embodiment of the present invention;
Fig. 5 shows a schematic cross-sectional structure of a transistor of a semiconductor device according to an embodiment of the present invention;
Fig. 6 shows a partial schematic structure of a semiconductor device according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples.
Fig. 3 shows a schematic cross-sectional structure of a transistor according to the prior art.
As shown in fig. 3, the transistor 100 is a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor, longitudinal Double-diffused metal oxide semiconductor), in this embodiment, an N-type VDMOS, which is disposed on the substrate 110, two spaced-apart well regions 130 are disposed at two ends of an upper surface of the epitaxial layer 120, the upper surfaces of the two well regions 130 each include a doped region 131, a gate structure is disposed on the epitaxial layer 120, the gate structure includes a gate oxide layer 141 and a polysilicon gate 142, a projection of the polysilicon gate 142 on the upper surfaces of the two well regions 130 is disposed between the two doped regions 131, and the two ends respectively extend to the two doped regions 131 to form a channel region between the two doped regions 131, the gate oxide layer 141 is disposed around the polysilicon gate 142 to isolate the polysilicon gate 142 from direct electrical connection with other structures, the source metal layer 101 covers the upper surface of the transistor 100, is electrically contacted with the well regions 130 and the doped regions 131 to form a source S by a source electrode, the lower surface of the substrate 110 covers the drain metal layer 102 to form a drain electrode, and the polysilicon gate 142 is led out of the polysilicon gate D.
Taking an N-type VDMOS as an example, the substrate 110 is an N-type doped substrate, for example, a silicon substrate, the drift region 120 is an N-type doped region, the well region 130 is a P-type doped region, and the transistor 100 forms a structure with a source S above and a drain D below.
Fig. 4 illustrates a schematic diagram of an upper surface structure of a transistor of a semiconductor device according to an embodiment of the present invention, and fig. 5 illustrates a schematic diagram of a cross-sectional structure of a transistor of a semiconductor device according to an embodiment of the present invention, wherein fig. 5 corresponds to a schematic diagram of a cross-sectional structure of a transistor 200 along an AA line in fig. 4.
Referring to fig. 4 and 5, the upper surface of the transistor 200 of the semiconductor device according to the embodiment of the present invention includes a first window region 201 and a gate structure 220 separated by an insulating layer 210, the upper surface of the first window region 201 corresponds to a source electrode, the gate structure 220 includes a second window region 221 for a gate electrode (polysilicon gate), the lower surface of the transistor 200 corresponds to a drain electrode, and the transistor 200 is identical to the transistor 100 in structure, for example, in that the source electrode and the gate electrode are clearly separated. The electrode material is typically copper, i.e., the surfaces of the first and second window regions 201 and 221 and the lower surface of the transistor 200 are copper-clad.
The thickness from the upper surface of the insulating layer 210 to the lower surface of the transistor 200 is greater than the thickness from the upper surfaces of the first and second window regions 201 and 221 to the lower surface of the transistor 200, so that the insulating performance can be ensured, and the positioning stability of the subsequent upper transistor in the first window region of the lower transistor can be facilitated.
Fig. 6 shows a partial schematic structure of a semiconductor device according to an embodiment of the present invention.
As shown in fig. 6, the semiconductor device 300 of the embodiment of the present invention includes a package frame including a base 310 and a pin 320 fixedly connected to the base 310, and a first transistor 2001 and a second transistor 2002 provided in the package frame. The structures of the first transistor 2001 and the second transistor 2002 are the same as the structure of the transistor 200, except that the size of the second transistor 2002 is smaller than that of the first transistor 2001, and mainly that the surface area of the first window region of the first transistor 2001 is larger than or equal to that of the lower surface of the second transistor 2002, so that the second transistor 2002 can be placed in the first window region of the first transistor 2001, and extraction of the gate electrode of the second window region of the first transistor 2001 is facilitated.
In an alternative embodiment, the size of the second transistor 2002 is larger than the size of the first window area of the first transistor 2001, and the corresponding electrodes of the first transistor 2001 and the second transistor 2002 (the source electrode (the first electrode) of the first window area of the first transistor 2001 and the drain electrode (the second electrode) of the lower surface of the second transistor 2002 are connected) can be electrically connected reliably through the conductive layer 301, so that the size design of the second transistor 2002 can be maintained, the performance of the second transistor 2002 is ensured, and the performance of the corresponding half-bridge circuit module is ensured.
The first transistor 2001 and the second transistor 2002 are sequentially stacked on the base 310, the first transistor 2001 is a lower layer transistor, the first transistor 2001 is directly arranged on the upper surface of the base 310, a drain electrode on the lower surface of the first transistor 2001 is electrically connected with one of the pins 320 through circuit arrangement on the base 310, and a drain terminal of the corresponding semiconductor device 300 is led out.
The second transistor 2002 corresponds to an upper layer transistor, is arranged in a first windowing region of the first transistor 2001, a drain electrode on the lower surface of the second transistor 2002 is electrically connected with a source electrode on the upper surface of the first windowing region of the first transistor 2001, a series structure of the first transistor 2001 and the second transistor 2002 is formed, and a source electrode of the first windowing region of the second transistor 2002, a gate electrode of the second windowing region and a gate electrode of the second windowing region of the first transistor 2001 are connected to corresponding pins 320 through lead wires 304 so as to lead out the source electrode of the second transistor 2002 as a source electrode of the semiconductor device 300, and a gate electrode of the first transistor 2001 and a gate electrode of the second transistor 2002 are led out.
The gate electrodes of the second window regions of the first transistor 2001 and the second transistor 2002 may be respectively led out TO two pins 320 or led out TO the same pin 320, and the control is unified, and the method is applicable TO252 packaging, and only three pins are led out.
In this embodiment, the conductive layer 301 is conductive adhesive, and the lower surface of the second transistor 2002 is electrically connected with the upper surface of the first window region of the first transistor 2001 through the conductive adhesive, so that the reliability of the electrical connection can be ensured, and the conductive adhesive can be sintered at a low temperature, so that the operation is convenient. In an alternative embodiment, the electrical connection between the lower surface of the second transistor 2002 and the upper surface of the first window region of the first transistor 2001 is a chip solder, and correspondingly, the conductive layer 301 is another conductive material such as solder.
In this embodiment, the first transistor 2001 and the second transistor 2002 have the source electrode on the upper surface and the drain electrode on the lower surface, and are stacked to form a series connection, which is a small structural improvement of the conventional VDMOS transistor 100 and is easy to realize. In an alternative embodiment, the upper surface of the first transistor 2001 may be provided with a source electrode and a drain electrode at the same time, the electrode lead may be led out to the pin 320 by using a wire, the source electrode and the drain electrode of the second transistor 2002 may be provided on the same surface, and the source electrode and the drain electrode on the upper surface of the first transistor 2001 are connected in series or in parallel, which may also reduce the number of islands of the base 310.
In the semiconductor device 300 according to the embodiment of the present invention, the first transistor 2001 and the second transistor 2002 are stacked, the second transistor 2002 is disposed on the first window area of the first transistor 2001, the requirement for the base 310 of the package frame is limited to the placement of the first transistor 2001, a conventional package frame can be adopted, no separate design of the package frame is required, and the package of the dual transistor with the half-bridge structure is realized without increasing the design cost of the package frame. The first transistor 2001 and the second transistor 2002 are stacked so as to be closely connected to each other, thereby reducing the resistance in the series connection path.
In this embodiment, taking two stacked transistor arrangements as an example, in an alternative embodiment, a plurality of stacked transistor arrangements are provided, which can also reduce the requirement for the number of islands of the package frame and reduce the package cost.
According to the semiconductor device adopting the power half-bridge stacking and sealing scheme, at least two transistors are stacked and arranged on the base of the packaging frame, so that the requirement on the number of base islands of the base is reduced, the semiconductor device is convenient to be compatible with a common packaging frame, and the packaging cost is reduced. The packaging of the power half-bridge stacking scheme can be in the forms of TO252, TO247, TO263 and the like.
In some embodiments, the wire bonding locations, directions, thicknesses, etc. may be different from those illustrated or described above.
It should be noted that the situation that the positional relationship between the "upper" and the "lower" is exchanged, or the positional relationship after the overall angle is uniformly adjusted, is within the protection scope of the present invention.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (8)

1.一种采用功率半桥叠封方案的半导体器件，其特征在于，包括：1. A semiconductor device adopting a power half-bridge stacking solution, characterized in that it includes: 封装框架，包括底座；A packaging frame, including a base; 至少两个晶体管，层叠设置在所述底座上，其中，At least two transistors are stacked on the base, wherein: 所述至少两个晶体管中的相邻晶体管中的下层晶体管的上表面包括第一开窗区，所述第一开窗区中包括所述下层晶体管的源电极和漏电极中的至少一个；An upper surface of a lower transistor in an adjacent transistor among the at least two transistors includes a first window region, and the first window region includes at least one of a source electrode and a drain electrode of the lower transistor; 所述至少两个晶体管中的相邻晶体管中的上层晶体管设置在所述下层晶体管的第一开窗区中，所述上层晶体管的下表面包括所述上层晶体管的源电极和漏电极中的至少一个，且与所述下层晶体管的源电极和漏电极中的至少一个串联或并联连接；An upper transistor in the adjacent transistors of the at least two transistors is arranged in the first window region of the lower transistor, and a lower surface of the upper transistor includes at least one of a source electrode and a drain electrode of the upper transistor, and is connected in series or in parallel with at least one of a source electrode and a drain electrode of the lower transistor; 所述至少两个晶体管中的晶体管包括纵向双扩散金属氧化物半导体管；A transistor of the at least two transistors comprises a vertical double diffused metal oxide semiconductor; 所述至少两个晶体管包括：The at least two transistors include: 第一晶体管，设置在所述底座上，所述第一晶体管的上表面包括通过绝缘层隔离的第一开窗区和第二开窗区，下表面包括漏电极，所述第一晶体管的第一开窗区中包括所述第一晶体管的源电极，所述第一晶体管的第二开窗区中包括所述第一晶体管的栅电极；A first transistor is disposed on the base, wherein the upper surface of the first transistor includes a first window region and a second window region isolated by an insulating layer, and the lower surface includes a drain electrode, the first window region of the first transistor includes a source electrode of the first transistor, and the second window region of the first transistor includes a gate electrode of the first transistor; 第二晶体管，设置在所述第一晶体管的第一开窗区上，所述第二晶体管的上表面包括通过绝缘层隔离的第一开窗区和第二开窗区，下表面包括与所述第一晶体管的源电极电连接的漏电极，所述第二晶体管的第一开窗区中包括所述第二晶体管的源电极，所述第二晶体管的第二开窗区中包括所述第二晶体管的栅电极，a second transistor, arranged on the first window region of the first transistor, wherein the upper surface of the second transistor includes the first window region and the second window region isolated by the insulating layer, and the lower surface includes a drain electrode electrically connected to the source electrode of the first transistor, the first window region of the second transistor includes the source electrode of the second transistor, and the second window region of the second transistor includes the gate electrode of the second transistor, 所述第一晶体管和所述第二晶体管均为纵向双扩散金属氧化物场效应管。The first transistor and the second transistor are both vertical double diffused metal oxide field effect transistors. 2.根据权利要求1所述的半导体器件，其特征在于，2. The semiconductor device according to claim 1, wherein: 所述第一晶体管的第一开窗区与所述第二晶体管的下表面之间设置有导电层，所述导电层包括导电胶。A conductive layer is arranged between the first window region of the first transistor and the lower surface of the second transistor, and the conductive layer includes conductive glue. 3.根据权利要求1所述的半导体器件，其特征在于，3. The semiconductor device according to claim 1, wherein: 所述第一晶体管和所述第二晶体管为高压晶体管。The first transistor and the second transistor are high voltage transistors. 4.根据权利要求3所述的半导体器件，其特征在于，4. The semiconductor device according to claim 3, characterized in that 所述第一晶体管和所述第二晶体管为NMOS管。The first transistor and the second transistor are NMOS transistors. 5.根据权利要求1所述的半导体器件，其特征在于，5. The semiconductor device according to claim 1, wherein: 所述第一晶体管的第一开窗区的面积大于所述第二晶体管的下表面的面积。An area of a first window region of the first transistor is larger than an area of a lower surface of the second transistor. 6.根据权利要求1所述的半导体器件，其特征在于，所述封装框架包括：6. The semiconductor device according to claim 1, wherein the packaging frame comprises: 第一引脚，与所述第一晶体管的下表面的漏电极电连接；a first pin electrically connected to a drain electrode on a lower surface of the first transistor; 第二引脚，与所述第二晶体管的第一开窗区的源电极电连接。The second pin is electrically connected to the source electrode of the first window region of the second transistor. 7.根据权利要求1或6所述的半导体器件，其特征在于，7. The semiconductor device according to claim 1 or 6, characterized in that: 所述第一晶体管的栅电极和所述第二晶体管的栅电极分别电连接至所述封装框架的两个引脚或连接至所述封装框架的同一引脚。The gate electrode of the first transistor and the gate electrode of the second transistor are respectively electrically connected to two pins of the package frame or to the same pin of the package frame. 8.一种半桥电路模块，其特征在于，包括：8. A half-bridge circuit module, comprising: 封装框架，包括底座；A packaging frame, including a base; 第一晶体管，设置在所述底座上，所述第一晶体管的上表面包括第一开窗区，所述第一开窗区包括所述第一晶体管的第一电极；A first transistor is disposed on the base, wherein an upper surface of the first transistor includes a first window area, and the first window area includes a first electrode of the first transistor; 第二晶体管，设置在所述第一晶体管上方，所述第二晶体管的下表面包括所述第二晶体管的第二电极；以及a second transistor disposed above the first transistor, wherein a lower surface of the second transistor includes a second electrode of the second transistor; and 导电层，具有上表面和下表面，其中，所述导电层的下表面耦接所述第一开窗区，所述导电层的上表面耦接所述第二晶体管的下表面，用于将所述第一晶体管的第一电极和所述第二晶体管的第二电极电性连接；A conductive layer having an upper surface and a lower surface, wherein the lower surface of the conductive layer is coupled to the first window region, and the upper surface of the conductive layer is coupled to the lower surface of the second transistor, for electrically connecting the first electrode of the first transistor and the second electrode of the second transistor; 所述晶体管包括纵向双扩散金属氧化物半导体管；The transistor comprises a vertical double diffused metal oxide semiconductor tube; 所述晶体管包括：The transistor comprises: 第一晶体管，设置在所述底座上，所述第一晶体管的上表面包括通过绝缘层隔离的第一开窗区和第二开窗区，下表面包括漏电极，所述第一晶体管的第一开窗区中包括所述第一晶体管的源电极，所述第一晶体管的第二开窗区中包括所述第一晶体管的栅电极；A first transistor is disposed on the base, wherein the upper surface of the first transistor includes a first window region and a second window region isolated by an insulating layer, and the lower surface includes a drain electrode, the first window region of the first transistor includes a source electrode of the first transistor, and the second window region of the first transistor includes a gate electrode of the first transistor; 第二晶体管，设置在所述第一晶体管的第一开窗区上，所述第二晶体管的上表面包括通过绝缘层隔离的第一开窗区和第二开窗区，下表面包括与所述第一晶体管的源电极电连接的漏电极，所述第二晶体管的第一开窗区中包括所述第二晶体管的源电极，所述第二晶体管的第二开窗区中包括所述第二晶体管的栅电极，a second transistor, arranged on the first window region of the first transistor, wherein the upper surface of the second transistor includes the first window region and the second window region isolated by the insulating layer, and the lower surface includes a drain electrode electrically connected to the source electrode of the first transistor, the first window region of the second transistor includes the source electrode of the second transistor, and the second window region of the second transistor includes the gate electrode of the second transistor, 所述第一晶体管和所述第二晶体管均为纵向双扩散金属氧化物场效应管。The first transistor and the second transistor are both vertical double diffused metal oxide field effect transistors.
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