CN112737532B - A Variable Gain Amplifier with High Gain Precision and Low Additional Phase Shift - Google Patents

Abstract

The invention belongs to the technical field of wireless communication, and specifically provides a novel variable gain amplifier with high gain precision and low additional phase shift, which is used to solve the problem of large additional phase shift in the high gain state of traditional variable gain amplifiers and high DAC in high gain precision. The question of number of digits required. The present invention introduces the asymmetric capacitor technology on the basis of the differential circuit structure. On the one hand, it can effectively solve the problem of large phase changes in the high-gain state caused by the different parasitic capacitances of the two differential circuits under different biases; on the other hand, the technology also It has the function of gain precision adjustment, only needs to reasonably configure the size of the asymmetric capacitor, and can achieve high gain precision control without increasing the number of DAC bits. To sum up, compared with the traditional variable gain amplifier structure, the present invention realizes lower additional phase shift under high gain state and high gain precision control under the same DAC bit number.

Description

A Variable Gain Amplifier with High Gain Precision and Low Additional Phase Shift

technical field

The invention belongs to the technical field of wireless communication, relates to a variable gain amplifier in a transceiver of a wireless communication system, and specifically provides a novel variable gain amplifier with high gain precision and low additional phase shift.

Background technique

In the wireless communication system receiver, due to the different distances between different regions and wireless communication equipment, the transmission process is affected by noise, loss, etc. differently, causing the receiving equipment to amplify different powers according to different received signals. In the wireless communication system transmitter, in order to better suppress the side lobe and transmit higher signal quality, it is necessary to adjust the gain of each channel; thus, the variable gain amplifier (VGA) came into being, in the wireless communication The transceiver plays a vital role in the front end of the system.

With the continuous development of communication systems, people have put forward requirements for miniaturization, portability and high performance of communication systems. In order to meet these requirements, integrated circuits have emerged in response to the situation. Among the existing integrated circuit manufacturing technologies, silicon-based technology has attracted much attention because of its low cost, low power consumption and increasing speed. Silicon-based technology includes SiGe and CMOS. At present, most VGA designs use SiGe technology. On the basis of SiGe technology, more high-gain precision and low additional phase shift technologies have been proposed. For example, in 2016, based on the SiGe process, F.Padovan et al. used the zero-pole compensation method to realize the low additional phase shift of VGA (F.Padovan, M.Tiebout, A.Neviani and A.Bevilacqua,"A 15.5– 39GHzBiCMOS VGA with phase shift compensation for 5G mobilecommunicationtransceivers,"ESSCIRC Conference 2016:42 ^nd European Solid-State CircuitsConference, Lausanne, 2016, pp.363-366); in 2017, B. Sadhu et al. Based on SiGe process, using local feedback The method realizes low additional phase shift of VGA (B.Sadhu et al., "A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and GainControl for 5G Communications," in IEEE Journal of Solid- State Circuits, vol.52, no.12, pp.3373-3391, Dec.2017). Since the manufacturing cost of the SiGe process is higher than that of the CMOS process, in order to achieve lower manufacturing costs, it is very important to develop VGAs with high gain accuracy and low phase variation based on the CMOS process; however, since the SiGe process is based on heterojunction bipolar transistors ( HBT) achieves dB linear control, while the CMOS process is based on metal-oxide semiconductor field effect transistors (MOSFETs) to achieve dB linear control, and the working principles of HBT and MOSFET are different, so the high gain accuracy and low phase based on SiGe process Variation techniques are not applicable in CMOS processes.

In 2019, Dr. Wu Tianjun from University of Electronic Science and Technology of China proposed a VGA design with low additional phase shift based on CMOS technology (T.Wu, C.Zhao, H.Liu, Y.Wu, Y.Yu and K.Kang,"A 20～43GHz VGA with 21.5dB GainTuning Range and Low Phase Variation for 5G Communications in 65-nm CMOS,"2019IEEE Radio Frequency Integrated Circuits Symposium(RFIC), Boston, MA, USA, 2019, pp.71-74.); the The design scheme adopts parasitic capacitance elimination and layout isolation enhancement technology to realize low additional phase shift. During the VGA gain change process, the main reason for the phase change is the parasitic capacitance, so eliminating the influence of the parasitic capacitance is the most effective way to achieve low additional phase shift of the VGA. As shown in Figure 7(a), this scheme uses a differential common-source circuit structure to achieve low additional phase shift of the VGA, and Figure 7(b) shows the small-signal equivalent model of the differential common-source circuit, from which we can It can be seen that due to the adoption of the differential structure, the current flow directions (I ₁ , I ₂ ) of the parasitic capacitances of the two transistors are opposite, thereby realizing the cancellation of the parasitic capacitances and further realizing low additional phase shift. However, this scheme cannot completely offset the parasitic capacitance, because the magnitude of the parasitic capacitance of the transistor is different under different biases; therefore, although this scheme reduces the phase change caused by the parasitic capacitance to a certain extent, it cannot It is completely eliminated, so that VGA still has a certain additional phase shift during the gain change process; especially in the high gain state, due to the large difference in the bias of the two transistors, the parasitic capacitance of the two transistors also differs greatly, the above scheme Only a small part of the parasitic capacitance can be canceled out, causing the phase of the VGA to vary greatly at high gain. Further, in order to achieve low additional phase shift, this solution utilizes the parasitic capacitor cancellation technique on the one hand, and sacrifices gain for lower additional phase shift on the other hand. In addition, the gain control of this scheme relies on external manual voltage adjustment, and there is no integrated digital-to-analog converter (DAC) control module, so this scheme cannot achieve high-precision gain control of VGA; and for the scheme of using DAC to realize VGA gain control Generally, the number of control bits of the DAC is increased to achieve high-gain precision control, but due to the increase of the number of DAC bits, the design difficulty, cost and power consumption also increase significantly.

To sum up, the existing variable gain amplifier (VGA) designed based on CMOS technology, on the one hand, has low gain control accuracy. The increase in the number of DAC digits has greatly increased the design difficulty, cost and power consumption; on the other hand, the additional phase shift caused by the VGA gain change process is large, and the low additional phase shift technology currently used is generally on the basis of sacrificing the gain. realized above. Therefore, it is the problem to be solved by the present invention to realize high gain precision control and low additional phase shift without increasing the number of DAC bits and without sacrificing the gain of the VGA designed based on the CMOS process.

Contents of the invention

The object of the present invention is to provide a novel variable gain amplifier with high gain precision and low additional phase shift to solve the above technical problems. In the variable gain amplifier structure of the present invention, the asymmetric capacitor technology is firstly introduced on the basis of the differential circuit structure; secondly, the on-chip DAC control circuit is matched to realize high-gain precision control; moreover, the introduction of the asymmetric capacitor technology On the one hand, it can effectively solve the problem of large phase changes in the high-gain state caused by the different parasitic capacitances of the two differential circuits under different biases; on the other hand, this technology also has the function of gain precision adjustment, and only needs to reasonably configure the size of the asymmetric capacitor , can achieve high-gain precision control without increasing the number of DAC bits; thus, the VGA under the CMOS process is based on asymmetric capacitor technology, which perfectly solves the problem of large additional phase shift in high-gain state and high DAC in high-gain precision. The question of number of digits required.

To achieve the above object, the technical solution adopted in the present invention is:

A novel variable gain amplifier with high gain accuracy and low additional phase shift, comprising: 4 transistors M1-M4, 2 matching capacitors C1, and two matching capacitors C2; it is characterized in that the variable gain amplifier adopts a differential structure , the differential input signal Vin+ is input to the gate of the transistor M1 after passing through the matching capacitor C1, the differential input signal Vin+ is input to the gate of the transistor M2 after passing through the matching capacitor C2, and the differential input signal Vin- is input to the gate of the transistor M3 after passing through the matching capacitor C2, The differential input signal Vin- is input to the gate of the transistor M4 after passing through the matching capacitor C1, the drain of the transistor M1 is connected to the drain of the transistor M3, and outputs a signal Vout+, the drain of the transistor M2 is connected to the drain of the transistor M4 connected and output signal Vout-, the sources of transistors M1-M4 are all grounded; the gates of transistor M1 and transistor M4 are connected in series with a bias resistor to control voltage V _a , and the gates of transistor M2 and transistor M3 are connected in series The control voltage V _b is connected after the bias resistor; the transistors M1 - M4 are of the same size, and the capacitance of the matching capacitor C1 is smaller than that of the matching capacitor C2 .

Further, the capacitance of the matching capacitor C2 is ≥1 pF, and the capacitance of the matching capacitor C1 is ≥200 fF.

Further, the matching capacitor C1 adopts a flat capacitor structure to reduce capacitance deviation caused by processing errors; the matching capacitor C2 adopts an interdigital capacitor structure to save chip area.

The beneficial effects of the present invention are:

The present invention provides a novel variable gain amplifier with high gain precision and low additional phase shift, which introduces asymmetric capacitor technology on the basis of differential circuit structure, that is, the capacitance of matching capacitor C1 is smaller than that of matching capacitor C2; the asymmetric capacitor The technology compensates for the unbalance problem caused by the different biases of the two channels in the differential structure. It only needs to reasonably configure the capacitance values of the asymmetrical capacitors C1 and C2 under the premise that the capacitance of the matching capacitor C1 is smaller than that of the matching capacitor C2. The size can completely compensate for the unbalance problem caused by the two differential channels under different biases, so that the parasitic capacitance of the two differential channels can be offset more thoroughly, thereby realizing a variable gain amplifier (VGA) with low additional phase shift in a high gain state. design;

On the other hand, since the asymmetric capacitance belongs to the matching capacitance of each channel, different capacitance values cause different impedance matching, and different impedance matching will cause the gain of the transistor to change, so by satisfying the capacitance of the matching capacitor C1 less than On the premise of matching the capacitance of capacitor C2, rationally configuring the capacitance of the asymmetric capacitor can also realize the gain control of the VGA, so as to achieve higher gain precision control by using asymmetric capacitor technology without increasing the number of DAC bits. . To sum up, the present invention only needs to reasonably configure the capacitance values of C1 and C2, which is equivalent to achieving lower additional phase shift and higher gain precision control;

In summary, compared with the traditional VGA design, the present invention realizes lower additional phase shift under high gain state and high gain precision control under the same DAC bit number; it perfectly solves the problem of traditional variable gain amplifier at high In the gain state, the additional phase shift is large and the high gain precision requires a high number of DAC digits.

Description of drawings

Fig. 1 is the structural representation of the variable gain amplifier of novel high gain precision low additional phase shift of the present invention,

FIG. 2 is a schematic diagram of the overall control circuit of the on-chip DAC in the embodiment of the present invention.

FIG. 3 is a curve showing the relationship between the capacitance value C1 and the circuit stability in the embodiment of the present invention.

FIG. 4 is a simulation result of a variable gain amplifier based on a symmetrical capacitor in an embodiment of the present invention, where (a) is the gain under different states, and (b) is the phase change under different gains.

FIG. 5 is a simulation result of a variable gain amplifier based on an asymmetric capacitor in an embodiment of the present invention, where (a) is the gain under different states, and (b) is the phase change under different gains.

FIG. 6 is a layout diagram of a variable gain amplifier based on an asymmetric capacitor in an embodiment of the present invention.

Fig. 7 is a schematic structural diagram of an existing differential common-source variable gain amplifier, wherein (a) is a simplified circuit schematic diagram, and (b) is a small-signal equivalent circuit model.

detailed description

The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

This embodiment provides a novel variable gain amplifier (VGA) with high gain precision and low additional phase shift. The variable gain amplifier is based on CMOS technology, and uses asymmetric capacitors and on-chip integrated DAC technology to achieve low VGA in high gain state. Additional phase shift, high gain precision control with low DAC bits. The schematic diagram of the VGA circuit based on the asymmetric capacitor technology and the schematic diagram of the overall control circuit of the DAC on the chip are as shown in Figure 1:

It can be seen from FIG. 1 that the VGA proposed in this embodiment includes: four transistors M1 to M4, two matching capacitors C1 and C2, and two control voltages V _a and V _b ; the circuit adopts a differential structure, and the differential input signal Vin+ After passing through the matching capacitor C1, it is input to the gate of transistor M1, the differential input signal Vin+ is input to the gate of transistor M2 after passing through the matching capacitor C2, the differential input signal Vin- is input to the gate of transistor M3 after passing through the matching capacitor C2, and the differential input signal Vin- After passing through the matching capacitor C1, it is input to the gate of the transistor M4, the drain of the transistor M1 is connected to the drain of the transistor M3, and outputs a signal Vout+, and the drain of the transistor M2 is connected to the drain of the transistor M4, and outputs a signal Vout-, the sources of transistors M1-M4 are all grounded; the gates of transistor M1 and transistor M4 are connected in series with a bias resistor to the control voltage V _a , and the gates of transistor M2 and transistor M3 are connected in series with a bias resistor control voltage V _b .

In this embodiment, in order to eliminate the phase change problem caused by the parasitic capacitance of the transistor, the VGA design based on the low additional phase shift of the CMOS process is realized; The parasitic capacitance difference between them; on the other hand, a differential structure is adopted, so that the parasitic capacitance currents of the two transistors flow in the opposite direction, realizing the cancellation of the parasitic capacitance, further reducing the parasitic capacitance of the transistor, and further reducing the additional phase shift of the VGA. Simultaneously, in order to solve the problem that the phase of VGA changes greatly under the high-gain state, the present invention proposes asymmetric capacitor technology, as shown in Figure 1, the matching capacitor C1 and C2 of differential two-way transistor are not equal to form an asymmetric capacitor structure; The asymmetrical capacitor compensates the unbalanced problem caused by the different biases of the two circuits in the differential structure. It only needs to reasonably configure the capacitance values of the asymmetrical capacitors C1 and C2 to completely compensate for the imbalance caused by the two differential circuits under different biases. Balance issues, so as to realize the VGA design with low additional phase shift in high gain state. For the capacitance configuration of capacitor C2, in order to better block the DC effect, generally take about 1pF; for the capacitance configuration of capacitor C1, on the one hand, it depends on the compensation effect of the imbalance problem caused by the difference in the two biases of the differential structure , a reasonable value of C1 will minimize the additional phase shift of the VGA under different gain states; on the other hand, it depends on the gain precision control requirements of the VGA, the higher the required gain precision, the greater the difference between C1 and C2; but , the value of C1 cannot be infinitely small, and the stability of the overall circuit must also be considered. As shown in Figure 3, when the value of C1 is less than 200fF, the entire circuit is unstable, and the value of C1 needs to be greater than 200fF; The capacitance configuration of symmetrical capacitors C1 and C2, C2 is about 1pF, the value of C1 minimizes the additional phase shift of VGA on the one hand, and ensures the stability of the circuit on the other hand.

In order to realize the high-gain precision control of VGA, this embodiment also provides a control circuit matching the above-mentioned variable gain amplifier (VGA), and integrates the DAC on the chip. The overall control circuit of the DAC is shown in Figure 2, including: built-in analog Current source bias circuit (to realize constant current source) and current mirror DAC circuit; the total current I _total of the current mirror is constant, and the PMOS current mirror DAC is controlled by switches, and different I _a and I _b are assigned to generate control voltages V _a and V _b correspondingly , so as to realize the gain control of the VGA; the constant current source Iref and the bias V _BIAS are implemented on-chip by using analog circuits. On the one hand, the asymmetric capacitor technology solves the above-mentioned unbalance problem of the two differential circuits under different biases. On the other hand, since the asymmetric capacitor belongs to the matching capacitor of each channel, different capacitance values cause different impedance matching. Different impedance matching will change the gain of the transistor, so by reasonably configuring the capacitance of the asymmetric capacitor, the gain control of the VGA can also be realized, so that the use of the asymmetric capacitor can be realized without increasing the number of DAC bits. technology for higher gain precision control.

The beneficial effects of the present invention are illustrated below in conjunction with simulation results:

Figure 4 shows the gain and phase simulation results of a traditional VGA designed with symmetrical capacitors (C1=C2=1pF). At 27GHz, the VGA achieves a maximum gain of 25.2dB, a maximum additional phase shift of 12.2°, and a gain accuracy of 0.5 dB; Gain and phase simulation results of the novel VGA designed for the asymmetric capacitor (C1=200fF, C2=1pF) provided by the present embodiment as shown in Figure 5, the novel VGA of the present embodiment adopts the same circuit structure as the traditional VGA and the same transistor size, also at 27GHz, the novel VGA of the present invention has achieved the highest gain of 25.5dB, and the maximum additional phase shift is only 4.3°, which is 65% lower than the additional phase shift of traditional VGA; under the same DAC control digit , achieving a gain accuracy of 0.2dB, which is 60% higher than that of traditional VGAs.

In summary, compared with the traditional VGA design based on symmetrical capacitors, the new VGA proposed by the present invention based on asymmetric capacitor technology achieves a higher performance in a high-gain state without increasing any design complexity and cost. Low additional phase shift, higher gain precision control without increasing the number of DAC bits, perfectly solves the problem of large additional phase shift in high gain state and high DAC bit number requirement under high gain accuracy.

As shown in Figure 6, the layout of the new high-gain precision low additional phase shift VGA provided by this embodiment, wherein, the M3 layer and the M4 layer are used as ground planes; the gate and drain electrodes of the transistor are respectively punched to the M9 layer through via holes , wherein, the gate is drawn out with M8 layer metal, and the drain is drawn out with M9 layer metal; the capacitance of capacitor C1 is small, and a flat capacitor structure is adopted in order to reduce the capacitance deviation caused by processing errors; the capacitance of capacitor C2 is large, in order to Save the chip area by adopting interdigitated capacitor structure.

The above is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless specifically stated, can be replaced by other equivalent or alternative features with similar purposes; all the disclosed features, or All method or process steps may be combined in any way, except for mutually exclusive features and/or steps.

Claims (4)

1. A high gain precision low additional phase shifted variable gain amplifier comprising: 4 transistors M1-M4, 2 matching capacitors C1 and 2 matching capacitors C2; the differential input signal Vin + passes through a matching capacitor C1 and then is input into a grid electrode of a transistor M1, the differential input signal Vin + passes through a matching capacitor C2 and then is input into a grid electrode of a transistor M2, the differential input signal Vin-passes through a matching capacitor C2 and then is input into a grid electrode of a transistor M3, the differential input signal Vin-passes through a matching capacitor C1 and then is input into a grid electrode of a transistor M4, a drain electrode of the transistor M1 is connected with a drain electrode of the transistor M3 and outputs a signal Vout +, a drain electrode of the transistor M2 is connected with a drain electrode of the transistor M4 and outputs a signal Vout-, and source electrodes of the transistors M1-M4 are all grounded; the gates of the transistors M1 and M4 are connected in series with a bias resistor and then connected with a control voltage V _a The gates of the transistors M2 and M3 are connected in series with a bias resistor and then connected with a control voltage V _b (ii) a And the capacitance value of the matching capacitor C1 is smaller than that of the matching capacitor C2.

2. The variable gain amplifier of claim 1 wherein said transistors M1-M4 are of equal size.

3. The variable gain amplifier of claim 1, wherein said matching capacitor C2 has a capacitance of 1pF or more, and said matching capacitor C1 has a capacitance of 200fF or more.

4. The high gain precision low additive phase shift variable gain amplifier of claim 1 wherein said matching capacitor C1 is a plate capacitor structure and said matching capacitor C2 is an interdigital capacitor structure.

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