CN112703600A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN112703600A CN112703600A CN201880095908.1A CN201880095908A CN112703600A CN 112703600 A CN112703600 A CN 112703600A CN 201880095908 A CN201880095908 A CN 201880095908A CN 112703600 A CN112703600 A CN 112703600A
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
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Abstract
一种阵列基板(100)、显示面板(200)及显示装置。阵列基板(100)包括:基底(10)，具有显示区域(101)和非显示区域(102)；多条栅极线(211)，设置于显示区域(101)；多条数据线(23)，设置于显示区域(101)；以及电传输层(20)，设置于显示区域(20)，其包括多条栅极引导线(21)，多条栅极引导线(21)分别与多条栅极线(211)电连接，多条栅极引导线(211)与多条数据线(23)均从显示区域(101)的同一侧引出以与外部控制电路(60)电连接。由于多条栅极引导线(21)、多条数据线(23)从显示区域(101)的同一侧引出至非显示区域(102)，并与外部控制电路(60)电连接，从而减少阵列基板(100)两侧边的排线面积。
An array substrate (100), a display panel (200), and a display device are disclosed. The array substrate (100) includes: a substrate (10) having a display area (101) and a non-display area (102); a plurality of gate lines (211) disposed in the display area (101); a plurality of data lines (23) disposed in the display area (101); and an electrical transport layer (20) disposed in the display area (20), which includes a plurality of gate guide lines (21), the plurality of gate guide lines (21) being electrically connected to the plurality of gate lines (211) respectively, and the plurality of gate guide lines (211) and the plurality of data lines (23) being led out from the same side of the display area (101) to be electrically connected to an external control circuit (60). Since multiple gate guide lines (21) and multiple data lines (23) are led out from the same side of the display area (101) to the non-display area (102) and electrically connected to the external control circuit (60), the wiring area on both sides of the array substrate (100) is reduced.
Description
The present application relates to the field of display technologies, and in particular, to an array substrate, a display panel using the array substrate, and a display device.
In an Organic Light-Emitting Diode (OLED) display technology, a Thin Film Transistor (TFT) may be used to drive and control an Organic Light-Emitting layer in an OLED display panel, so as to implement Light-Emitting display. When the thin film transistor is driven and controlled, the data line, the gate line and the power line are required to provide electric signal support for the thin film transistor. In addition, when the thin film transistor is used for driving control, other auxiliary circuit structures, such as a logic control circuit structure, a chip on film structure, etc., are also required. However, the connection of these circuit structures to the thin film transistor results in complicated arrangement of the connecting conductive wires of the display panel, and increases the layout area, which is not favorable for the narrow and small design of the frame of the display panel.
Disclosure of Invention
In view of this, the present application provides an array substrate, and a display panel and a display device using the same, which are intended to improve the arrangement structure of the connecting electrical wires of the array substrate, so as to facilitate the design of narrowing the frame of the display panel.
To this end, the present application provides an array substrate, including:
a substrate having a display area and a non-display area located outside the display area;
a plurality of gate lines disposed in the display region and spaced in rows;
the data lines are arranged in the display area at intervals and are arranged in rows, the data lines are not intersected with the gate lines vertically, and the gate lines and the data lines define the display area together; and
and an electrical transmission layer disposed in the display region, the electrical transmission layer including a plurality of gate guide lines electrically connected to the plurality of gate lines, respectively, such that the plurality of gate lines are electrically connected to an external control circuit through the plurality of gate guide lines, and the plurality of gate guide lines and the plurality of data lines are led out from the same side of the display region to the non-display region to be electrically connected to the external control circuit.
Optionally, the array substrate further includes a plurality of power lines disposed in the display area, the electrical transmission layer further includes a power guide line for electrically connecting the power lines to the external control circuit, and the power guide line is disposed in the display area and led out from the same side of the display area as the plurality of gate guide lines and the plurality of data lines to be electrically connected to the external control circuit.
Optionally, the power supply guide line is arranged in a grid.
Optionally, the power supply guide line includes two portions, a portion of the power supply guide line located in a region where the gate guide line is not located is in a grid shape, and a portion of the power supply guide line located in a region where the gate guide line is located is in a strip shape.
Optionally, the plurality of gate guide lines are distributed at intervals in a strip structure, and the plurality of gate guide lines are parallel to the plurality of data lines and are not coplanar.
Optionally, the plurality of gate guide lines are not uniformly long and short, and the long gate guide lines are wider than the short gate guide lines.
Optionally, the plurality of gate guide lines are arranged in sequence according to the length order.
Optionally, the plurality of gate guide lines are shortest and located in the center of the display area, and the gate guide lines arranged from the center of the display area to both sides are longer and longer.
Optionally, the display device further includes a plurality of thin film transistor units and a plurality of power lines, the plurality of thin film transistor units are arranged in the display area in a matrix, an area surrounded by two adjacent gate lines and two adjacent data lines defines a pixel unit, each thin film transistor unit is correspondingly located in one pixel unit, and each thin film transistor unit is electrically connected to a corresponding gate line, a corresponding data line and a corresponding power line.
Optionally, the substrate further comprises a first insulating layer, the electrical transmission layer is formed on the surface of the substrate, the first insulating layer is formed on one side of the electrical transmission layer away from the substrate, and the plurality of thin film transistor units are formed on one side of the first insulating layer away from the electrical transmission layer, so that the first insulating layer insulates the electrical transmission layer and the plurality of thin film transistor units from each other.
Optionally, each of the thin film transistor units includes a first transistor and a second transistor; the grid electrode of each first transistor is electrically connected with an adjacent grid line, the source electrode of each first transistor is electrically connected with an adjacent data line, and the drain electrode of each first transistor is electrically connected with the grid electrode of the second transistor in the same thin film transistor unit; the source electrode of each second transistor is electrically connected with one power line, and the drain electrode of each second transistor is used for being connected with one organic light-emitting unit.
Optionally, the device further comprises a second insulating layer, a third insulating layer and a protective layer, the gate of the first transistor and the gate of the second transistor are isolated from each other and disposed on a side of the first insulating layer away from the electrical transmission layer, the second insulating layer covers the gate of the first transistor, the gate of the second transistor and a side of the first insulating layer away from the substrate, the channel layer of the first transistor and the channel layer of the second transistor are isolated from each other and disposed on a side of the second insulating layer away from the substrate, the third insulating layer covers the channel layer of the first transistor, the channel layer of the second transistor and a side of the second insulating layer away from the substrate, the source and the drain of the first transistor and the source and the drain of the second transistor are formed on a side of the third insulating layer away from the substrate at intervals, the protective layer covers the source electrode and the drain electrode of the first transistor and one side, far away from the substrate, of the source electrode and the drain electrode of the second transistor.
Optionally, the non-display area includes two portions respectively located at two opposite sides of the display area, two sides of the display area where the non-display area is located are both perpendicular to the extending direction of the data lines and are parallel to the extending direction of the gate lines, and the plurality of gate lead lines and the plurality of data lines are both led out from the non-display area at one side to be electrically connected to the external control circuit.
Optionally, the display device further includes an electrostatic discharge structure disposed in the non-display region on a side opposite to a direction in which the plurality of gate guide lines and the plurality of data lines are drawn, the electrostatic discharge structure being connected to the electrical transport layer to discharge static electricity.
In the technical scheme of the application, the array substrate is arranged by changing the connecting electric leads of the array substrate, the grid guide lines and the data lines are all led out from the same side of the display area to the non-display area so as to be electrically connected with an external control circuit, and therefore the flat cable area on two side edges of the array substrate is reduced, and the narrow and small design of a frame of the display panel is facilitated.
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the structures shown in the drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic view of a portion of the structure of the cross-section of FIG. 1;
fig. 3 is a schematic circuit structure diagram of the thin film transistor unit in fig. 2;
FIG. 4 is a schematic layout of a gate lead according to an embodiment of the present application;
fig. 5 is a schematic layout diagram of a data line according to an embodiment of the present application.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. If in the embodiments of the present application there is a description referring to "first", "second", etc., the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
It is to be understood that, as shown herein, the positional relationship between one or more layers of the substance involved in the embodiments of the present application, such as the terms "stacked" or "formed" or "applied" or "disposed", is expressed using terms such as: any terms such as "stacked" or "formed" or "applied" may cover all manner, kinds and techniques of "stacked". For example, sputtering, plating, molding, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation, Hybrid Physical-Chemical Vapor Deposition (HPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and the like.
The embodiment of the application provides an array substrate, and a display panel and a display device using the array substrate, wherein the array substrate comprises:
a substrate having a display area and a non-display area located outside the display area;
a plurality of gate lines disposed in the display region and spaced in rows;
the data lines are arranged in the display area at intervals and are arranged in rows, the data lines are not intersected with the gate lines vertically, and the gate lines and the data lines define the display area together; and
and an electrical transmission layer disposed in the display region, the electrical transmission layer including a plurality of gate guide lines electrically connected to the plurality of gate lines, respectively, such that the plurality of gate lines are electrically connected to an external control circuit through the plurality of gate guide lines, and the plurality of gate guide lines and the plurality of data lines are led out from the same side of the display region to the non-display region to be electrically connected to the external control circuit.
In order to make the technical solutions of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
Referring to fig. 1 to 5, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure; FIG. 2 is a schematic view of a portion of the structure of the cross-section of FIG. 1; fig. 3 is a schematic circuit structure diagram of the thin film transistor unit in fig. 2; FIG. 4 is a schematic layout of a gate lead according to an embodiment of the present application; fig. 5 is a schematic layout diagram of a data line according to an embodiment of the present application.
Referring to fig. 1 to 3, an embodiment of the present disclosure provides an array substrate 100, which can be applied to a display panel 200, preferably an OLED display panel. The array substrate 100 has a display region 101 and a non-display region 102 on at least one side of the display region 101.
The array substrate 100 further includes a base 10, and an electrical transmission layer 20, a plurality of thin film transistor units 30, a plurality of gate lines 211, a plurality of data lines 23, and a plurality of power lines 221 formed on the base 10, wherein the electrical transmission layer 20, the plurality of thin film transistor units 30, the plurality of gate lines 211, the plurality of data lines 23, and the plurality of power lines 221 are correspondingly located in the display region 101.
In this embodiment, the non-display area 102 includes two portions respectively located at two opposite sides of the display area 101. It should be noted that fig. 2 shows a schematic cross-sectional structure of only one tft unit 30.
As shown in fig. 2, the display panel 200 includes a plurality of organic light emitting units 1. The thin film transistor units 30 can be used to drive and control the plurality of organic light emitting units 1 in the display panel 200 to realize light emitting display, wherein each thin film transistor unit 30 corresponds to one organic light emitting unit 1.
In some embodiments, the organic light emitting unit 1 includes a cathode, an organic light emitting layer, and an anode, which are stacked. The organic light emitting layer is disposed between the cathode and the anode, and when a working voltage is applied between the cathode and the anode, the organic light emitting layer is excited to emit light, so that light emission display can be realized, wherein the thin film transistor unit 30 is electrically connected to the anode, so that the organic light emitting unit 1 can be driven and controlled. It will be appreciated that the organic light-emitting unit 1 may still have more functional layer structures to achieve better light-emitting effect.
Optionally, the plurality of organic light emitting units 1 include one or more of a red light emitting unit, a blue light emitting unit, and a green light emitting unit. It is understood that when each of the thin film transistor units 30 is connected to one of the red light emitting unit, the blue light emitting unit, or the green light emitting unit, the organic light emitting unit 1 can be caused to emit light in a single color.
As shown in fig. 2 and 3, the electrical transmission layer 20 includes a plurality of gate guide lines 21 and a plurality of power guide lines 22, which are insulated and isolated from each other, and the plurality of gate guide lines 21 are parallel to and non-coplanar with the plurality of data lines 23. Each of the gate lines 21 is connected to one of the gate lines 211, and each of the power lines 22 is connected to one of the power lines 221. In this embodiment, the substrate 10 is made of an electrically insulating material to encapsulate and protect the electrical transmission layer 20, so as to prevent the electrical transmission layer 20 from being electrically connected to other external cables.
The gate lines 211 are arranged in rows at intervals, the data lines 23 are arranged in columns at intervals and do not intersect with the gate lines 211 perpendicularly, an area enclosed by two adjacent gate lines 211 and two adjacent data lines 23 defines a pixel unit, each pixel unit corresponds to one thin film transistor unit 30 and one organic light emitting unit 1, and the pixel units are arranged in rows and columns to define a display area of the display panel 200, namely the display area 101 of the array substrate 100.
The plurality of power lines 221 are disposed in parallel to the plurality of gate lines 211 at intervals or in parallel to the plurality of data lines 23 at intervals. In this embodiment, the plurality of power lines 221 are spaced apart from and parallel to the plurality of gate lines 211. In some embodiments, both sides of the display panel 200 where the non-display area 102 is located are perpendicular to the direction in which the data lines 23 extend, and are parallel to the direction in which the gate lines 211 extend.
Referring to fig. 4, the gate guide lines 21 and the power guide lines 22 are electrically connected to an external control circuit (not shown), so that the gate lines 211, the power lines 221, and the data lines 23 are electrically connected to the external control circuit of the non-display region 102 on one side of the display region 101, and the thin film transistor unit 30 is controlled by the external control circuit. In some embodiments, an outer lead connection region 60 is provided in the non-display region 102 for connecting the plurality of gate guide lines 21, the plurality of power guide lines 22 and the plurality of data lines 23 to the external control circuit. That is to say, each gate line 211, each power line 221, and each data line 23 are led out from one side of the array substrate 100 to be connected to the external control circuit, and compared to the prior art in which the gate line 211, the power line 221, and the data line 23 are led out from two sides or more than two sides of the array substrate 100, the present invention can reduce the area of the flat cable at the two sides of the array substrate 100, so as to facilitate the design of narrowing the frame of the display panel 200. It should be noted that the external control circuit is, for example, a driver IC, and may be directly disposed in the non-display region, or may be disposed in the non-display region through a flexible circuit board instead of being directly disposed in the non-display region.
The thin film transistor units 30 are disposed on the electrical transmission layer 20, and provide operating current and/or operating voltage to the thin film transistor units 30 through the electrical transmission layer 20, so that the thin film transistor units 30 can operate normally. It is understood that the thin film transistor unit 30 may be manufactured by sputtering, evaporation, vapor deposition, etching, etc. so that the thin film transistor unit 30 is disposed on the electrical transmission layer 20.
With reference to fig. 2, each of the tft units 30 includes a first transistor 31 and a second transistor 32, a gate of each of the first transistors 31 is electrically connected to an adjacent gate line 211, and a source of each of the first transistors 31 is electrically connected to an adjacent data line 23. All the data lines 23 are electrically connected to an external control circuit of the non-display region 102 at one side thereof. The source of the second transistor 32 in the same row is electrically connected to an adjacent one of the power lines 221.
Further, the first transistor 31 includes a first gate 311, a first semiconductor 312 corresponding to the first gate 311, and a first source 313 and a first drain 314 respectively contacting two opposite sides of the first semiconductor 312. It is understood that the first gate 311 corresponds to the first semiconductor 312. The first gate 311 is a gate of the first transistor 31, the first source 313 and the first drain 314 are a source and a drain of the first transistor 31, respectively, and the first semiconductor 312 is a channel layer of the first transistor 31.
Similarly, the second transistor 32 includes a second gate 321, a second semiconductor 322 corresponding to the second gate 321, and a second source 323 and a second drain 324 respectively contacting two opposite sides of the second semiconductor 322. The second gate 321 corresponds to the second semiconductor 322 in position, the second gate 321 is the gate of the second transistor 32, the second source 323 and the second drain 324 are the source and the drain of the second transistor 32, respectively, and the second semiconductor 322 is the channel layer of the second transistor 32.
The gate of the second transistor 32 is electrically connected to the drain of the first transistor 31, and the first transistor 31 and the second transistor 32 are electrically connected in parallel. The gate guide line 21 of the electrical transmission layer 20 is electrically connected to the gate of the first transistor 31 through the gate line 211, and the power guide line 22 is electrically connected to the source of the second transistor 32 through the power line 221, so as to provide the thin film transistor unit 30 with an operating current and/or an operating voltage. It is understood that the source of the first transistor 31 is externally connected to a data signal current and/or voltage through the data line 23, and the drain of the second transistor 32 is electrically connected to the organic light emitting unit 1, that is, the thin film transistor unit 30 can drive and control the organic light emitting unit 1 to implement light emitting display.
Specifically, as shown in fig. 3, the present embodiment provides a schematic circuit structure diagram of the thin film transistor unit 30. The gate guide lines 21 and the power guide lines 22 of the electrical transmission layer 20 provide operating current and/or operating voltage for the thin film transistor unit 30, and the source of the first transistor 31 provides data signal current and/or voltage for the thin film transistor unit 30 through the data line 23.
The first transistor 31 and the second transistor 32 are organically connected to form the thin film transistor unit 30, and are commonly disposed on the same layer structure, for example, on the electrical transmission layer 20. This structure can conveniently provide power support for the thin film transistor unit 30 and provide a stable and consistent operating current and/or operating voltage to obtain a stable control signal, thereby improving the stability of the product. Simultaneously, the gate guide line 21, the power guide line 22 and the data line 23 for providing the thin film transistor unit 30 with the working current and/or the working voltage are all led out from one side of the array substrate 100 to be electrically connected with the external control circuit, thereby facilitating the design of narrowing the frame of the display panel 200.
Referring to fig. 2, the array substrate 100 further includes a first insulating layer 41, a second insulating layer 42, a third insulating layer 43, a passivation layer 44 and a planarization layer 45. The electrical transmission layer 20 is formed on the substrate 10, the first insulating layer 41 is formed on the electrical transmission layer 20, the first gate 311 and the second gate 321 are separately disposed on the first insulating layer 41, and the electrical transmission layer 20 is insulated from the first gate 311 and the second gate 321 by the first insulating layer 41. The second insulating layer 42 covers the first gate 311, the second gate 321, and the first insulating layer 41, and the first semiconductor 312 and the second semiconductor 322 are isolated from each other and disposed on the second insulating layer 42. The first gate 311 corresponds to the first semiconductor 312, and the second gate 321 corresponds to the second semiconductor 322.
In this embodiment, the electrical connection between the layers is performed by using a via hole between the layers, for example, the electrical connection between the first gate 311 and the gate guide line 21 is performed by a via hole 411, and the via hole 411 penetrates through the first insulating layer 41 and is used for performing the electrical connection between the first gate 311 and the gate guide line 21.
The third insulating layer 43 is formed on the first semiconductor 312 and the second semiconductor 322, and covers the second insulating layer 42. The third insulating layer 43 fixes and encapsulates the first semiconductor 312 and the second semiconductor 322 to protect the first semiconductor 312 and the second semiconductor 322.
Further, the first source 313, the first drain 314, the second source 323, and the second drain 324 are formed on the third insulating layer 43 at intervals, and the first source 313, the first drain 314, the second source 323, and the second drain 324 may be formed by simultaneously patterning the same conductive material, such as aluminum, silver, gold, or an alloy thereof. The first source 313 and the first drain 314 are correspondingly located on two opposite sides of the first semiconductor 312, and are respectively in contact with the first semiconductor 312 through a via 431 and a via 432 penetrating through the third insulating layer 43. Alternatively, one end of the first drain 314 is in contact with the first semiconductor 312, and the other end is electrically connected to the gate of the second transistor 32, i.e., the second gate 321. The first drain electrode 314 is electrically connected to the second gate electrode 321 through a via 3141 penetrating through the third insulating layer 43 and the second insulating layer 42.
The second source electrode 323 and the second drain electrode 324 are correspondingly located at two opposite sides of the second semiconductor 322 and are electrically connected to the second semiconductor 322 through a via 433 and a via 434 penetrating through the third insulating layer 43, respectively. The power line 221 and the second source electrode 323 are disposed on the same layer and electrically connected, wherein the power line 221 is electrically connected to the power guide line 22 through a via 2211. In the present embodiment, a storage capacitor C (as shown in fig. 2) is formed between the first drain 314 and the second drain 324, so as to provide a stable operating current and/or operating voltage for the second transistor 32.
Further, the protection layer 44 is formed on the data line 23, the first source electrode 313, the first drain electrode 314, the second source electrode 323, the second drain electrode 324, the power line 221, and the third insulating layer 43 for packaging protection. The planarization layer 45 is formed on the protection layer 44 to form a flat plane. Optionally, a common electrode 50 is formed on the planarization layer 45, the common electrode 50 is electrically connected to the drain of the second transistor 32 through a via 51, wherein the anode of the organic light emitting unit 1 is electrically connected to the common electrode 50, so that the thin film transistor unit 30 is electrically connected to the organic light emitting unit 1.
It is understood that the electrical connection between layers can be achieved by using vias between layers to make electrical connection, and filling metal conductive material in the vias penetrating through the insulating layer, for example, the metal filling in the vias and the corresponding metal conductive layer above the vias are made of the same metal material. Of course, in some embodiments, the electrical connections between layers may also be made using connection bank wiring.
In some embodiments, the electrical transport layer 20 provides power support to the thin film transistor cells 30 through vias between layers. The thin film transistor units 30 are disposed on the electrical transmission layer 20 in an array to correspond to the organic light emitting units 1 of the driving control display panel 200, wherein the organic light emitting units 1 define a display area forming the display panel 200.
In some embodiments, the gate lead 21 and the power lead 22 are isolated and cooperate to form a layered structure. It is understood that the electrical transmission layer 20 may be prepared by sputtering, evaporation, vapor deposition, etching, and the like. Optionally, the gate guide lines 21 are strip-shaped structures that are spaced apart from each other, and the power guide lines 22 are connected to form a layered structure, for example, a power guiding layer is plated, and insulating trenches are etched on the power guiding layer and filled with an insulating material, that is, the insulating trenches surround the gate guide lines 21, so that the power guide lines 22 and the gate guide lines 21 are insulated. In a preferred embodiment, the gate guide line 21 and the power guide line 22 are patterned simultaneously with the same conductive layer.
Further, the power supply lead wire 22 is grid-layered. The power supply guide line 22 is arranged in a grid shape, which can save production materials and is beneficial to reducing internal stress of the power supply guide line 22. In particular, when the flexible display panel 200 is bent, the power guide lines 22 can be better bent with less stress generated inside, thereby enhancing the bending performance of the product.
In some embodiments, as shown in fig. 4, the electrical transmission layer 20 includes a plurality of the gate guide lines 21, and the gate guide lines 21 provide a gate operating current and/or an operating voltage for the corresponding one or more thin film transistor units 30. Each gate guide line 21 is electrically connected to one of the gate lines 211, and the gate lines 211 are connected to the external control circuit in the non-display region 102 through the gate guide lines 21.
Since the non-display region 102 of the present embodiment is located on the side of the display panel 200 parallel to the direction in which the gate lines 211 are arranged, distances between the plurality of gate lines 211 arranged in the display region 101 and the non-display region 102 are different, which results in the gate guide lines 21 being arranged in different lengths, and when the gate guide lines 21 are arranged in different lengths, the long gate guide lines 21 are wider than the short gate guide lines 21.
The plurality of gate guide lines 21 may be arranged in order of length from one side of the display region 101, and the plurality of gate guide lines 21 may be arranged in order of length from both sides of the display region 101. When the gate guide lines 21 are arranged in order of length from both sides of the display region 101, specifically, the shortest gate guide line 21 is located in the center of the display region 101, and the gate guide lines 21 arranged from the center to both sides are longer. At this time, the power supply guide line 22 includes two portions, a portion located in a region where the gate guide line 21 is not disposed is in a grid shape, and a portion located in a region where the gate guide line 21 is disposed is in a stripe shape. Wherein the power supply guide lines 22 of the strip portion are parallel to and spaced apart from the gate guide lines 21.
It is understood that when the gate guide lines 21 are of the same length, the gate guide lines 21 should be of the same width to ensure that the electrical signal is stable and consistent. When the gate guide lines 21 are arranged in different lengths, the long gate guide lines 21 are wider than the short gate guide lines 21 to ensure that the stable and consistent electrical signals can be provided. The long gate guide lines 21 can transmit electrical signals to other more distant regions of the display panel 200, but because the transmission distance is long and the impedance is relatively large, the gate guide lines 21 with a widened design are needed; the short gate guide lines 21 can transmit electrical signals to other closer regions of the display panel 200, but because the transmission distance is short and the impedance is relatively small, the gate guide lines 21 with a narrow and small design are required, so as to ensure that the gate guide lines 21 with different lengths can provide multiple paths of stable and consistent electrical signals, thereby ensuring the product stability. The grid guide line 21 is long and wide, so that the difficulty of the production process can be reduced, the production quality can be improved, the grid guide line 21 can provide stable and consistent electric signals, and the stability of the product can be guaranteed.
Referring to fig. 5, an embodiment of the present application provides a layout diagram of a source connection line of the first transistor 31, i.e., the data line 23. The source of the first transistor 31 in the tft unit 30 passes through the data line 23 to provide the tft unit 30 with a data electrical signal. The source of the first transistor 31 is connected to the external control circuit via a data line 23, thereby driving and controlling the thin film transistor unit 30. It is understood that the data line 23, the gate guide line 21 and the power guide line 22 are insulated from each other and are led out from the same side of the display panel 200 (i.e., the non-display region 102 on the side of the display region 101) to be electrically connected to the external control circuit. The gate lead 21 and the power lead 22 are disposed in the same layer and may be patterned from the same conductive material. The data line 23 may be disposed at the same layer as the first source electrode 313, and the data line 23, the first drain electrode 314, the second source electrode 323, and the second drain electrode 324 are simultaneously patterned from the same conductive material.
Further, the array substrate 100 further includes a chip on film structure (not shown). The COF structure is located in the non-display region 102 and electrically connected to the gate lead 21, the power lead 22, and the data line 23 of the first transistor 31.
The external control circuit is in communication connection with the flip-chip thin film structure, thereby logically controlling the thin film transistor unit 30. It should be understood that other IC chips may be connected to the chip on film structure to assist the external control circuit to logically control the thin film transistor unit 30, so that the organic light emitting unit 1 connected to the thin film transistor unit 30 can normally display light.
In some embodiments, the array substrate 100 further includes an electrostatic discharge structure 70 (fig. 1). The static electricity discharge structure 70 is connected to the electrical transmission layer 20 to discharge static electricity. The electrostatic discharge structure 70 is disposed in the non-display region 102 on the opposite side of the direction in which the plurality of gate guide lines 21 and the plurality of data lines 23 are drawn.
Based on the display panel 200, the embodiment of the present application further provides a display device. The display device includes the display panel 200. It is understood that the display device includes, but is not limited to, a display device such as a smart phone, a tablet computer, a PC-side computer, or a smart tv.
The embodiments described above are exemplary embodiments of the present application, but the embodiments of the present application are not limited to the embodiments described above, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present application should be regarded as equivalent substitutions and are included in the scope of the present application.
Claims (16)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/125720 WO2020133446A1 (en) | 2018-12-29 | 2018-12-29 | Array substrate, display panel, and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112703600A true CN112703600A (en) | 2021-04-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880095908.1A Pending CN112703600A (en) | 2018-12-29 | 2018-12-29 | Array substrate, display panel and display device |
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| Country | Link |
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| CN (1) | CN112703600A (en) |
| WO (1) | WO2020133446A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112838099B (en) * | 2021-01-07 | 2023-07-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
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| WO2020133446A1 (en) | 2020-07-02 |
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