CN112670180B

CN112670180B - Memory, semiconductor device and manufacturing method thereof

Info

Publication number: CN112670180B
Application number: CN201910982431.5A
Authority: CN
Inventors: 韩清华
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-10-16
Filing date: 2019-10-16
Publication date: 2024-08-23
Anticipated expiration: 2039-10-16
Also published as: CN112670180A

Abstract

The invention discloses a memory, a semiconductor device and a method of manufacturing the same. The method comprises the following steps: etching fins on the surface of the substrate; forming a protective film on the fin for preventing oxidation of the fin; etching at least the substrate body around the fin to form a base protruding from the substrate body at the bottom of the fin; an oxidation base; depositing a first dielectric layer on the surface of the substrate, wherein the thickness of the first dielectric layer is at least greater than the height of the base station; removing the protective film on the top of the fin and enabling the top surface of the fin to be flush with the upper surface of the first dielectric layer; transistors are fabricated in the fins. The method can adopt bulk silicon as a substrate to manufacture the semiconductor device, and the whole manufacturing process is simple, and the low-leakage-current semiconductor device manufactured by the method has lower cost.

Description

Memory, semiconductor device and manufacturing method thereof

Technical Field

The present invention relates generally to semiconductor technology, and more particularly, to a memory, a semiconductor device, and a method of manufacturing the same.

Background

Memory cells in DRAM memories are particularly sensitive to transistor leakage, with smaller transistor leakage resulting in better retention time (retention time) and sensing margin (SENSING MARGIN) for the memory cells. Among them, gate induced drain leakage current (GIDL) has a large influence on the reliability of a transistor.

In the semiconductor manufacturing process, SOI (Silicon-On-Insulator) technology is generally used to achieve the effect of reducing the leakage current of the transistor. SOI technology is typically achieved by forming a semiconductor film over an insulator and then forming a transistor over the semiconductor film, which significantly reduces the occurrence of transistor leakage. However, the cost of the semiconductor chip processed by the SOI technology is correspondingly higher due to the large processing difficulty and higher cost of the SOI substrate. The cost prohibitive SOI technology is not suitable for producing DRAM (dynamic random access memory) memory.

Therefore, there is a need for a process that can process transistors with small leakage currents on bulk silicon.

The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

It is a primary object of the present invention to overcome at least one of the above-mentioned drawbacks of the prior art, and to provide a method of fabricating a semiconductor device, comprising:

etching fins on the surface of the substrate;

forming a protective film on the fin for preventing oxidation of the fin;

etching at least the substrate body around the fin to form a base protruding from the substrate body at the bottom of the fin;

an oxidation base;

depositing a first dielectric layer on the surface of the substrate, wherein the thickness of the first dielectric layer is at least greater than the height of the base station;

removing the protective film on the top of the fin and enabling the top surface of the fin to be flush with the upper surface of the first dielectric layer;

Transistors are fabricated in the fins.

According to one embodiment of the present invention, etching at least a substrate body around a fin to form a pedestal protruding from the substrate body at a bottom of the fin includes:

etching the protective film, and only retaining the protective film covered on the fin;

the substrate body around the fin is etched to form a pedestal protruding from the substrate body at the bottom of the fin.

According to one embodiment of the present invention, the etching method used for etching the protective film is a dry etching method.

According to one embodiment of the invention, the base station is oxidized using a thermal oxidation process.

According to one embodiment of the invention, when the oxidation is carried out by a thermal oxidation process, the oxidation temperature is in the range of 500-1200 ℃.

According to one embodiment of the invention, the fins are riser-shaped and the abutment is a bar-shaped boss extending along the bottom of the fins.

According to one embodiment of the invention, the top of the fin is removed by chemical mechanical polishing Cheng Laiqu to make the top surface of the fin flush with the upper surface of the first dielectric layer.

The present invention also proposes a semiconductor device comprising:

A substrate on which an insulating base is provided;

the fin is arranged on the upper surface of the base;

A first dielectric layer disposed between adjacent fins such that each fin is independent;

And the transistor is arranged in the fin and is intersected with the fin at a certain angle.

According to one embodiment of the invention, the thickness of the vertical portion of the abutment connected to the fin is in the range of 10-100nm.

According to one embodiment of the invention, the thickness of the horizontal portion of the abutment has a value in the range of 5-60nm.

According to one embodiment of the invention, the transistor is a triode or a diode.

According to one embodiment of the invention, a protective film is further provided between the fin and the first dielectric layer.

According to one embodiment of the present invention, the protective film is silicon nitride.

According to one embodiment of the invention, the substrate is a silicon, silicon carbide or silicon germanium substrate.

According to one embodiment of the invention, the transistor is angled from 15 degrees to 90 degrees to the fin.

The invention also proposes a memory comprising a semiconductor device as described above.

According to the technical scheme, the method has the advantages and positive effects that:

The bottom of the fin is provided with an insulating base, and two sides of the fin are provided with insulating first dielectric layers, so that the fin is surrounded by insulating materials, and insulation between the fin and the substrate is realized. With the fin as a substrate, a transistor is fabricated in the fin, and the transistor is correspondingly surrounded by an insulating material, so that the leakage current of the transistor is reduced, and particularly, the gate induced drain leakage current (GIDL) can be significantly reduced. The method can adopt bulk silicon as a substrate to manufacture the semiconductor device, and the whole manufacturing process is simple, so that the low-leakage-current semiconductor device manufactured by the method has lower cost. This method is particularly suitable for fabricating DRAM memories.

Drawings

Various objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the invention, when taken in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the invention and are not necessarily drawn to scale. In the drawings, like reference numerals refer to the same or similar parts throughout. Wherein:

Fig. 1 is a schematic perspective view of a semiconductor device according to an exemplary embodiment;

fig. 2 is a schematic diagram of a semiconductor device in full cross-section, shown in accordance with an exemplary embodiment;

fig. 3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment;

fig. 4 is a schematic diagram showing a semi-finished semiconductor device after step S1 in full section according to an exemplary embodiment;

fig. 5 is a schematic diagram showing a semi-finished semiconductor device after step S2 in full section according to an exemplary embodiment;

fig. 6 is a schematic diagram showing a full cross-section of a semi-finished semiconductor device after step S31 is performed, according to an exemplary embodiment;

Fig. 7 is a schematic diagram showing a full cross-section of a semi-finished semiconductor device after step S32 is performed, according to an exemplary embodiment;

fig. 8 is a schematic diagram showing a semi-finished semiconductor device after step S4 in full section according to an exemplary embodiment;

Fig. 9 is a schematic diagram showing a full cross-section of a semi-finished semiconductor device after step S5 is performed, according to an exemplary embodiment;

Fig. 10 is a schematic diagram showing a semi-finished semiconductor device after step S6 in full section according to an exemplary embodiment;

fig. 11 is a schematic diagram showing a full cross-section of a semi-finished semiconductor device after step S71 is performed, according to an exemplary embodiment;

fig. 12 is a schematic diagram showing a full cross-section of a semi-finished semiconductor device after step S72 is performed, according to an exemplary embodiment;

fig. 13 is a schematic diagram showing a full cross-section of a semi-finished semiconductor device after deposition of the second dielectric layer in step S73, according to an example embodiment;

fig. 14 is a schematic diagram showing a full cross-section of a semi-finished semiconductor device after performing the formation of the first electrode in step S73, according to an exemplary embodiment;

fig. 15 is a schematic diagram showing a full cross-section of a semi-finished semiconductor device after deposition of the third dielectric layer in step S73, according to an example embodiment;

Wherein reference numerals are as follows:

1. A semiconductor device; 11. a substrate body; 111. a protective layer; 100. a transistor; 12. a fin; 121. a first doped region; 122. a second doped region; 13. a protective film; 14. a base station; 15. an insulating layer; 16. a first dielectric layer; 17. a groove; 18. a second dielectric layer; 19. a first electrode; 20. a third dielectric layer; 21. a first polysilicon layer; 22. a second polysilicon layer; 23. a second electrode; 24. a third electrode; 161. a slit.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.

The embodiment discloses a memory. The memory may be a DRAM memory. The reservoir comprises at least one semiconductor device 1, which semiconductor device 1 is shown in fig. 1 and 2.

Referring to fig. 3, fig. 3 shows a method of manufacturing a semiconductor device 1 in the present embodiment. The manufacturing method comprises the steps S1 to S7.

Referring to fig. 4, step S1: etching fins 12 on the surface of the substrate;

The substrate may be a silicon, silicon carbide or silicon germanium substrate. The substrate is preferably bulk silicon, which is inexpensive. The substrate may be substantially planar. A protective layer 111 is formed on the surface of the substrate in advance, and the protective layer 111 may be a silicon nitride film. The etching of the substrate may be performed by dry etching or wet etching the region of the substrate where the fin 12 is not required to be formed, while leaving the region where the fin 12 is required to be formed, thereby forming the fin 12 protruding from the surface of the substrate body 11 after etching the thin substrate.

The individual fins 12 are configured as riser structures, which are not limited to being flat plates, nor are the surfaces of the risers limited to being planar, and the surfaces of the risers may also be irregular surfaces such as curved surfaces, without limitation. The fins 12 are preferably straight, bar-shaped risers. The substrate is an N-well type or P-well type substrate. Trivalent impurity ions, such as boron, indium and gallium ions, are implanted into the P-well type substrate, and pentavalent impurity ions, such as phosphorus, arsenic and antimony ions, are implanted into the N-well type substrate. The fin 12 is of the same conductivity type as the substrate, i.e., both are P-well or N-well.

Referring to fig. 5, step S2: forming a protective film 13 for preventing oxidation of the fin 12 on the fin 12;

the protective film 13 completely covers the fin 12, and the protective film 13 covering the fin 12 side end face is not shown in fig. 1 and fig. 5 to 15. The protective film 13 may be formed on the surface of the fin 12 through a chemical vapor deposition process. Protective films 13 cover the respective side walls and top wall of the fin 12. The thickness of the protective film 13 may be 3 to 5nm. The protective film 13 is preferably a nitride of silicon, for example, silicon nitride. Silicon nitride may be formed by reacting dichlorosilane (SiH ₂Cl₂) with ammonia (NH ₃) at high temperature.

Referring to fig. 6 and 7, step S3: etching at least the substrate body 11 around the fins 12 to form a base 14 protruding from the substrate body 11 at the bottom of the fins 12;

The substrate body 11 around the fins 12 is etched so that the substrate is further thinned so that the portions under the fins 12 are exposed to form the base 14. The base 14 protrudes from the substrate body. The abutment is a bar-shaped boss extending along the bottom of the fin. During etching of the substrate, it is desirable to avoid etching away the protective film 13 on the fin 12, preferably by dry etching.

Referring to fig. 8, step S4: an oxidation base 14;

In this step, the base 14 may be oxidized by a thermal oxidation method. The substrate is first placed in an oxidation furnace, the oxidation furnace is filled with dry oxygen, and then the temperature in the oxidation furnace is raised so that the oxygen oxidizes the base 14 of the substrate that is not covered with the protective film 13. The abutment 14 typically needs to be fully oxidized. Since the surface of the substrate in the region not covered with the protective film 13 is oxidized during the thermal oxidation of the base 14, the insulating layer 15 is formed. At this time, the insulating layer 15 and the base 14 are both oxides of silicon, for example, silicon dioxide. And the fin 12 is covered with a protective film 13, the protective film 13 being capable of preventing the fin 12 from being oxidized.

The thickness of the vertical part of the base platform connected with the fin is 10-100nm, the thickness of the horizontal part of the base platform is 5-60nm, and the oxidation temperature is 500-1200 ℃, so that the material of the base platform can be completely oxidized into silicon dioxide. The silicon dioxide prepared by adopting the thermal oxidation method is of an amorphous structure, the resistivity is as high as 1 multiplied by 10 ¹⁴～1×10¹⁶ omega gcm, and the base station has good insulating property.

Referring to fig. 9, step S5: depositing a first dielectric layer 16 on the surface of the substrate, the first dielectric layer 16 having a thickness at least greater than the height of the base 14;

the material of the first dielectric layer 16 may be an oxide of silicon, such as silicon dioxide. The first dielectric layer 16 may be formed by a chemical vapor deposition process. The first dielectric layer 16 may be formed by reacting dichlorosilane (SiH ₂Cl₂) and ozone (O ₃) at high temperature. The thickness of the first dielectric layer 16 is greater than the height of the base 14. Thus, both sides of the fin 12 are filled with the first dielectric layer 16. The fin 12 is embedded in the slot 161 of the first dielectric layer 16.

Referring to fig. 10, step S6: removing the protective film on the top of the fin and enabling the upper surface of the first dielectric layer 16 to be level with the top surface of the fin 12;

A polishing process may be used to make the upper surface of the first dielectric layer 16 flush with the top surface of the fin 12. The Polishing process may be a chemical mechanical Polishing (CHEMICAL MECHANICAL Polishing) process. The protective film 13 and the protective layer 111 on top of the fin 12 can also be removed during the polishing process to expose the top of the fin 12.

Referring to fig. 1 and 2, step S7: fabricating a transistor 100 within fin 12;

In this step, the transistor 100 may be fabricated in the fin 12 using conventional transistor fabrication processes with the fin 12 as a substrate. Transistor 100 intersects fin 12 at an angle, which is preferably 15 degrees to 90 degrees. The transistor 100 may be a transistor or a diode. The bottom of the fin 12 has an insulating base 14 and the sides of the fin 12 have an insulating first dielectric layer 16, so that the fin 12 is surrounded by insulating material, which provides insulation between the fin 12 and the substrate. With the fin 12 as a substrate, the transistor 100 is fabricated in the fin 12, and the transistor 100 is correspondingly surrounded by an insulating material, so that the leakage current of the transistor 100 is reduced. In particular, when the transistor is a triode, gate induced drain leakage current (GIDL) can be significantly reduced. The method can adopt bulk silicon as a substrate to manufacture the semiconductor device 1, and the whole manufacturing process is simple, so that the low-leakage current semiconductor device 1 manufactured by the method has lower cost. This method is particularly suitable for fabricating DRAM memories.

Further, step S7 includes steps S71 to S74.

Referring to fig. 11 and 2, step S71: ion implanting the fin 12 to form a first doped region 121 and a second doped region 122 on top of the fin 12, the first doped region 121 and the second doped region 122 being of opposite conductivity type to the fin 12;

The fin 12 is ion-implanted from the top of the fin 12 to form a first doped region 121 and a second doped region 122 at the top of the fin 12. The first doped region 121 and the second doped region 122 are both P-type doped or both N-type doped. The P-type doped first doped region 121 and the second doped region 122 are implanted with trivalent impurity ions, such as boron, indium, gallium ions; the N-type doped first and second doped regions 121 and 122 are implanted with pentavalent impurity ions, such as phosphorus, arsenic, antimony ions. When the fin 12 is P-well type, the first doped region 121 and the second doped region 122 are both N-type doped; when the fin 12 is N-well type, the first doped region 121 and the second doped region 122 are P-type doped. In this embodiment, the first doped region 121 and the second doped region 122 are both N-type doped, and the fin 12 is N-well type. The first and second doped regions 121 and 122 may be formed by the same ion implantation process. The first and second doped regions 121 and 122 may also be formed by two ion implantation processes, respectively. The first doped region 121 and the second doped region 122 are both located on top of the fin 12. The first doped region 121 and the second doped region 122 are separated from each other along the length direction of the fin 12.

Referring to fig. 12, step S72: the fin 12 is etched to form a trench 17 between the first doped region 121 and the second doped region 122, the bottom of the trench 17 not extending to the mesa 14.

The fin 12 may be etched using dry etching. The grooves 17 formed in the fins 12 penetrate the fins 12 in a direction perpendicular to the plate surface of the fins 12. The trench 17 separates the first doped region 121 and the second doped region 122. The trench 17 does not completely break the fin 12, and the fin 12 at the bottom of the trench 17 forms a saddle fin (SADDLE FIN). The depth of both the first and second doped regions 121, 122 is less than the depth of the trench 17. The width of the groove 17 is preferably smaller than the depth. The cross section of the groove 17 is preferably trapezoidal with the upper base of the trapezoid being wider than the lower base.

Step S73: referring to fig. 13, a second dielectric layer 18 is deposited on the inner walls of the trench 17, and referring to fig. 14, a metal material is deposited into the trench 17 to form a first electrode 19;

An insulating material is deposited on the inner walls of the trenches 17 to form a second dielectric layer 18 on the inner walls of the trenches 17. The material of the second dielectric layer 18 may be an oxide of silicon, such as silicon dioxide. The second dielectric layer 18 does not fill the inner walls of the trenches 17. After the second dielectric layer 18 is attached to the inner wall of the trench 17, a metal material is deposited on the surface of the second dielectric layer 18 to form the first electrode 19 in the trench 17. A second dielectric layer 18 separates the metal material from the fin 12. The first electrode 19 may be made of tungsten, copper, aluminum, gold, silver, or other metal materials.

Referring to fig. 1 and 2, step S74: depositing a first polysilicon layer 21 over the first doped region 121 and a second polysilicon layer 22 over the second doped region 122; a metal material is deposited on the first polysilicon layer 21 to form a second electrode 23, and a metal material is deposited on the second polysilicon layer 22 to form a third electrode 24.

The first polysilicon layer 21 and the second polysilicon layer 22 are made of polysilicon, and can be made by chemical vapor deposition. The second electrode 23 and the third electrode 24 may be made of a metal material such as tungsten, copper, aluminum, gold, or silver. The first polysilicon layer 21 is disposed between the first doped region 121 and the second electrode 23. The second polysilicon layer 22 is disposed between the second doped region 122 and the third electrode 24. Thus, a transistor 100 is formed in the fin 12, the gate of the transistor 100 being the first electrode 19, the drain being the second electrode 23, and the source being the third electrode 24.

Further, in step S1, a plurality of fins 12 are etched on the surface of the substrate, and the fins 12 are parallel to each other;

in step S2, a layer of protective film 13 is deposited on each fin 12;

in step S3, when etching the substrate body 11 around the fins 12, the substrate body 11 in the region between the adjacent two fins 12 is also etched;

In step S5, when the first dielectric layer 16 is deposited, the first dielectric layer 16 fills at least the gap between two adjacent fins 12;

in step S6, the protective film 13 on top of all fins 12 is removed;

In step S7, at least one transistor 100 is fabricated within each fin 12;

After such processing, the transistor 100 can be fabricated in each fin 12, and the first dielectric layer 16 between two adjacent fins 12 forms a shallow trench isolation region that can effectively isolate the transistor 100 on the adjacent two fins 12 while reducing the occurrence of leakage current.

Further, in step S71, at least two first doped regions 121 are formed and a second doped region 122 is disposed between every two adjacent first doped regions 121 when ion implantation is performed on the fin 12;

In step S72, when the fin 12 is etched, the trench 17 is etched between the adjacent first doped region 121 and the second doped region 122;

In step S73, a second dielectric layer 18 is deposited in each trench 17, and then a metallic material is deposited in each trench 17 to form a first electrode 19 in each trench 17;

In step S74, a first polysilicon layer 21 is multiplied on each first doped region 121, and a second electrode 23 is formed on each first polysilicon layer 21;

thus, two transistors 100 are formed in each fin 12, and the two transistors 100 share one third electrode 24 as a source, the gates of the two transistors 100 are respectively two first electrodes 19, and the drains of the two transistors 100 are respectively two second electrodes 23. Sharing a single source for both transistors 100 reduces the overall area of the transistor 100 and reduces the device size. The memory further comprises at least two storage capacitors, the second electrodes 23 of the two transistors can be used as storage capacitor contact terminals to be respectively connected with the two storage capacitors, and the two transistors 100 can respectively control the two storage capacitors.

Further, in step S72, the fins 12 and the first dielectric layer 16 are etched simultaneously so that the trench 17 can penetrate the plurality of fins 12;

in step S73, the first electrode 19 forms a metal line extending along the trench 17, the metal line extending through the plurality of fins 12;

In step S74, the third electrode 24 forms a metal line covering the second polysilicon layer 22 on the different fin 12.

Thus, the metal line formed by the first electrode 19 may be used as a word line of the memory, and the metal line formed by the third electrode 24 may be used as a bit line of the memory. The transistors 100 connected to the word line are all on when the word line is high, and the transistors 100 connected to the word line are all off when the word line is low.

Further, step S3 includes step S31 and step S32.

Referring to fig. 6, step S31: the protective film 13 is etched, leaving only the protective film 13 overlying the fin 12.

Referring to fig. 7, step S32: the substrate body 11 around the fin 12 is etched to form a base 14 protruding from the substrate body 11 at the bottom of the fin 12.

Since the materials of the protective film 13 and the substrate body 11 are different, the etching is divided into two times, and each etching is more targeted, which is more beneficial to improving the etching precision.

Further, referring to fig. 15, in step S73, after the first electrode 19 is formed, a third dielectric layer 20 is further deposited on the upper surface of the first electrode 19 to cover the first electrode 19.

The third dielectric layer 20 has insulation property, and the material of the third dielectric layer 20 may be silicon nitride. The third dielectric layer 20 can insulate the first electrode 19 from other components above the first electrode 19. The surface of the third dielectric layer 20 is preferably flush with the surface of the first dielectric layer 16.

In another preferred embodiment, the substrate used is an SOI (Silicon-On-Insulator) insulating substrate.

Although the invention has been disclosed with reference to certain embodiments, numerous variations and modifications may be made to the described embodiments without departing from the scope and scope of the invention. It is to be understood, therefore, that the invention is not to be limited to the specific embodiments disclosed and that it is to be defined by the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that,

Comprising the following steps:

A substrate on which an insulating base is provided;

the fin is arranged on the upper surface of the base;

A first dielectric layer arranged between adjacent fins, so that each fin exists independently, and the upper surface of the first dielectric layer is flush with the top surface of the fin;

the transistor is arranged in the fin and is crossed with the fin at a certain angle;

a protective film is also disposed between the fin and the first dielectric layer.

2. The semiconductor device according to claim 1, wherein,

The fin is riser-shaped, and the base is a strip-shaped boss extending along the bottom of the fin.

3. The semiconductor device according to claim 2, wherein,

The thickness of the vertical part of the base platform connected with the fin is 10-100nm.

4. The semiconductor device according to claim 2, wherein,

The thickness of the horizontal part of the base is 5-60nm.

5. The semiconductor device according to claim 1, wherein,

The transistor is a triode or a diode.

6. The semiconductor device according to claim 1, wherein,

The protective film is silicon nitride.

7. The semiconductor device according to claim 1, wherein,

The substrate is a silicon, silicon carbide or silicon germanium substrate.

8. The semiconductor device according to claim 1, wherein,

The transistor is at an angle of 15 degrees to 90 degrees to the fin.

9. A memory, characterized in that,

A semiconductor device comprising any of claims 1 to 8.