CN112612740B - Serial data transparent transmission system based on SPI bus protocol - Google Patents
Serial data transparent transmission system based on SPI bus protocol Download PDFInfo
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- CN112612740B CN112612740B CN202011521890.2A CN202011521890A CN112612740B CN 112612740 B CN112612740 B CN 112612740B CN 202011521890 A CN202011521890 A CN 202011521890A CN 112612740 B CN112612740 B CN 112612740B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
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Abstract
The invention provides a serial data transparent transmission system based on an SPI bus protocol, which comprises a host computer, a slave chip unit and a data transmission system, wherein the host computer comprises a microcontroller, the slave chip unit comprises a plurality of slave chips connected in series, and each slave chip comprises a master side controller, a slave side controller and two groups of multiplexers. And the slave side controllers of the first slave chip in the plurality of slave chips connected in series are connected with the microcontroller of the upper computer, and the slave side controllers of the other slave chips are respectively connected with the master side controller of the previous slave chip, so that the upper computer can perform data read-write operation on all the slave chips connected in series.
Description
Technical Field
The disclosure relates to the technical field of integrated circuits, in particular to a serial data transmission system based on an SPI bus protocol.
Background
SPI (SERIAL PERIPHERAL INTERFACE ) is a high-speed, full duplex, synchronous communication bus first proposed by Motorola, and occupies only 4 wires on the pins of the chip, saving pins of the chip, and saving space on the PCB layout, which is a simple and easy-to-use feature, and now more and more devices support this communication protocol.
The SPI interface is a common interface of the sensor chip and is used as a communication interface for sensor chip configuration and sensor data interaction. The conventional micro-control processor or processors communicate with the chip through the SPI protocol, and one-to-one or one-to-many communication can be adopted. When a pair of N communication architectures are adopted, the MCU (Microcontroller Unit, micro control processor) is required to output N CSN ports which are respectively connected with a target chip, but the port number of the micro control processor is obviously increased, so that the use efficiency of the MCU is reduced, and the expansion performance of the SPI communication system is obviously restricted.
Disclosure of Invention
First, the technical problem to be solved
Based on the above problems, the present disclosure provides a serial data transparent transmission system based on an SPI bus protocol, so as to alleviate the technical problems of low expansibility of a circuit system, low communication efficiency, and the like caused by excessive occupation of interface resources of a master control processor by a one-master-multiple-slave SPI communication system in the prior art.
(II) technical scheme
The invention provides a serial data transparent transmission system based on an SPI bus protocol, which comprises a host computer, a slave chip unit and a data transmission system, wherein the host computer comprises a microcontroller, the slave chip unit comprises a plurality of slave chips connected in series, and each slave chip comprises a master side controller, a slave side controller and two groups of multiplexers.
According to the embodiment of the disclosure, the slave side controller of the first slave chip of the plurality of slave chips connected in series is connected with the microcontroller of the upper computer, and the slave side controllers of the other slave chips are respectively connected with the master side controller of the previous slave chip, so that the upper computer can read and write data of all the slave chips connected in series.
According to the embodiment of the disclosure, the multiplexer is configured to send a bypass signal to the slave chip, so as to realize a punch-through function of an SPI signal sent by the upper computer, thereby performing a data reading operation on any specific slave chip.
According to the embodiment of the disclosure, the host initiates writing operation, the chip selection address is 00, which means that the host needs to write into each slave chip, and if the chip selection address is not 00, only the slave chip corresponding to the chip selection address is written into.
According to the embodiment of the disclosure, if the chip selection address of the slave chip where the multiplexer is located is the same as the chip selection address in the write operation sent by the upper computer, the write operation is directly executed.
According to the embodiment of the disclosure, if the chip selection address of the slave chip where the multiplexer is located is different from the chip selection address in the write operation sent by the upper computer, the multiplexer sends a bypass signal to switch to the bypass mode, so as to realize the punch-through function of the write command sent by the upper computer, and the write operation is transmitted to the slave chip of the next stage until the slave chip corresponding to the chip selection address is written.
According to the embodiment of the disclosure, when the upper computer sends out a read operation, the chip selection address of the slave chip is identified to be smaller than the pre-read chip selection address in the read operation sent out by the upper computer, and then the slave chip is switched to a bypass mode.
According to an embodiment of the disclosure, each slave chip further includes an automatic addressing register, configured to perform automatic addressing on the chip after power-up.
(III) beneficial effects
As can be seen from the above technical solutions, the serial data transparent transmission system based on the SPI bus protocol of the present disclosure has at least one or a part of the following advantages:
(1) Port resources of a host can be greatly saved, and system board-level wiring is saved;
(2) Reliable bidirectional data exchange of the transparent transmission system is realized, the integrity of SPI bus protocol is ensured, and the system design difficulty is reduced;
(3) The method has good expansibility, can realize flexible adjustment of the number of slave chips under the condition that the maximum value of the addressing register is not exceeded, and improves the efficiency of system design.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments thereof with reference to the accompanying drawings in which:
FIG. 1 schematically illustrates a block diagram of the constituent structure of a serial data pass-through system based on the SPI bus protocol in accordance with an embodiment of the present disclosure;
FIG. 2 schematically illustrates typical read and write operation timing of the SPI protocol of an embodiment of the present disclosure;
FIG. 3 schematically illustrates a serial data pass-through system write mode equivalent connection diagram of the present disclosure based on the SPI bus protocol, in accordance with an embodiment of the present disclosure;
FIG. 4 schematically illustrates a serial data pass-through system read mode equivalent connection diagram of the present disclosure based on the SPI bus protocol, in accordance with an embodiment of the present disclosure;
FIG. 5 schematically illustrates an automatic addressing flow diagram of a serial data pass-through system of the present disclosure based on the SPI bus protocol, in accordance with an embodiment of the present disclosure;
Fig. 6 schematically illustrates a chip write operation flow diagram of the serial data pass-through system of the present disclosure based on the SPI bus protocol, according to an embodiment of the present disclosure.
Fig. 7 schematically illustrates a system read operation flow diagram of the serial data pass-through system of the present disclosure based on the SPI bus protocol, according to an embodiment of the present disclosure.
Detailed Description
The serial data transmission system based on the SPI bus protocol consists of a design scheme of an on-chip interface circuit supporting the system and a read-write operation flow based on the SPI protocol, and realizes an efficient one-to-many communication function on the basis of adhering to the content of the SPI protocol.
In implementing the present disclosure, the inventors have found that SPI communicates in a Master-Slave manner, and a Master device has a plurality of slaves, at least four signal lines are required, respectively, a MOSI (Master Output/Slave Input) signal line controlled by the Master device, a MISO (Master Input/Slave Output) signal line controlled by the Slave device, a SCLK (clock) signal line generated by the Master device, and a CSN (Slave enable) signal line controlled by the Master device. The CSN signal line is used to control whether the chip is selected, that is, the chip select signal is a predetermined enable signal (low level), and the operation of the chip is only valid. This allows multiple SPI devices to be connected on the same bus, and referring to FIG. 2, which shows a typical read-write timing diagram of an SPI interface, the serial data transparent transmission system based on the SPI bus protocol of the present disclosure can improve the efficiency of a one-to-many SPI communication system.
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
In an embodiment of the present disclosure, a serial data transparent transmission system based on an SPI bus protocol is provided, and with reference to fig. 1, 3, and 4, the serial data transparent transmission system based on the SPI bus protocol includes:
an upper computer including a microcontroller, and
A slave chip unit comprising a plurality of slave chips connected in series, each slave chip comprising a master side controller, a slave side controller, and two sets of multiplexers;
Wherein, the slave side controller of the first slave chip in the plurality of slave chips connected in series is connected with the microcontroller of the upper computer, the slave side controllers of the other slave chips are respectively connected with the master side controller of the previous slave chip;
the multiplexer is controlled by a Bypass signal output from the side controller in the slave chip, and realizes the data reading operation of the upper computer on any appointed slave chip.
In the embodiment of the disclosure, fig. 1 shows a serial data transparent transmission system based on an SPI bus protocol in the present solution, which is formed by serially connecting an upper computer (a microcontroller MCU or the like) and a plurality of Slave chips, wherein the serial connection mode is that an SPI Slave side (Slave) of the present chip is connected to a Master side (Master) of a previous chip, and simultaneously, the SPI Master side of the present chip is connected to a Slave side of a next chip. The slave chip in the scheme comprises an SPI slave side controller and an SPI master side controller, and also comprises two groups of multiplexers (mux 1 and mux 2) and is controlled by a Bypass (Bypass) signal output by the slave side controller. When the Bypass signal is effective, the connection mode in the chip is Bypass of the master-slave controller in the chip, thus realizing the pass-through function of SPI signals, namely, the SPI signal group of the upper chip is directly connected with the SPI signal group of the lower chip.
In the embodiment of the disclosure, the control manner described above and shown in fig. 3 are combined to obtain the write mode equivalent connection diagram of the serial data transmission system based on the SPI bus described in the disclosure, and as shown in fig. 4, taking the read chip2 chip as an example, the read mode equivalent connection diagram when the system is in Bypass (Bypass) mode is shown, wherein it can be seen that the chip1 is switched to Bypass mode.
In the embodiment of the disclosure, as shown in fig. 2, only three signals of CSN, SCLK and MOSI are used for writing operation of the SPI protocol, which are all sent by the host, and all SPI interface signals are used for reading operation of the SPI protocol. Thus, it is determined that for compatibility with the SPI bus interface protocol, a write operation can support a one-to-many slave mode, whereas a one-to-one mode must be used for a one-to-many slave mode read operation if multiple CSN signals are disabled.
In the disclosed embodiment, as shown in fig. 5, after power-on, automatic addressing must first be performed, wherein a special register set in the slave chip, i.e., an automatic addressing register (register address of 00) is utilized. The specific operation includes that after power-on and starting, a host initiates a write operation, the chip select address is 00, the register address is 00, and the data is 01. After the SPI Slave controller of the first-stage chip receives the data, the chip selection address of the first-stage chip is set to be 01, the data is added with 1 (namely, the chip selection address is 00, the register address is 00, the data is 02), the second-stage chip is written in through the SPI MASTER controller of the current-stage chip, the chip selection address of the second-stage chip is set to be 02, the writing operation is sequentially completed step by step, and automatic addressing of the serial connection chip can be realized.
In the embodiment of the present disclosure, as shown in fig. 6, the data identification of the slave chip is specifically shown, so that the data writing of the master microcontroller MCU to all slave chips connected in series and the data writing to one slave chip can be realized. The method comprises the following specific operations that a host initiates writing operation, a chip selection address is 00, which means that the host needs to write in each slave chip, and if the chip selection address is not 00, the host only writes in a specified chip. After receiving the writing command from the chip, it will determine if the chip selection address is the same as the addressing of the chip (i.e. if the address 00 register data generated by the addressing is consistent), if so, it is stored in the corresponding register, and the writing operation is finished, if not, it is not stored, and it continues to use SPI MASTER to execute the same writing operation to the next chip.
In the embodiment of the present disclosure, as shown in fig. 7, three phases of writing "pre-read address" and recognizing mode switching, one-to-one read operation, and mode reset are respectively involved. The system firstly executes writing operation, writes chip selection addresses for executing reading operation into 01 address registers (pre-reading address registers) of all slave chips, so that each slave chip can identify whether a host computer is about to execute the reading operation on the slave chip, the chip identification local addressing is smaller than the pre-reading chip selection addresses, the chip identification local addressing is switched to a Bypass (Bypass) mode, the whole serial transparent transmission system forms temporary one-to-one SPI connection, the host computer can execute normal reading operation, and after the reading operation is finished, the host computer resets the 01 address registers of all the slave chips to realize resetting from the Bypass mode (Bypass) to a serial writing mode.
The above embodiments are further described in detail with reference to the objects, technical solutions and advantageous effects of the present disclosure. It should be understood that the foregoing is only an example of the specific embodiments of the present disclosure, and is not intended to limit the disclosure, but any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Thus, embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the drawings or the text of the specification, implementations not shown or described are all forms known to those of ordinary skill in the art, and not described in detail. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be simply modified or replaced by those of ordinary skill in the art.
From the above description, those skilled in the art should clearly recognize that the present disclosure is based on the serial data pass-through system of the SPI bus protocol.
In summary, the present disclosure provides a serial data transparent transmission system based on an SPI bus protocol, which can greatly save port resources of a host for one-to-many SPI system requirements, and save system board level wiring. Through reasonable in design's working method, including automatic addressing, write operation, read operation flow etc., realized passing through the reliable two-way data exchange of transmission system based on SPI bus protocol, guaranteed the integrality of SPI bus protocol, reduced the system design degree of difficulty, have good expansibility, under the condition that does not surpass addressing register maximum value, can realize from flexible adjustment of chip number, improved the efficiency of system design.
It should be further noted that, the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings, and are not intended to limit the scope of the present disclosure. Like elements are denoted by like or similar reference numerals throughout the drawings. Conventional structures or constructions will be omitted when they may cause confusion in understanding the present disclosure.
And the shapes and dimensions of the various elements in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. In addition, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the description and the claims to modify a corresponding element does not by itself connote any ordinal number of elements or the order of manufacturing or use of the ordinal numbers in a particular claim, merely for enabling an element having a particular name to be clearly distinguished from another element having the same name.
Furthermore, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the list above and may be changed or rearranged according to the desired design. In addition, the above embodiments may be mixed with each other or other embodiments based on design and reliability, i.e. the technical features of the different embodiments may be freely combined to form more embodiments.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also, in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (6)
1. A serial data pass-through system based on an SPI bus protocol, comprising:
an upper computer including a microcontroller, and
A slave chip unit comprising a plurality of slave chips connected in series, each slave chip comprising a master side controller, a slave side controller, and two sets of multiplexers;
The method comprises the steps that an upper computer initiates writing operation, a chip selection address is 00, which means that the upper computer needs to write in each slave chip, if the chip selection address is not 00, only the slave chip corresponding to the chip selection address is written in, and if the chip selection address of the slave chip where a multiplexer is located is different from the chip selection address in writing operation sent by the upper computer, the multiplexer sends a bypass signal to switch to a bypass mode, so that a pass-through function of a writing command sent by the upper computer is realized, and the writing operation is transmitted to the slave chip at the next stage until the slave chip corresponding to the chip selection address is written in.
2. The serial data transparent transmission system based on the SPI bus protocol as set forth in claim 1, wherein the slave side controller of the first slave chip of the plurality of serially connected slave chips is connected with the microcontroller of the upper computer, and the slave side controllers of the other slave chips are respectively connected with the master side controller of the previous slave chip, so that the upper computer can perform data read-write operation on all the serially connected slave chips.
3. The serial data transparent transmission system based on the SPI bus protocol according to claim 1, wherein the multiplexer is configured to send a bypass signal to the slave chip, and implement a pass-through function of the SPI signal sent by the host computer, so as to perform a data reading operation on any specific slave chip.
4. The serial data transparent transmission system based on the SPI bus protocol according to claim 1, wherein the multiplexer is located at the same chip select address from the chip as the chip select address in the write operation sent from the host computer, and directly performs the write operation.
5. The serial data transparent transmission system based on SPI bus protocol as set forth in claim 3, wherein when the upper computer sends out a read operation, the slave chip recognizes that its chip selection address is smaller than the pre-read chip selection address in the read operation sent out by the upper computer, and then switches to the bypass mode.
6. A serial data transmission system based on the SPI bus protocol as recited in claim 3, further comprising an auto-addressing register in each slave chip for performing auto-addressing of the chip upon power-up.
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| CN107153622A (en) * | 2017-05-24 | 2017-09-12 | 中国电子科技集团公司第四十研究所 | A kind of drive control method based on spi bus |
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| CN111667877B (en) * | 2020-04-28 | 2023-01-17 | 中国科学院微电子研究所 | Memory test circuit, test system and test method |
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