CN1126029C - Method and appts. for access complex vector located in DSP memory - Google Patents

Abstract

A method and apparatus for efficiently accessing the real parts and the imaginary parts of complex vector components in a digital signal processor memory is implemented through the incorporation of a new processor addressing, the fixed displacement mode. An additional register, the fixed displacement register, and an additional control flag, the fixed displacement configuration bit are needed. The method of employment requires only a single address register, and does not require use of the normal offset register used for indexed addressing, leaving the offset register to be used for simultaneous post modification and/or bit reversal. Dual memory spaces sharing a common address space are not required, thereby simplifying memory management, and the method and apparatus are compatible with all addressing.

Description

Method and device for accessing complex vectors in DSP memory

technical field

The invention relates to a method for processor storage addressing and storage address generation, in particular to a method for accessing complex vectors stored in a digital signal processor memory.

Background technique

In US 4 809 156 a circuit for generating memory addresses in a computer system is described. An address generating logic includes two multiplexers (Multiplexer) and an adder, and the adder is connected with the memory address register for outputting the memory address to the central processing unit. Alternative inputs to a multiplexer are from the shift register (Displacement Register) and the extension register. Switching between the two registers is controlled by a sign bit, which is generated by a comparator, and the input value of the comparator is stored in the accumulator and the base address register. The comparator produces a sign detect output signal which reflects the value of the sign flag stored in the flags register. This symbol flag determines whether to select the shift register or the extension register as the input of the adder.

Figure 1 shows an address generation unit (AGU) 102 of a typical prior art processor, such as a digital signal processor. The term "processor" refers herein to any data processing device, such as, but not limited to, a digital signal processor. AGU 102 typically contains register banks for memory data access. Typical register banks, each containing three registers:

1. An address register (pointer) 104, represented by Rn;

2. An offset register 106, represented by Nn; and

3. A buffer length register 108, represented by Mn.

where n=1...k is the subscript of the group, and K is the number of groups existing in the processor address generation unit.

The term "Array" is used herein to denote any plurality of locations in the processor's memory such that each location is accessed with an index relative to a fixed base address, where an index is a Regular integer multiples. The term "Vector" is used herein to represent any multiplicity of data values stored in such an array, and the term "Component" is used herein to represent any data value of such a vector, and the term "Complex number)" in this context represents any pair of data values. This data value is denoted herein as "First part" and "Second part"; includes a pair of numbers consisting of a "real part" and an "imaginary part" in the usual mathematical sense , but not limited to this. The term "complex vector" refers herein to any pair of vectors of the same number of components. The term "First array" refers herein to any memory array in the processor that contains the first part (or vectors) of a pair of vectors of a complex number. And the term "second array (Second array)" refers herein to any memory array in the processor that contains the second part (or vector) of a vector pair of a complex vector. A complex vector can be composed of vectors of complex numbers in the usual mathematical sense; the real numbers of the complex vector are stored in the first array, and the imaginary numbers of the complex vector are stored in the second array. Alternatively, a complex vector can consist of vectors of complex numbers in the usual mathematical sense; the real numbers of the complex vector are stored in the second array, and the imaginary numbers of the complex vector are stored in the first array. As a further variation, a complex vector according to the invention may be composed of two vectors of any number of data values, which need not represent complex numbers in the usual mathematical sense. In addition, the terms "Access" and "Accessing" with respect to processor memory are used herein to represent in memory and fetching values stored in memory.

When working with complex vectors, the first and second arrays are usually placed at different addresses in memory, or in different memory spaces, depending on the processor's memory architecture. To access a complex vector with indirect addressing, two different address registers are required; one address register for the first array and one for the second array. A limitation of this approach is that address registers are expensive resources in digital signal processors. When the first array and the second array are in the same memory, a single address register and an offset register can be used for access. This method can be used if the address register itself points to the first array, and the offset register contains the offset between the first array and the second array. In this case, the first array can be accessed using indirect addressing of the address register (Rn), and the second array can be accessed using indexed indirect addressing of the address register and its offset register (that is, Rn+Nn). array. However, offset registers are already used in bit-reversal and post-modification-by-step addressing modes and cannot be used in indexed indirect addressing modes. Therefore, when indexed indirect addressing is used, two address registers are required for accessing complex vectors. This situation arises in the Fast Fourier Transform (FFT) algorithm, where bit-inverted addressing is used; in the simplification of complex signals, where stepwise post-modification addressing is used, etc. . (A survey of the field and descriptions of existing DSP architectures can be found in "A Buyer's Guide to Digital Signal Processors," published by Berkeley Design Technology Inc. in 1995.

Most existing digital signal modifiers do not address this memory access problem; therefore, to access a complex vector, two different address registers are required when the offset register is already in use. An existing solution is shown in Figure 2, which is used in Motorola's DSP56××× series processors. This approach uses two data stores: an X-store 202 and a Y-store 204, which have the same address space 206. It also requires a dedicated assembly language syntax (not shown in Figure 2) and an address generation unit (as shown in Figure 1). A complete description of this architecture can be found in the DSP56000 24-Bit Digital Signal Processor Family Handbook, published by Motorola, Inc. (DSP Division, Semiconductor Products Division, Austin, Texas); it contains the reference material described herein . In this prior art solution, the architecture of the address generation unit is such that the address register 208 (R0) points to the same address for both, the X-memory 202 and the Y-memory. Thus, the first array and the second array of complex vectors located in different memory spaces but at the same location can be accessed simultaneously using address register 208 (R0) alone. As shown in Figure 2, the address register points to address OX0002, but it has no specific relationship with the address space. Pointing to specific memory spaces is done by assembly language opcodes. For example, if the first array is located at X-memory 202 and the second array is located at Y-memory 204; and the first array stores the real part of the complex vector and the second array stores the imaginary part of the complex vector; then set address OX0002 Transferring the real part of the value to register A and the imaginary part to register B can be done with the following assembly code:

move X(R0), A;

move Y(R0), B;

This solution has two problems: First, the two parts of the vector (pointing to the first array and the second array respectively), must be located at the same location in different memories. This can lead to inefficient use of memory (gaps in the memory), while making it difficult to accomplish memory relocation when needed. For example, if the first array in X-memory 202 needs to be relocated, then the second array in Y-memory also needs to be relocated to keep both at the same address.

It is widely recognized and would be of great benefit to have an efficient method of accessing complex vectors in processor memory which requires only a single address register, does not require the use of offset registers and does not require multiple memories to share the same address space. The present invention meets this aim.

Contents of the invention

The present invention provides a processor, including: an address generation unit, which is used to calculate and access the storage address of the real number part and the imaginary part of the complex number vector stored in the memory of the processor, and the said complex number vector is vector pairs having the same number of data values, said process having indexed indirect addressing capability, and enabling a fixed displacement mode having a state selected from the group of an enabled state and a disabled state, Wherein said address generating unit includes: an address register; at least one programmable fixed displacement register; a control register containing a fixed displacement configuration flag indicating whether the fixed displacement mode is enabled or disabled; a buffer length register; and an offset register, which is distinguished from said fixed shift register. The real part of the complex data value is accessed with instructions having the non-indexed indirect addressing mode, and the imaginary part of the complex data value is accessed with the instruction having the indexed indirect addressing mode.

The present invention provides a method for implementing a fixed displacement mode in a processor having: an address register, at least one programmable fixed displacement register, a control with a fixed displacement configuration flag bit indicating the state of the fixed displacement mode registers, a buffer length register and an offset register distinct from said fixed shift register. The processor has instructions capable of using indexed indirect addressing, which involves the steps of: (a) registering a base address into an address register and a fixed displacement into a fixed displacement register, (b) checking for indexed indirect addressing For the current instruction in addressing mode, (c) check the fixed-displacement configuration flag bit, and (d) if the current instruction uses indexed indirect addressing mode and the fixed-displacement configuration bit is set, generate a value equal to said base address and said The storage address of the sum of fixed displacements.

The present invention provides a method for accessing complex data values of complex vectors by a processor, the complex data values have a real part with a base address and an imaginary part offset by a fixed displacement value from the base address, wherein the process executed by the processor The instruction can select the addressing mode from the group consisting of indexed indirect addressing mode and non-indexed indirect addressing mode. The method includes the following steps: a) register the base address into the address register; b) register the fixed displacement amount into At least one fixed displacement register; c) selecting the enabling state of the fixed displacement mode, wherein said selection of the enabling state of the fixed displacement mode includes the following steps: i) setting the fixed displacement configuration flag bit; and ii) using indexed indirect addressing addressing mode; d) using instructions with non-indexed indirect addressing mode to access the real part of the complex data value; e) using instructions with indexed indirect addressing mode to access the imaginary part of the complex data value.

Thus, the present invention successfully solves the disadvantages of the presently known arrangements and methods. First, the present invention can access complex vectors in any addressing mode by using a register set of an address generating unit. Secondly, the present invention does not propose any restriction on the storage allocation of the real part and the imaginary part of a complex vector (for example, its first array and second array), nor does it propose any restriction on the storage space and address.

Description of drawings

Herein, the invention is described by way of example with reference to the accompanying drawings, which are:

FIG. 1 shows an address generation unit of a prior art digital signal processor.

FIG. 2 shows a prior art storage configuration for digital signal processing.

Fig. 3 shows the novel characteristics of the address generating unit in the digital signal processor according to the present invention.

Figure 4 is a flow chart of a fixed shift address generation algorithm.

Figure 5 shows an example of memory states.

Figure 6 illustrates the architecture of two data storage spaces.

Detailed ways

According to the principle and operation of a method and device of the present invention, can explain with accompanying drawing and corresponding description, the important part of device address generation unit of the present invention is shown in Fig. 3, and the step of method of the present invention is shown in Fig. 4 The flowcharts illustrate their implementation in a digital signal processor or other processor according to the invention. These steps implement the fixed displacement mode, which is a new processor mode according to the invention.

As illustrated in Figure 3, it is first necessary to provide certain additional hardware capabilities. In particular, the processor must have a fixed shift register 310 in the address generation unit 302, denoted by Rf1. The fixed shift register should be software programmable like all other registers in address generation unit 302 . It is also possible, but not necessary, to use more than one fixed shift register, wherein additional fixed shift registers 312, 314 and 316 are represented by Rf2, Rf3...Rfn _n , respectively, in the figure Indicated by a dotted box. The ellipsis ... indicates that more additional fixed shift registers may be added. The register group 322 includes Rn, Nn, Mn, and Rf1. The present invention requires that the processor be capable of indexed indirect addressing mode, which can be implemented by any method known in the art. It should be noted that fixed shift register 310 and offset register 306 are distinct. Fixed shift register 310 and offset register 306 perform different functions, and they are used independently of each other.

In addition, this processor needs to have a new mode, which is called "fixed displacement mode" in this paper. This fixed displacement mode has two states: one is an enabled state and the other is a non-enabled state; they can be controlled by the fixed displacement configuration bit 320 added to the control register 318 . The fixed displacement configuration bits act as control flags in this method. The operation of the fixed displacement approach in the method of the present invention is described in detail below. Control register 318 may be an existing control register modified in an existing processor design, or it may be a new control register. Furthermore, the provided processor needs to have hardware to implement the process steps (see below) in a fixed shift mode. To implement the hardware facilities to perform the steps described below, various techniques well known in the art can be used.

According to the present invention, the steps of the method for realizing the fixed displacement method for generating the storage address executed by the processor are as follows, and are shown in FIG. 4 .

1. Register the register set 322 in the registering step 402 into the address generating unit 302 (FIG. 3). This step registers the base address into the address register 304 , the address offset into the offset register 306 , the buffer length into the buffer length register 308 , and the fixed displacement into the fixed displacement register 310 .

2. Check at decision point 404 whether the current instruction uses indexed indirect addressing.

3. If the indexed indirect addressing mode is not used, the address is generated in the address generation step 408 by the usual method, which is well known in the art.

4. If the indexed indirect addressing mode is used, at decision point 406 it is checked whether the fixed displacement configuration bit 302 (FIG. 3) is set.

5. If the fixed displacement configuration bit 320 is not set, the fixed displacement mode is in a disabled state, and the address generation unit 302 operates in the storage address generation step 410 according to the usual method. At this time, the new feature described herein operates, the access address is formed by Rn+Nn, which does not change the value of the Rn register 304 (FIG. 3). When the fixed displacement configuration bit 302 is cleared, the offset register Nn 306 (FIG. 3) is the source for all post-modified and indirect indexed addressing modes.

6. If the fixed displacement configuration bit is set, then the fixed displacement mode is enabled; the offset source generated by the storage address of all indexed indirect addressing modes is the fixed displacement register 310 (Rfn), not the offset Shift register 306(Nn); this process takes place in address generation step 412. The address generated is the sum of the contents of the fixed shift register 310 and the address register. Accessing address Rn+Rfn does not change the value of Rn register 304 (FIG. 3).

According to the present invention, the storage address generating method returns to step 414 and ends.

The fixed shift configuration bit is used as a control flag. When it is set, the fixed shift mode is enabled; when it is cleared, the fixed shift mode is disabled. In any case, the fixed shift mode is only valid when the current instruction uses the indexed indirect address mode. If the addressing mode used by the current instruction is not indexed indirect addressing mode, the fixed shift mode is not valid even if it is enabled. As is well known in the art, other addressing modes exist than indexed indirect addressing modes, including but not limited to direct addressing and post-modification addressing modes. It is possible to include any of these addressing modes in a single instruction. The term "Non-indexing indirect addressing" as used herein refers to any other addressing mode that does not include indexed indirect addressing.

It should be noted that assembly language can, but does not have to, support fixed shift register 310 (Rf1) in memory address generation commands. The term "assembly language" is used herein to refer to both: the assembly syntax support and the configuration that produces the machine instructions. If the assembly language supports fixed shift registers, then assembly syntax to enable fixed shifts is defined as a single instruction rather than as a processor with enabled and disabled states. In the case where the assembly language does not support fixed shift registers, it is sufficient to specify that the command has only the offset register 306(Nn). Because this specifies the addressing mode. The hardware automatically uses either the offset register 306 or the fixed shift register 310 for storage address generation depending on the state of the fixed shift configuration bits 320 . Also note that designating different storage arrays as "first array" or "second array" is arbitrary, and their contents are also completely arbitrary.

It is obvious that the method according to the invention allows the processor to efficiently access both parts of the complex vector. For example, suppose the states of the address generation unit and memory are as follows:

R1=1000 (address register 304 among Fig. 3)

N1=2 (offset register 306 among Fig. 3)

M1=is programmed into a linear addressing mode (buffer length register 308-actual programming is determined by the manufacturer in Figure 3)

Rf1=50 (fixed displacement register 310 among Fig. 3)

Execute the following assembly code (pseudocode):

Mov(R1)+N1,A;

MOV(R1+N1), B;

Wherein A and B are the general-purpose registers of the processor (not the registers of the address generation unit 302), note that (R1)+N1 is a post-modification addressing mode, which means that the storage access is to the location R1, and R1 is after the storage access, is incremented by N1. Note also that (R1+N1) is an indexed indirect addressing mode, meaning that the memory access is to location R1+N1, leaving R1 unchanged during or after the memory access.

FIG. 5 illustrates the situation when two different values of shift configuration bit 320 are fixed, with address 504 for memory area 502 . In Figure 5 and the examples below, all data values and address locations are represented in decimal, and in both cases the following holds:

• The storage area from address 1000 onwards to 1049 is designated as the first array 518 , while the storage area from address 1050 onwards is designated as the second array 520 .

·Before execution, the address register has an initial value of 506, which is equal to 1000. This means that the initial value of R1 points to memory location 512 which is equal to 1000, and the content of 1000 is -348.

After the first instruction is completed, register A has the value -348, and address register R1 points to address 1002, meaning that R1 points to location 514 in memory, which has an address of 1002 and contains data value 4391.

· After finishing execution, the last value of address register R1 is 510, which is equal to 1002. This is because the second instruction only includes the indexed addressing mode, and the indexed addressing mode does not change the value of an address register.

After executing the second instruction, the content of register B depends on the fixed displacement mode. The following describes the setting and clearing of the fixed shift mode.

Fixed shift configuration bits not set:

In this case, the fixed shift configuration bit is cleared (not set). Therefore, the fixed shift mode is not enabled. The storage address is generated in the usual way, after the execution of the second instruction, register B contains the value 4391 from the storage location 514 of the first array 518 .

Fixed shift configuration bit settings:

In this case, the fixed shift configuration bit is set. Therefore, the fixed displacement mode is enabled. Since the first instruction does not use indexed indirect addressing, the memory address for the first instruction is generated in the usual way. The second instruction uses the indexed indirect addressing mode, and because the fixed shift configuration bit is set (therefore, the fixed shift mode is enabled), the offset generated by the storage address is searched by Rf1, and the access content Storage address 516 for -819. Thus, in this case, after execution of the second instruction, the content of register B is -819, which is storage location 516 from the second array 520 .

So, this may effectively access the real and imaginary parts of a vector of complex numbers. For example, if the real number part is stored in the second array 520, and the imaginary number part is stored in the first array 518; The imaginary part of one, and register B holds a real part of the parts of the complex vector.

In the above examples, the method according to the invention is represented in a simple memory architecture, ie a single memory space structure. Today, advanced DSP algorithms require a relatively complete memory architecture, so modern digital signal processors have a dual-memory space structure. FIG. 6 shows an example, which is used for complex vectors according to the method of the present invention, and the first array and the second array have different storage spaces. Address 606 corresponds to data value content 608 . In Figure 6 and the following examples, all address locations are represented in hexadecimal.

In order to use the method of the present invention in a dual memory space architecture, the arrangement of the memory must be sequential. Here there is a memory space 602, represented by "X memory address space", for the first array 610, whose starting address is OX0000; at the same time, there is a storage space 604, denoted by "Y storage address space", used for the second array 612, and its start address is OX8000. As required, the addresses shown in Figure 6 are sequential. Note that in this example the MSB of the address identifies which memory space is being used.

In this configuration, the base address of the real part of the complex vector can be placed in X space 602, for example, address OX0002, and the base address of the imaginary part of the complex vector can be placed in Y space, for example, address OX8008. In order to work in the fixed displacement mode, the fixed displacement register Rf needs to be set to OX8006 (OX8008-OX0002), and the fixed displacement configuration bit 320 in the control register 318 (FIG. 3) should be set.

Although limited embodiments of the invention have been described, many variations, modifications and other applications of the invention will be recognized.

Claims (3)

1. A processor, comprising: An address generating unit (302), which is used to calculate and access the storage address of the real number part and the imaginary part of the complex number vector stored in the memory of the processor; it is characterized in that: said complex number vector has the same data a vector of pairs of values; said processing has indexed indirect addressing capability and enables a fixed displacement mode having a state selected from the group of an enabled state and a disabled state; Wherein said address generating unit (302) includes: an address register (304), at least one programmable fixed shift register (310, 312, 314, 316), A control register (318), which contains a fixed displacement configuration flag (320) indicating whether the fixed displacement mode is enabled or disabled, a buffer length register; and an offset register (306), which is distinct from said fixed shift registers (310, 312, 314, 316); accessing the real part of a complex data value with an instruction having non-indexed indirect addressing mode; Access the imaginary part of a complex data value using an instruction with indexed indirect addressing mode. 2. A method for implementing a fixed-displacement mode in a processor, the processor having an address register (304), at least one programmable fixed-displacement register (310, 312, 314, 316), a state register indicating the fixed-displacement mode The control register (318) of fixed displacement configuration flag bit (320), a buffer length register (318) and an offset register different from said fixed displacement register (310,312,314,316); It is characterized in that: The processor has instructions capable of using indexed indirect addressing, which involves the following steps: (a) deposit (S402) a base address into the address register (304) and a fixed displacement into the fixed displacement register (310, 312, 314, 316), (b) checking (S404) the current instruction for the indexed indirect addressing mode, (c) check (S406) fixed displacement configuration flag (320), and (d) If the current instruction uses the indexed indirect address mode, and the fixed displacement configuration bit (320) is set, generate (S412) a storage address equal to the sum of said base address and said fixed displacement. 3. The method for accessing the complex data value of the complex vector by the processor according to claim 1, characterized in that: the complex data value has a real part with a base address and an imaginary part offset by a fixed displacement value from the base address; wherein the instructions executed by the processor can select the addressing mode from the group consisting of indexed indirect addressing mode and non-indexed indirect addressing mode; The method includes the following steps: a) register the base address into the address register (304); b) registering the fixed displacement amount to at least one fixed displacement register (310, 312, 314, 316); c) Select the enabling state of the fixed displacement mode, wherein said selection of the enabling state of the fixed displacement mode includes the following steps: i) set the fixed displacement configuration flag (320); and ii) Use indexed indirect addressing; d) accessing the real part of a complex data value with an instruction having non-indexed indirect addressing mode; e) Accessing the imaginary part of a complex data value with an instruction having an indexed indirect addressing mode.

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