CN112509615B - Flash memory, sensing circuit and method for determining storage state of memory cell - Google Patents

Abstract

The present application relates to flash memory, sensing circuits, and methods of determining the storage state of a memory cell. The sensing circuit includes a first switch, a second switch, an isolation switch, and a state determination unit, wherein the first switch includes an input terminal connected to a system voltage source, and an output terminal connected to the input terminal of the isolation switch; the isolation switch includes an input terminal connected to an input terminal of the output terminal of the first switch, and an output terminal connected to a sensing node suitable for connection with the storage unit to be detected; the second switch includes an input terminal connected to the output terminal of the isolation switch; The output end of the memory cell series connection of the unit; the state determination unit is connected to the sensing node and is set to determine the storage state of the memory cell to be detected according to the voltage of the sensing node.

Description

Flash memory, sensing circuit and method for determining storage state of memory cell

technical field

The present application relates to a storage device, and more particularly, to a flash memory, a sensing circuit in the flash memory, and a method for determining a storage state of a memory cell to be detected by the sensing circuit.

Background technique

Flash memory is a type of non-volatile memory that can retain stored data without power. Compared with traditional hard disks, flash memory has the advantages of faster reading speed, lower power consumption, better shock resistance, etc., and is therefore used more and more. For example, flash memory is commonly used in electronic systems such as personal computers, digital cameras, digital media players, digital recorders, vehicles, wireless devices, cellular telephones, and removable memory modules.

Flash memory can be divided into NOR flash memory and NAND flash memory. Taking NAND flash memory as an example, in use, it is necessary to perform erasing and writing operations on specific memory cells, and in these operations, a sensing circuit for verifying or reading the state of the specific memory cells is required. A conventional sensing circuit firstly charges a sensing node connected to a certain bit line in the flash memory, and then determines the relationship with the bit by detecting the sensing voltage at the sensing node after being discharged through the bit line. The memory state of the selected memory cell corresponding to the line. In such a sensing circuit, the sensing voltages corresponding to different storage states are relatively close, which may affect the accuracy of state identification.

A later proposed sensing circuit further separates the sensing voltages corresponding to different storage states by setting a boost driver, so as to improve the identification accuracy of the storage states. However, this sense circuit requires a separate N-well at the precharge switch for the precharge sense node to prevent current leakage caused by boosting, which increases the design size of the sense circuit, It is not conducive to the miniaturization trend of flash memory. In addition, in the above two schemes, the control signal of the precharge switch needs to be changed many times when other page buffers are operated, which increases the power consumption of the sensing circuit.

Therefore, there is a need for a sensing circuit that can reduce design size and/or power consumption.

It should be understood that this Background section is intended, in part, to provide a useful background for understanding the present technology, and is not intended to imply that these matters were necessarily prior art that was already known to those skilled in the art prior to this application.

SUMMARY OF THE INVENTION

One aspect of the present disclosure provides a sensing circuit, a first switch, a second switch, an isolation switch, and a state determination unit, wherein the first switch includes an input terminal connected to a system voltage source, and an input terminal connected to the isolation switch an output terminal of the input terminal; the isolation switch includes an input terminal connected to the output terminal of the first switch, and an output terminal connected to a sensing node suitable for connection with the storage unit to be detected; the second switch includes an input terminal connected to the output terminal of the isolation switch and an output terminal adapted to be connected with the memory cell string including the memory cell to be detected; the state determination unit is connected to the sensing node and arranged to determine the storage state of the memory cell to be detected according to the voltage of the sensing node.

According to one embodiment, the isolating switch is a low voltage N-type device.

According to one embodiment, the isolation switch is a low voltage N-type metal oxide semiconductor transistor.

According to one embodiment, the state determination unit is configured to determine the storage state of the memory cell to be detected by comparing the voltage of the sensing node with a reference voltage.

According to one embodiment, the sensing circuit further includes a third switch including: an input connected to the output of the second switch; and an output connected to the string of memory cells.

According to one embodiment, a parasitic capacitance is formed between the output terminal of the third switch and the ground.

According to one embodiment, the sensing circuit further includes a fourth switch including: an input connected to the system voltage source; and an output connected to the input of the third switch.

According to one embodiment, the first switch, the second switch, the third switch and the fourth switch are metal oxide semiconductor transistors.

According to one embodiment, the first switch is a P-type metal oxide semiconductor transistor.

According to one embodiment, the second switch, the third switch and the fourth switch are N-type metal oxide semiconductor transistors.

According to one embodiment, the sense circuit further includes a boost driver connected to the sense node and configured to provide a boost voltage to the sense node.

According to one embodiment, a parasitic capacitance is formed between the output of the isolation switch and the boost driver.

According to one embodiment, a parasitic capacitance is formed between the output terminal of the isolation switch and ground.

Another aspect of the present disclosure provides a method for determining a storage state of a memory cell to be detected by a sensing circuit, the sensing circuit includes a first switch, a second switch, an isolation switch, and a state determination unit, wherein the first The input terminal of the switch is adapted to receive the system voltage from the system voltage source, the output terminal of the first switch is connected to the input terminal of the isolation switch, the output terminal of the isolation switch is connected to the sensing node and the input terminal of the second switch, and the output terminal of the second switch is connected to the input terminal of the second switch. The output terminal is connected to a memory cell string including a memory cell to be detected, and the method includes: turning on a first switch and an isolation switch at a first time point to charge a sensing node with a system voltage; turning off at a second time point turning on the first switch and the isolation switch; turning on the second switch at a third time point so that the sensing node is electrically connected to the memory cell string; turning off the second switch at a fourth time point; The voltage of the detection node determines the storage state of the memory cell to be detected.

According to one embodiment, the method further comprises: applying a boost voltage to the sensing node at a fifth time point between the second time point and the third time point, and reducing the boost voltage at a sixth time point after the fourth time point and determining the storage state of the memory cell to be detected according to the voltage of the sensing node after the sixth time point.

According to one embodiment, the sensing circuit further comprises a boost driver connected to the sensing node, the boost driver being arranged to apply a boost voltage to the sensing node.

According to one embodiment, a parasitic capacitance is formed between the output of the isolation switch and the boost driver.

According to one embodiment, the isolating switch is a low voltage N-type device.

According to one embodiment, the isolation switch is a low voltage N-type metal oxide semiconductor transistor.

According to one embodiment, determining the storage state of the memory cell to be detected includes: determining the storage state of the memory cell to be detected by comparing the voltage of the sensing node with a reference voltage.

According to one embodiment, the sensing circuit further includes a third switch including: an input connected to the output of the second switch; and an output connected to the string of memory cells.

According to one embodiment, a parasitic capacitance is formed between the output terminal of the third switch and the ground.

According to one embodiment, the sensing circuit further includes a fourth switch including: an input connected to the system voltage source; and an output connected to the input of the third switch.

According to one embodiment, the first switch, the second switch, the third switch and the fourth switch are metal oxide semiconductor transistors.

According to one embodiment, the first switch is a P-type metal oxide semiconductor transistor.

According to one embodiment, the second switch, the third switch and the fourth switch are N-type metal oxide semiconductor transistors.

According to one embodiment, a parasitic capacitance is formed between the output terminal of the isolation switch and ground.

Yet another aspect of the present disclosure provides a flash memory including: a plurality of memory cells arranged in an array; and a plurality of the sensing circuits as described above, respectively connected to each column of the plurality of memory cells.

Description of drawings

The above and other advantages and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a flash memory according to an embodiment of the present disclosure.

2 shows a schematic diagram of a sensing circuit according to an embodiment of the present disclosure.

3 illustrates a control signal timing diagram for the sensing circuit in FIG. 2 in accordance with an embodiment of the present disclosure.

FIG. 4 shows a flowchart of a method for operating the sensing circuit of FIG. 2 in accordance with an embodiment of the present disclosure.

FIG. 5 shows a schematic diagram of a sensing circuit according to another embodiment of the present disclosure.

FIG. 6 illustrates a control signal timing diagram for the sensing circuit in FIG. 5 according to an embodiment of the present disclosure.

FIG. 7 shows a flowchart of a method for operating the sensing circuit of FIG. 5 in accordance with an embodiment of the present disclosure.

Detailed ways

Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The present invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will also be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on the other element or layer. or directly connected to another element or layer, or elements or layers may be present therebetween. And when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" may refer to a physical, electrical, and/or fluid connection with or without intervening elements.

Throughout the specification, the same reference numerals refer to the same components. In the drawings, the thickness of layers and regions are exaggerated for clarity.

Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of one or more embodiments. Description of an element as a "first" element may not require or imply the presence of a second or other element. The terms "first," "second," etc. may also be used herein to distinguish between different classes or groups of elements. For the sake of brevity, the terms "first", "second", etc. may mean "a first category (or first group)", "second category (or second group)", etc., respectively.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the term "comprising" specifies the presence of stated features, regions, steps, operations, elements and/or components, but does not exclude one or more other features, regions, The presence or addition of steps, operations, elements, components and/or groups thereof.

Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In example embodiments, when the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both "lower" and "upper" orientations, depending on the particular orientation of the figures. Similarly, when the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "under" can encompass both an orientation of above and below.

As used herein, "about" or "approximately" includes the stated value as well as by one of ordinary skill in the art when taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, limitations of the measurement system) The average value within the acceptable deviation of the determined specific value. For example, "about" can mean within one or more standard deviations.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It is also to be understood that terms, such as those defined in commonly used dictionaries, should be construed to have meanings consistent with their meanings in the relevant art and in the context of the present invention, and unless explicitly so defined herein, Will not be interpreted in an idealized or overly formalized sense.

Some exemplary implementations are described and illustrated in the drawings in terms of functional blocks, units and/or modules, as is customary in the art. Those skilled in the art will understand that these blocks, units and/or modules are connected by wiring such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. The electrical circuit (or optical circuit) of the device or the like is physically realized. Where the blocks, units and/or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled with software (eg, microcode) to perform the various functions discussed herein, and may optionally They are driven by firmware and/or software. It is also contemplated that each block, unit and/or module may be implemented by special purpose hardware, or as special purpose hardware for performing some functions and a processor for performing other functions (eg, one or more programmed a combination of a microprocessor and associated circuitry). Additionally, each block, unit and/or module in some example embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the scope of the inventive concepts or modules. Furthermore, the blocks, units and/or modules in some example embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concepts.

FIG. 1 shows a schematic diagram of a flash memory 100 according to an embodiment of the present disclosure. The flash memory 100 includes M×N memory cells C(1,1) to C(M,N), where M and N are positive integers. Taking NAND flash memory as an example, memory cells in the same column (for example, C(1,1) to C(M,1)) can be connected in series to the same bit line (for example, bit line BL1 ), and the memory cell strings connected in series have One end may be connected to the bit line via the bit line transistor Tb, and the other end may be connected to the source line via the source line transistor Ts. Each bit line connects the corresponding memory cell string to the sensing circuit 200 . Memory cells located in the same row (eg, C(M,1) to C(M,N)) may be connected to the same word line (eg, word line WLM). During operation, the memory cell string in which the memory cell to be detected is located is selected by the bit line transistor Tb and/or the source line transistor Ts, and the memory cell to be detected in the memory cell string is selected by applying a read voltage on the word line , and then the sensing circuit 200 reads the voltage or current on the corresponding bit line to determine the storage state of the memory cell to be detected. Taking the read memory cell C(M, N) as an example, by turning on the bit line transistor Tb and source line transistor Ts corresponding to the bit line BLN, the read voltage is applied on the word line WLM, and the read voltage is applied on the other word lines. A pass voltage is applied to select the memory cell C(M,N) to be detected, and then the voltage or current on the bit line BLN is read by the sensing circuit 200 to determine the storage state (eg, erased state/programmed) of the selected memory cell status, or "1"/"0").

FIG. 2 shows a schematic diagram of a sensing circuit 200 according to an embodiment of the present disclosure.

As shown in FIG. 2 , the sensing circuit 200 according to an embodiment of the present disclosure may include a first switch T ₁ , a second switch T ₂ , an isolation switch T _iso and a state determination unit SA. The input terminal of the first switch T ₁ may be directly or indirectly connected to the system voltage source V _DD , and the output terminal of the first switch T ₁ may be connected to the input terminal of the isolation switch T _iso . The input terminal of the isolation switch T _iso may be connected to the output terminal of the first switch T ₁ , and the output terminal of the isolation switch T _iso may be connected to the sensing node SO, the state determination unit SA and the input terminal of the second switch T ₂ . The output terminal of the _second switch T2 can be connected to the bit line BL of a certain memory cell string in the flash memory. For example, the output terminal of the _second switch T2 may be connected to the bit line BL of a certain memory cell string in the flash memory through the _third switch T3. In some embodiments, the sensing circuit 200 may further include a _fourth switch T ₄ , the input terminal of which may be directly or indirectly connected to the system voltage source V _DD , and the output terminal of the fourth switch T ₄ may be Connected to the output of the _second switch T2 and the input of the _third switch T3.

The first switch T ₁ , the second switch T ₂ , the third switch T ₃ and the fourth switch T ₄ included in the sensing circuit 200 may be metal oxide semiconductor (MOS) transistors. In some embodiments, the first switch T ₁ may be a P-type MOS transistor, and the isolation switch T _iso , the second switch T ₂ , the third switch T ₃ and the fourth switch T ₄ may be N-type MOS transistors. The state determination unit SA may include a MOS transistor, and the gate thereof may be connected to the sensing node SO. However, the state determination unit SA is not limited thereto, and it may also include other devices such as latches. In this case, the input terminal of the _first switch T1 can be the source of the transistor, the output terminal of the _first switch T1 can be the drain of the transistor, and the gate of the first switch T1 is used to receive control of its conduction On and off control signal Prechb; the input terminal of the isolating switch T _iso can be the source of the transistor, the output terminal of the isolating switch T _iso can be the drain of the transistor, and the gate of the isolating switch T _iso is used to receive the control signal. Turn on and off control signal Prech_isob; the input end of the second switch T ₂ can be the source of the transistor, the output end of the second switch T ₂ can be the drain of the transistor, and the gate of the second switch T ₂ is to receive the control signal Vsoblk that controls its on and off; the input terminal of the _third switch T3 can be the source of the transistor, the output terminal of the _third switch T3 can be the drain of the transistor, and the output terminal of the _third switch T3 can be the drain of the transistor. The gate is used to receive the control signal Vblbias that controls its turn-on and turn-off; the input end of the fourth switch T ₄ can be the source of the transistor, the output end of the fourth switch T ₄ can be the drain of the transistor, and the fourth switch T 4 can be the drain of the transistor. _The gate of the switch T4 is used to receive the control signal Vblclamp that controls its turn-on and turn-off.

In the sensing circuit 200 according to the present embodiment, a parasitic capacitance C SO may be formed between the sensing node SO or the output terminal of the first switch T ₁ and the ground, and a parasitic capacitance C _SO may be formed between the bit line BL and the ground Capacitance C _bl .

The operation method of the sensing circuit shown in FIG. 2 will be described below with reference to FIGS. 3 and 4 .

FIG. 3 shows a timing diagram of control signals for the sensing circuit in FIG. 2 according to an embodiment of the present disclosure; FIG. 4 shows a timing diagram of a method for operating the sensing circuit in FIG. 2 according to an embodiment of the present disclosure. flow chart.

2 to 4 , when the sensing circuit 200 is operating, according to the method 400 , first, at step S401 , the first switch T ₁ and the isolation switch T _iso are turned on to charge the sensing node SO with the system voltage . For example, the first switch T ₁ and the isolating switch T _iso may be turned on at a first time point t ₁ to charge the sense node SO with the system voltage, while the second switch T ₂ is in an off state (also referred to as is "open"). In the case where the _first switch T1 is _a P-type MOS transistor, the isolation switch _Tiso and the _second switch T2 are N-type MOS transistors, as shown in FIG. The high-level control signal Prechb is applied to the gate of the isolation switch T _iso , and the high-level control signal Prech_isob is applied to the gate of the second switch T ₂ , and the low-level control signal Vsoblk is applied to the gate of the second switch T 2, so that the first switch T ₁ and the isolating switch T _iso is conducting, and the second switch T ₂ is in the off state (also referred to as the "open state"). The first switch T ₁ and the isolating switch T _iso that are turned on electrically connect the sensing node SO with the system voltage source _VDD , and the sensing node SO is charged to the system voltage after a period of time.

Then, at step S402, the first switch T ₁ and the isolation switch T _iso are turned off. For example, the first switch T ₁ and the isolating switch T _iso may be opened at the second point in time t ₂ . In the case where the first switch T1 is _a P-type MOS transistor and the isolation switch T _iso is an N-type MOS transistor, as shown in FIG. 3 , a high-level control signal Prechb can be applied to the gate of the _first switch T1 , and a low-level control signal Prech_isob is applied to the gate of the isolation switch T _iso , so that the first switch T ₁ and the isolation switch T _iso are turned off. At this time, the voltage of the sensing node is the system voltage.

At step S403, the second switch T ₂ is turned on, so that the sensing node SO is electrically connected to the memory cell string. For example, the second switch T ₂ may be turned on at the third time point t ₃ . When the second switch T ₂ is an N-type MOS transistor, as shown in FIG. 3 , the second switch T ₂ can be turned on by applying a high-level control signal Vsoblk to the gate of the second switch T ₂ . At this time, the voltage of the sensing node SO may vary according to the storage state of the to-be-detected memory cell selected by the word line in the memory cell string. For example, the sensing node SO may be discharged through the memory cell string as the sensing current Isense is generated, and in the process, the voltage of the sensing node SO also decreases.

At step S404, the _second switch T2 is turned off. For example, the second switch T ₂ may be turned off at the fourth time point t ₄ after the sensing node SO is discharged for a period of time. When the second switch T ₂ is an N-type MOS transistor, as shown in FIG. 3 , the second switch T ₂ can be turned off by applying a low-level control signal Vsoblk to the gate of the second switch T ₂ . At this time, the electrical connection between the sensing node SO and the memory cell string is disconnected.

Since the change of the voltage of the sensing node SO may be different according to the storage state of the memory cell to be detected, the storage to be detected can be determined by detecting the voltage at the sensing node SO after the sensing node SO is discharged at step S405 The storage state of the unit. This detection can be performed by the state determination unit SA after the _fourth point in time t4. In some embodiments, the storage state of the memory cell to be detected can be determined by comparing the voltage of the sensing node SO with a reference voltage. For example, when the voltage of the sensing node SO is higher than the reference voltage, it may be determined that the memory cell is in the program state or "0", and when the voltage of the sensing node SO is lower than the reference voltage, it may be determined that the memory cell is in the erased state or "0"1". For the case where the state determination unit SA includes a MOS transistor, the gate threshold voltage of the MOS transistor can be used as a reference voltage, and the storage state of the memory cell to be detected can be determined by the switching state of the MOS transistor in the state determination unit SA.

In the case where the sensing circuit 200 includes the _third switch T3 and the _fourth switch T4, the states of the _third switch T3 and the _fourth switch T4 can be controlled by the control signals Vblclamp and Vblbias, respectively. The three switches T ₃ and the fourth switch T ₄ may be in a conducting state. At the above step S401, while the sensing node SO is charged to the system voltage capacitance, C _bl is also charged, eg, to Vblbias-Vth, where Vth is the threshold voltage of the third switch T ₃ .

FIG. 5 shows a schematic diagram of a sensing circuit according to another embodiment of the present disclosure. Compared with the sensing circuit 200 shown in FIG. 2 , the sensing circuit 500 shown in FIG. 5 is different in that a boost driver Boost is provided at the sensing node SO, which is connected to the sensing node SO and configured as A boost voltage is provided to the sense node SO. A parasitic capacitance C _SO may be formed between the sensing node SO or the output terminal of the first switch and the boost driver Boost.

FIG. 6 shows a timing diagram of control signals for the sensing circuit in FIG. 5 according to an embodiment of the present disclosure; FIG. 7 shows a timing diagram of a method for operating the sensing circuit in FIG. 5 according to an embodiment of the present disclosure. flow chart.

The operation method of the sensing circuit shown in FIG. 5 will be described below with reference to FIGS. 6 and 7 .

4 to 7 , when the sensing circuit 500 is operating, according to the method 700, first, at step S701, the first switch T ₁ and the isolation switch T _iso are turned on to charge the sensing node OS with the system voltage . For example, the first switch T ₁ and the isolating switch T _iso may be turned on at a first time point t ₁ to charge the sense node SO with the system voltage, while the second switch T ₂ is in an off state (also referred to as is "open"). In the case where the first switch T1 is _a P-type MOS transistor, the isolation switch T _iso and the _second switch T2 are N _- type MOS transistors, as shown in FIG. The high-level control signal Prechb is applied to the gate of the isolation switch T _iso , and the high-level control signal Prech_isob is applied to the gate of the second switch T ₂ , and the low-level control signal Vsoblk is applied to the gate of the second switch T 2, so that the first switch T ₁ and the isolating switch T _iso is conducting, and the second switch T ₂ is in the off state (also referred to as the "open state"). The first switch T ₁ and the isolating switch T _iso that are turned on electrically connect the sensing node SO with the system voltage source _VDD , and the sensing node SO is charged to the system voltage after a period of time.

Then, at step S702, the first switch T ₁ and the isolation switch T _iso are turned off. For example, the first switch T ₁ and the isolating switch T _iso may be opened at the second point in time t ₂ . When the first switch T1 is _a P-type MOS transistor and the isolation switch _Tiso is an N-type MOS transistor, as shown in FIG. 6 , a high-level control signal Prechb can be applied to the gate of the _first switch T1 , and a low-level control signal Prech_isob is applied to the gate of the isolation switch T _iso , so that the first switch T ₁ and the isolation switch T _iso are turned off. At this time, the voltage of the sensing node is the system voltage.

At step S703, a boost voltage is applied to the sense node SO. For example, as shown in FIG. 6 , at a fifth time point t ₅ after the second time point t ₂ , the boost driver Boost may start to output a high-level output voltage Vboost so that the voltage at the sensing node SO increases.

At step S704, the second switch T ₂ is turned on, so that the sensing node SO is electrically connected to the memory cell string. For example, the second switch T ₂ may be turned on at the third time point t ₃ . When the second switch T ₂ is an N-type MOS transistor, as shown in FIG. 6 , the gate of the second switch T ₂ can be turned on by applying a high-level control signal Vsoblk to the gate of the second switch T ₂ . At this time, the voltage of the sensing node SO may vary according to the storage state of the to-be-detected memory cell selected by the word line in the memory cell string. For example, the sensing node SO may be discharged through the memory cell string 210 as the sensing current Isense is generated, and the voltage of the sensing node SO is also reduced in the process.

At step S705, the _second switch T2 is turned off. For example, the second switch T ₂ may be turned off at the fourth time point t ₄ after the sensing node SO is discharged for a period of time. When the second switch T ₂ is an N-type MOS transistor, as shown in FIG. 6 , the second switch T ₂ can be turned off by applying a low-level control signal Vsoblk to the gate of the second switch T ₂ . At this time, the electrical connection between the sensing node SO and the memory cell string 210 is disconnected.

At step S706, the boost voltage is lowered. For example, as shown in FIG. 6 , at a sixth time point t ₆ after the fourth time point t ₄ , the boost driver Boost may reduce the output voltage Vboost, eg, reduce the output voltage Vboost by ΔV, or change it to 0.

Then, the storage state of the memory cell to be detected may be determined by detecting the voltage at the sensing node SO at step S707. This detection can be performed by the state determination unit SA after the fourth point in time _t6 . In some implementations, the storage state of the memory cell can be determined by comparing the voltage of the sense node SO with a reference voltage. For example, when the voltage of the sensing node SO is higher than the reference voltage, it may be determined that the memory cell is in the program state or "0", and when the voltage of the sensing node SO is lower than the reference voltage, it may be determined that the memory cell is in the erased state or "0"1". For the case where the state determination unit SA includes a MOS transistor, its gate threshold voltage can be used as a reference voltage, and the storage state of the memory cell can be determined by the switching state of the MOS transistor in the state determination unit SA.

In the case where the sensing circuit 500 includes the _third switch T3 and the _fourth switch T4, the states of the _third switch T3 and the _fourth switch T4 can be controlled by the control signals Vblclamp and Vblbias, respectively. The three switches T ₃ and the fourth switch T ₄ may be in a conducting state. At the above step S701, while the sensing node SO is charged to the system voltage capacitance, C _bl is also charged, eg, to Vblbias-Vth, where Vth is the threshold voltage of the third switch T ₃ .

The sensing circuit 500 according to the above-mentioned embodiment increases the voltage at the sensing node through the boost driver during the sensing process, which makes the voltage at the sensing node SO corresponding to different storage states of the memory cell to be detected have a larger value separation space, which improves reading accuracy. At the same time, since the isolation switch T _iso is set in the sensing circuit 500 , which isolates the first switch T ₁ from the sensing node when boosting with the boost driver, it is possible to avoid possible occurrence due to the voltage at the sensing node The current leakage occurs when the voltage is higher than the system voltage, so that the N-well provided separately at the _first switch T1 can be omitted, which can reduce the design size of the sensing circuit.

By the end of the detailed description, those skilled in the art will understand that many changes and modifications of the preferred embodiments can be made without substantially departing from the principles of the present invention. Accordingly, the disclosed preferred embodiments of the present invention are used in a general and descriptive sense only and not for purposes of limitation.

Claims (26)

1. A sensing circuit comprising a first switch, a second switch, a disconnector, a state determining unit, and a boost driver, wherein:

the first switch includes:

an input terminal connected to a system voltage source; and

an output connected to an input of the isolation switch;

the disconnecting switch comprises:

an input connected to an output of the first switch; and

an output connected to a sensing node adapted to connect with a memory cell to be sensed;

the second switch includes:

an input connected to an output of the isolation switch; and

an output adapted to be connected to a memory cell string comprising said memory cells to be tested,

the state determining unit is connected to the sensing node and configured to determine a storage state of the memory cell to be detected according to a voltage of the sensing node, an

The boost driver is connected to the sense node and configured to provide a boost voltage that boosts the voltage of the charged sense node,

wherein the isolation switch is configured to open at least during the time that the boost driver is providing the boost voltage.

2. The sensing circuit of claim 1, wherein the isolation switch is a low voltage N-type device.

3. The sensing circuit of claim 2, wherein the isolation switch is a low voltage nmos transistor.

4. The sensing circuit as claimed in claim 1, wherein the state determining unit is configured to determine the storage state of the memory cell to be detected by comparing the voltage of the sensing node with a reference voltage.

5. The sensing circuit of claim 1, wherein the sensing circuit further comprises a third switch comprising:

an input connected to an output of the second switch; and

an output connected to the string of memory cells.

6. The sensing circuit of claim 5, wherein a parasitic capacitance is formed between the output of the third switch and ground.

7. The sensing circuit of claim 5, wherein the sensing circuit further comprises a fourth switch comprising:

an input connected to the system voltage source; and

an output connected to an input of the third switch.

8. The sensing circuit of claim 7, wherein the first switch, the second switch, the third switch, and the fourth switch are metal oxide semiconductor transistors.

9. The sensing circuit of claim 8, wherein the first switch is a P-type metal oxide semiconductor transistor.

10. The sensing circuit of claim 8, wherein the second, third, and fourth switches are nmos transistors.

11. The sensing circuit as claimed in claim 10, wherein a parasitic capacitance is formed between the output of the isolation switch and the boost driver.

12. The sensing circuit as claimed in claim 1, wherein a parasitic capacitance is formed between the output terminal of the isolation switch and ground.

13. A method of determining a memory state of a memory cell to be detected by a sensing circuit, the sensing circuit comprising a first switch, a second switch, a disconnector and a state determination unit, wherein an input of the first switch is adapted to receive a system voltage from a system voltage source, an output of the first switch is connected to an input of the disconnector, an output of the disconnector is connected to a sensing node and an input of the second switch, an output of the second switch is connected to a string of memory cells comprising the memory cell to be detected, the method comprising:

turning on the first switch and the isolation switch at a first time point to charge the sensing node with the system voltage;

opening the first switch and the disconnector at a second point in time;

applying a boosted voltage to the sensing node at a fifth point in time between the second point in time and the third point in time to boost the voltage of the sensing node;

turning on the second switch at a third time point such that the sensing node is electrically connected with the memory cell string;

opening the second switch at a fourth point in time;

decreasing the boosted voltage at a sixth time point after the fourth time point; and

and determining the storage state of the storage unit to be detected according to the voltage of the sensing node after the sixth time point.

14. The method of claim 13, the sensing circuit further comprising a boost driver connected to the sensing node, the boost driver configured to apply the boost voltage to the sensing node.

15. The method of claim 14, wherein a parasitic capacitance is formed between the output of the isolation switch and the boost driver.

16. The method of claim 13, wherein the isolation switch is a low voltage N-type device.

17. The method of claim 16, wherein the isolation switch is a low voltage nmos transistor.

18. The method of claim 13, wherein determining the storage state of the memory cell to be tested comprises:

determining a storage state of the memory cell to be detected by comparing a voltage of the sensing node with a reference voltage.

19. The method of claim 13, the sensing circuit further comprising a third switch, the third switch comprising:

an input connected to an output of the second switch; and

an output connected to the string of memory cells.

20. The method of claim 19, wherein a parasitic capacitance is formed between the output of the third switch and ground.

21. The method of claim 19, the sensing circuit further comprising a fourth switch comprising:

an input connected to the system voltage source; and

an output connected to an input of the third switch.

22. The method of claim 21, wherein the first switch, the second switch, the third switch, and the fourth switch are metal oxide semiconductor transistors.

23. The method of claim 22, wherein the first switch is a pmos transistor.

24. The method of claim 22, wherein the second switch, the third switch, and the fourth switch are nmos transistors.

25. The method of claim 13, wherein a parasitic capacitance is formed between an output terminal of the isolation switch and ground.

26. A flash memory, comprising:

a plurality of memory cells arranged in an array; and

a plurality of the sensing circuits of any of claims 1-12, respectively connected to each column of memory cells of the plurality of memory cells.

Images