CN112506476B - A fast architecture method and device for a digital twin workshop system - Google Patents

Abstract

The invention provides a fast architecture method for a digital twin workshop system, which includes forming a process file with workshop production logic and manufacturing procedures according to the extracted dynamic process data of a manufacturing workshop, and constructing a logical data model of the workshop according to the process file; The geometric model data of the manufacturing workshop is collected, and the geometric data modeling of the digital twin workshop is completed by means of geometric modeling. Based on shader coding, the geometric model data is transferred from the CPU memory to the pre-allocated buffer area of the GPU, and the coordinate transformation of the geometric model in the twin space is preset through matrix transformation; the CPU calculates the dynamic logical data and sends the data to the GPU. Send graphics rendering instructions to make the GPU interact with the geometry model data in the pre-allocated buffer in multiple batches. In the invention, the dynamic logic data and geometric model data of the twin system are calculated in parallel, and the problem of delayed mapping caused by the large amount of data in the digital twin workshop system can be solved.

Description

A fast architecture method and device for digital twin workshop system

technical field

The invention relates to the technical field of digital manufacturing, and in particular, to a method and a device for rapid architecture of a digital twin workshop system.

Background technique

Digital twin (DT) is a key technology that uses digital models to mirror physical systems in virtual space. The simulation analysis of physical quantity, multi-scale and multi-probability faithfully reflects the whole life cycle process of the corresponding entity, and realizes digital analysis, simulation, operation and maintenance and management.

At present, digital twin is a cutting-edge technology in the field of cyber-physical systems in the world, and has broad application prospects in electric power, urban planning, building construction, industrial manufacturing and other fields. In the early days, the establishment of the digital twin system focused on the creation of geometric models, data transmission and service analysis. The built models were mainly static objects, and the models did not have cooperative motion attributes, and the data content and form were relatively simple. However, for industrial manufacturing systems, due to the existence of manufacturing processes and manufacturing processes, when modeling a digital twin system, in addition to a large number of static geometric model data, there are also a large number of dynamic attribute data, that is, the production process introduced by the manufacturing process. , process and other logical data, it is necessary to model the motion matching relationship, which increases the complexity of resource consumption and model construction, resulting in the early digital twin system not suitable for industrial manufacturing. Therefore, with the increase in the amount of data and the operation requirements of the twin system, how to quickly construct the digital twin system and ensure the fidelity and real-time performance of the twin relationship has become one of the keys to the development of digital twin technology in the manufacturing field.

The establishment of a digital twin system depends on the processing and calculation of a large amount of model data, especially in the manufacturing field, which includes a large number of model data of static attributes and logical data of dynamic attributes. Quickly calculating data and improving execution efficiency are the keys to ensuring the faithful and real-time mapping relationship of the twin system. The key to this, so far there is little research in this area. At the same time, considering that the processing of geometric model data and dynamic logic data by the digital twin system mainly relies on CPU and GPU, it is necessary to reasonably allocate computing resources and computing tasks. Otherwise, the execution efficiency of the digital twin system cannot be improved, resulting in a twin system. Lazy mapping problem.

SUMMARY OF THE INVENTION

The technical problem to be solved by the embodiments of the present invention is to provide a fast architecture method and device for a digital twin workshop system. Data parallel computing solves the problem of delayed mapping of the twin system caused by the large amount of operation data in the digital twin workshop system.

In order to solve the above-mentioned technical problem, the embodiment of the present invention provides a fast architecture method for a digital twin workshop system, including the following steps:

S1. According to the extracted dynamic process data of the manufacturing workshop, a process file with workshop production logic and manufacturing procedures is formed, and a logical data model of the workshop is constructed according to the process file; the geometric model data of the manufacturing workshop is collected through an embedded data controller, etc. Geometric data modeling of digital twin workshop;

S2. Transfer the geometric model data from the CPU memory to the pre-allocated buffer area of the GPU based on shader coding, and preset the coordinate transformation of the geometric model in the twin space through matrix transformation;

S3. While calculating the dynamic logical data, the CPU sends graphics rendering instructions to the GPU, so that the GPU interacts with the geometric model data in the pre-allocated buffer area in multiple batches, completes the parallel calculation of the geometric model data, and obtains the rendered digital twin workshop .

Wherein, the geometric model data of the manufacturing workshop is collected through various tools such as an embedded data controller, a sensor network, a data acquisition card and an industrial camera.

Wherein, the dynamic process data of the workshop includes data such as workshop production logic and manufacturing procedures. The geometric model data includes the texture, position, size and size of the workshop model.

Wherein, the step S3 specifically includes:

While calculating the dynamic logical data, the CPU sends graphics rendering instructions to the GPU. After the GPU obtains the CPU graphics calling rendering instructions, the GPU interacts with the geometric model data in the pre-allocated buffer in multiple batches, and reads the pre-allocated data in batches. Allocate the vertex data and rendering state of the geometric model data in the buffer area to complete the multi-batch rendering of the model. And through the corresponding matrix operation, determine the size and position of the model rendered in each batch;

The embodiment of the present invention also provides a rapid architecture device for a digital twin workshop system, including:

The data modeling module forms a process file with workshop production logic and manufacturing procedures according to the extracted dynamic process data of the manufacturing workshop, and constructs a logical data model of the workshop; collects the geometric model data of the manufacturing workshop through an embedded data controller, etc., to complete the described Geometric data modeling of digital twin workshops.

The data transfer module, based on the shader coding method, transfers the geometric model data, including vertex patches and other data from the CPU memory to the pre-allocated buffer area of the GPU, and determines the rendered data through the matrix operation in the pre-allocated buffer area of the GPU. the size and location of the geometric model;

Parallel computing module, the CPU sends graphics rendering instructions to the GPU while calculating the dynamic logical data, so that the GPU interacts with the geometric model data in the pre-allocated buffer in multiple batches, and reads the geometric models in the pre-allocated buffer in batches. Vertex data and rendering state of the data to complete the multi-batch rendering of the model. And through the corresponding matrix operation, determine the size and position of the model rendered in each batch;

Wherein, the geometric model data of the manufacturing workshop is collected through various tools such as an embedded data controller, a sensor network, a data acquisition card and an industrial camera.

Wherein, the dynamic process data of the workshop includes data such as workshop production logic and manufacturing procedures. The geometric model data includes the texture, position and size of the workshop model.

Implementing the embodiment of the present invention has the following beneficial effects:

By establishing a pre-allocated buffer area in the GPU, the invention separates the geometric model data operation in the digital twin workshop from the CPU, so that the frequent interaction between the CPU and the GPU caused by a large number of model rendering work is transformed into the GPU and its pre-processing. Allocating data exchange between buffer areas saves the computing resources of the CPU, so that the CPU can centrally process the logic data (ie dynamic logic data) in the digital twin workshop, and realize the parallel computing of the twin workshop data between the CPU and the GPU, thereby Realize the reasonable allocation of the resources occupied by the geometric model data and dynamic logic data, realize the parallel computing of the twin workshop data by CPU and GPU, and solve the twin system delay mapping problem caused by the large amount of operation data of the digital twin workshop system.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and for those of ordinary skill in the art, obtaining other drawings according to these drawings still belongs to the scope of the present invention without any creative effort.

1 is a flowchart of a method for fast architecture of a digital twin workshop system provided by an embodiment of the present invention;

2 is a logic diagram of parallel computing of logic and model data in an application scenario of a digital twin workshop system fast architecture method provided by an embodiment of the present invention;

3 is a schematic diagram of a CPU model data transmission process in an application scenario of a fast architecture method for a digital twin workshop system provided by an embodiment of the present invention;

4 is a schematic diagram of a GPU model data processing process in an application scenario of a fast architecture method for a digital twin workshop system provided by an embodiment of the present invention;

5 is a flowchart of a rendering process of a digital twin workshop in an application scenario of a fast architecture method for a digital twin workshop system provided by an embodiment of the present invention;

6 is a comparison diagram of the operation effect of the circuit breaker digital twin workshop in the application scenario of the fast architecture method of the digital twin workshop system provided by the embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a rapid architecture device for a digital twin workshop system provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

As shown in FIG. 1, it is a fast architecture method for a digital twin workshop system proposed in an embodiment of the present invention, including the following steps:

Step S1, according to the extracted dynamic process data of the manufacturing workshop, a process file with workshop production logic and manufacturing procedures is formed, and a logical data model of the workshop is constructed; the geometric model data of the manufacturing workshop is collected through an embedded data controller, etc., to complete the digital twin. Geometric data modeling of the workshop.

The specific process is that the workshop environment and production process of general industrial manufacturing workshops are relatively complex, there are many internal parts in the workshop, and the production process is complicated. In order to build a digital twin workshop in a virtual environment, it is necessary to accurately model and faithfully model the physical geometric information of the manufacturing workshop. map.

First, the geometric model data and dynamic process data of the workshop are collected through various tools such as embedded data controllers, sensor networks, data acquisition cards and industrial cameras to form process files and build a logical data model of the workshop; The geometric model data includes but is not limited to the texture, position and size of the workshop global model, and the information data is static model data; the production logic information includes but is not limited to the production process and steps of the workshop dynamic production line, and the production logic information data is dynamic logical data.

Second, build a digital twin workshop based on the information model. For example, collect the geometric information of the information model, including the geometric model data of the workshop and dynamic process data, build a twin geometric model (ie digital twin workshop) in a virtual environment, and perform mesh merging and optimization on the model to prepare for the construction of the scene. .

Step S2 transfers the geometric model data from the CPU memory to the pre-allocated buffer area of the GPU based on shader coding, and presets the coordinate transformation of the geometric model in the twin space through matrix transformation.

The specific process is that the architecture of the digital twin workshop relies on the support of a large number of geometric models and logical models with dynamic attributes. The computer needs to give enough CPU resources to the dynamic logical data with high complexity to achieve a high degree of coupling between the logical behaviors of the models.

In the traditional digital twin workshop based on CPU operation, the CPU needs to process a large amount of geometric model data and logic data at the same time, which makes the system memory pressure high and the CPU load is too heavy, which is easy to cause the problem of digital twin delay mapping.

In view of the fact that the GPU contains hundreds of stream processors, which are suitable for parallel data computing, it is proposed to establish a pre-allocated buffer area in the GPU to separate the static model operations of the workshop from the CPU (that will be mapped in the digital twin workshop). The model data is transferred to the GPU pre-allocated buffer area), thereby converting the frequent interaction between the CPU and the GPU into the data exchange between the GPU and the pre-allocated buffer area, avoiding CPU resource consumption. At the same time, based on the actual manufacturing process and process flow, the logic planning is carried out, and the constraint rules and dynamic logic data of production behavior are established. The CPU can centrally process the logic data, realize the parallel computing of the twin workshop data between the CPU and the GPU, and improve the computing efficiency. .

Step S3: While calculating the dynamic logic data, the CPU sends a graphics rendering instruction to the GPU, so that the GPU interacts with the geometric model data in the pre-allocated buffer area in multiple batches, completes the parallel calculation of the geometric model data, and obtains the rendered digital twin. workshop.

The specific process is that the CPU sends graphics rendering instructions to the GPU while calculating the dynamic logical data. After the GPU obtains the CPU graphics call rendering instructions, the GPU performs multiple batches of interactive calculation with the geometric model data in the pre-allocated buffer area. Read the vertex data and rendering state of the geometric model data in the pre-allocated buffer at one time, and complete the multi-batch rendering of the model. And through the corresponding matrix operation, determine the size and position of the model rendered in each batch;

In the embodiment of the present invention, the process flow and production logic of the manufacturing workshop are mainly calculated by the CPU, and the specific implementation methods include a state machine, collision detection, and the like. In addition, the CPU also requires the processing and computation of the geometric model data. As shown in Figure 2, all the dynamic logic data for realizing the dynamic production line is loaded into the memory from the disk, and then transferred to the video memory storage of the GPU. The GPU reads the vertex data and rendering state in the pre-allocated buffer area in batches according to the received CPU rendering command, and the size and position of the preset model in the virtual space through the matrix transformation in the buffer area. Finally, the production logic picture of the workshop production line is dynamically rendered on the user interface.

Considering that the workshop geometric model data conforms to the data characteristics of parallel computing, a large amount of model computing work is separated to the GPU by means of shader coding, and a part of the buffer area is pre-allocated in the GPU video memory for the GPU to read and write, and the CPU only needs to be responsible for notifying The GPU interacts with data in preallocated buffers. As shown in Figure 3, for the transfer process of the geometric model data from the CPU side, a large amount of geometric model data (DATA2) in the digital twin workshop is loaded from the disk to the memory, and then transferred to the pre-allocated buffer area through transmission, storage, etc. Where DATA2 contains the vertex information and rendering state of the geometric model.

As shown in Figure 4, for the processing process of the geometric model data on the GPU side, the CPU stores the data information of the geometric model in the pre-allocated buffer area of the GPU. The vertex data and rendering state in the multi-batch are read in multiple batches, and the size and location of the model rendered in the rendering batch are determined through corresponding matrix operations, so as to realize the parallel processing of logic and model data, and complete the construction of the digital twin workshop, such as shown in Figure 5.

It should be noted that there are three main types of world coordinate transformations (ie vertex transformations) of twins in virtual space: translation, scaling and rotation. The workshop model with dynamic logical attributes will preset its motion trajectory in the CPU memory, The invention transplants the geometric model data into the GPU buffer area, and through the combination of several transformation matrices in the buffer area, the translation, rotation and scaling can be combined, and the state of the static model data can be arbitrarily planned in the virtual space to realize the corresponding production. Faithful mapping of logic, manufacturing process.

As shown in formula (1), using the homogeneous coordinate representation, any vector (x, y, z) in the scene can be translated by (t _x , t _y , t _z ) distance on each coordinate axis in space.

Assuming that the scaling factor is (k _x , k _y , k _z ), if the three scaling coefficients k are equal, it is called uniform scaling, otherwise it is non-uniform scaling, which will stretch or squeeze the model, which will change the correlation with the model. In order to maintain the realism of the model in the scene, non-uniform scaling is generally not selected.

As shown in formula (2), any vector (x, y, z) is scaled (k _x , _ky , k _z ) times in space.

角度。As shown in formula (3), by using the rotation around the _X , _Y , and Z axes, the matrix that rotates along any axis can be deduced. ,R _z ) rotate

angle.

As shown in FIG. 6 , the application scenario of a fast architecture method for a digital twin workshop system in an embodiment of the present invention is further described:

In order to verify the results, taking the batch circuit breaker manufacturing workshop as the object, the proposed rapid architecture method of the digital twin workshop is verified and compared. Circuit breakers are commonly used in power distribution networks. They are electrical equipment that protects the safety of terminal power consumption. The annual demand is as high as billions.

The geometric structure of the miniature circuit breaker includes parts such as handle and magnetic system. Take a miniature circuit breaker manufacturing workshop with a daily output of more than 100,000 poles as an example. The workshop system includes 6 complete production lines, and a single production line contains 24 sets of equipment. There are a total of 144 manufacturing units, involving 4,860 assembly actions and 4,548 inspection actions. The manufacturing process includes 18 process processes such as automatic assembly, multi-stage riveting, and laser marking. The number of corresponding digital twin workshop geometric models is as high as 47,415. , including 6.39×10 ⁷ vertices and 6.71×10 ⁷ patches, which requires a large amount of computing resources.

The circuit breaker digital twin workshop includes mapping models such as the workshop storage model, the circuit breaker production line and the corresponding production line equipment. The geometric model data of the circuit breaker workshop is collected through the embedded data controller, etc., and the digital twin workshop is completed by the method of geometric modeling. geometric data modeling. According to the collected model information, the model of the circuit breaker workshop is analyzed, and the dynamic production logic of the production line is realized through the state machine, collision detection and operation logic control code calculation, so as to realize the three-dimensional reconstruction of the circuit breaker digital twin workshop.

The twin workshop visualization platform is developed in the software development environment, including the always-displayed workshop operation interface and the pop-up unit operation interface. Among them, the production data contained in the workshop operation status interface include: equipment operation status, planned assembly quantity, planned completion rate, one-time pass-through rate, OEE (comprehensive equipment efficiency) of each unit, equipment energy consumption and system real-time time, etc.; the operation interface contains The data include: unit name, equipment operation status, output, qualified rate, unqualified quantity, comprehensive equipment efficiency, etc. When a process in the physical workshop fails, through the sending and receiving of signals, the twin workshop will immediately interrupt the user operation, automatically jump to the faulty unit, and the faulty unit will stop the production process, realizing the real mapping with the physical system of the workshop. When the signal returns to normal, the system will stop the alarm and resume normal operation in synchronization with the physical circuit breaker workshop.

In order to compare and verify the performance of the built digital twin workshop system, the present invention is based on the Intel(R) Core(TM) i7-10510U CPU@1.80GHz 2.30GHz hardware environment to verify the proposed digital twin workshop fast architecture method. . Table 1 records that under the above-mentioned hardware conditions, the method based on the existing CPU serial calculation is compared with the method based on the parallel calculation of logic and model data proposed by the present invention, and the automatic pad printing, multi-level riveting, Processing results of units such as automatic piercing, automatic detection and laser marking.

Table 1

The four indicators of frames per second (FPS), Batches, CPU utilization and GPU utilization were compared respectively. FPS is the frequency of screen update per second when drawing the scene. The higher the frame rate, the smoother and more realistic the screen is. Usually the frame rate The interactive frame rate (30fps) is required, and the human eye will not be able to detect the change of the frame rate when the frame rate reaches 75fps. The process of calling the graphics rendering API by the CPU is called batch. The drawing of each primitive needs to call the drawing function, so the number of batches is increasing, and a large number of model drawing operations seriously affect the drawing efficiency. It can be seen from Table 1 that when rendering the number of 10302 models based on the CPU, it is difficult to meet the rendering requirements. However, with the architecture method proposed in this paper, when the number of models reaches 40032 under more logical process conditions, the FPS number is increased from 10.3 to 392, which is much higher than the frame rate perceived by the human eye, which improves the execution efficiency. In addition, due to the release of the CPU call frequency pressure, the number of corresponding batches has been reduced from 4810 to 10. The parallel architecture method improves the utilization efficiency of the GPU, and the utilization efficiency is increased from 65% to 97%, which greatly reduces the computing pressure of the CPU.

In Figure 6, for the comparison of the operation effect of the digital twin workshop of the whole circuit breaker, it can be seen from the comparison results that due to the parallel processing method, the GPU usage efficiency is improved, the computing burden of the CPU is released, and the processing of dynamic logic data is improved. , the running frame rate of the circuit breaker digital twin workshop increased to 387fps, much higher than the interactive frame rate requirement, the CPU utilization decreased by 31%, the GPU utilization increased by 21%, and the batches decreased from the original 6898 to 261. The optimization effect is obvious. .

As shown in FIG. 7, it is a fast architecture device for a digital twin workshop system proposed in an embodiment of the present invention, including:

The data modeling module forms a process file with workshop production logic and manufacturing procedures according to the extracted dynamic process data of the manufacturing workshop, and constructs a logical data model of the workshop; collects the geometric model data of the manufacturing workshop through an embedded data controller, etc., to complete the described Geometric data modeling of digital twin workshops.

The data transfer module, based on the shader coding method, transfers the geometric model data, including vertex patches and other data from the CPU memory to the pre-allocated buffer area of the GPU, and determines the rendered data through the matrix operation in the pre-allocated buffer area of the GPU. the size and location of the geometric model;

Parallel computing module, the CPU sends graphics rendering instructions to the GPU while calculating the dynamic logical data, so that the GPU interacts with the geometric model data in the pre-allocated buffer in multiple batches, and reads the geometric models in the pre-allocated buffer in batches. Vertex data and rendering state of the data to complete the multi-batch rendering of the model. And through the corresponding matrix operation, determine the size and position of the model rendered in each batch;

Wherein, the geometric model data of the manufacturing workshop is collected through various tools such as an embedded data controller, a sensor network, a data acquisition card and an industrial camera.

Wherein, the dynamic process data of the workshop includes data such as workshop production logic and manufacturing procedures. The geometric model data includes the texture, position and size of the workshop model. Implementing the embodiment of the present invention has the following beneficial effects:

The invention establishes a pre-allocated buffer area in the GPU, separates the geometric model data operation in the digital twin workshop from the CPU, and converts the frequent interaction between the CPU and the GPU into the data exchange between the GPU and its pre-allocated buffer area , saves the computing resources of the CPU, and the CPU can centrally process the logic data (ie dynamic logic data) in the digital twin workshop to realize the parallel computing of the twin workshop data between the CPU and the GPU, so as to realize the geometric model data and dynamic Reasonable allocation of resources occupied by logical data enables parallel computing of twin workshop data by CPU and GPU, and solves the problem of twin system delay mapping caused by the large amount of operational data in the digital twin workshop system.

It is worth noting that, in the above system embodiment, the units included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units It is only for the convenience of distinguishing from each other, and is not used to limit the protection scope of the present invention.

Those of ordinary skill in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium, and the storage medium , such as ROM/RAM, magnetic disk, CD, etc.

The above disclosure is only a preferred embodiment of the present invention, and of course, it cannot limit the scope of the rights of the present invention. Therefore, the equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims (4)

1. A rapid architecture method of a digital twin workshop system is characterized by comprising the following steps:

s1, forming a process file with a workshop production logic and a manufacturing procedure according to the extracted dynamic process data of the manufacturing workshop, and constructing a logic data model of the workshop through the process file; acquiring geometric model data of a manufacturing workshop, and completing geometric data modeling of the digital twin workshop through geometric modeling, wherein dynamic process data of the workshop comprise workshop production logic and manufacturing procedure data which are dynamic logic data, and the geometric model data comprise texture, position, dimension and size data of a workshop model;

s2, transferring the geometric model data from the CPU memory to a pre-allocation cache area of the GPU based on a shader coding mode, and presetting coordinate transformation of the geometric model in a twin space through matrix transformation;

s3, the CPU sends a graphic rendering instruction to the GPU while calculating the dynamic logic data, so that the GPU and the geometric model data of the pre-allocation cache area interact in multiple batches, parallel calculation of the geometric model data is completed, and a rendered digital twin workshop is obtained.

2. The method for rapid architecture of a digital twin plant system according to claim 1, wherein the geometric model data of the manufacturing plant is cooperatively collected by a plurality of tools including an embedded data controller, a sensor network, a data acquisition card and an industrial camera.

3. The digital twin plant system rapid architecture method according to claim 1, wherein the step S3 specifically includes:

the method comprises the steps that a CPU sends a graphic rendering instruction to a GPU while calculating dynamic logic data, after the GPU obtains a CPU graphic call rendering instruction, the GPU and geometric model data of a pre-allocation cache area carry out multi-batch interaction, vertex data and rendering states of the geometric model data in the pre-allocation cache area are read in batches, multi-batch rendering of the model is completed, and the size and the position of a rendered model in each batch are determined through corresponding matrix operation.

4. A digital twin workshop system fast architecture device, comprising:

the data modeling module is used for forming a process file with workshop production logic and manufacturing procedures according to the extracted dynamic process data of the manufacturing workshop and constructing a logic data model of the workshop; collecting geometric model data of a manufacturing workshop, and completing geometric data modeling of the digital twin workshop, wherein dynamic process data of the workshop comprise workshop production logic and manufacturing procedure data which are dynamic logic data, and the geometric model data comprise texture, position, dimension and size data of a workshop model;

the data transfer module transfers the geometric model data comprising the vertex patch data from the CPU memory to a pre-allocation cache area of the GPU based on a shader coding mode, and determines the size and the position of a rendered geometric model through matrix operation in the pre-allocation cache area of the GPU;

and the parallel computing module is used for sending a graphic rendering instruction to the GPU while the CPU computes the dynamic logic data, so that the GPU and the geometric model data of the pre-allocation cache region carry out multi-batch interaction, the vertex data and the rendering state of the geometric model data in the pre-allocation cache region are read in batches, multi-batch rendering of the model is completed, and the size and the position of the rendered model of each batch are determined through corresponding matrix operation.

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