CN112422675A - Heterogeneous processing platform flow control management method and device based on fpga - Google Patents
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Abstract
本发明提供一种基于fpga的异构处理平台流控管理方法及装置。该方法包括：接收器件向发送器件发送缓冲控制字符，所述缓冲控制字符用于指示当前时刻接收器件的剩余缓存空间大小；发送器件接收到所述缓冲控制字符后，设置各待传输事务流包的优先级，优先发送高优先级的事务流包。本发明利用反馈调节控制机制将接收器件的空闲缓冲数量反馈给发送器件，发送器件根据接收器件的反馈信息来重新调整事务流包的优先级属性，再分发给下一模块单元，大大增加了缓冲区的利用率。
The invention provides an FPGA-based heterogeneous processing platform flow control management method and device. The method includes: a receiving device sends a buffer control character to a sending device, where the buffer control character is used to indicate the size of the remaining buffer space of the receiving device at the current moment; after the sending device receives the buffer control character, setting each transaction stream packet to be transmitted The priority is to send high-priority transaction flow packets first. The invention uses the feedback adjustment control mechanism to feed back the idle buffer quantity of the receiving device to the sending device, and the sending device readjusts the priority attribute of the transaction flow packet according to the feedback information of the receiving device, and distributes it to the next module unit, which greatly increases the buffering capacity. area utilization.
Description
Technical Field
The invention relates to the technical field of heterogeneous processing platforms, in particular to a heterogeneous processing platform flow control management method and device based on fpga.
Background
With the rapid development of the current big data industry, the continuous update and iteration of high-speed AD/DA conversion, the appearance of high-frequency hot spots such as deep reinforcement learning and the like, higher requirements are provided for the operation processing capability and the data transmission capability of a computing platform, so that a single traditional computing platform cannot meet the processing and transmission of massive data, and a heterogeneous processing platform becomes the next research direction.
Compared with the traditional system architecture, the heterogeneous processing system architecture can coordinate multitask processing concurrently, can complete interactive fusion of a large amount of data, and has the capability of meeting the requirement of processing various complex tasks. Compared with the traditional architecture, the system is composed of a plurality of hardware processors aiming at specific application functions, and can provide more efficient processing capability for a plurality of different task requirements. In the heterogeneous processing platform, each processing module performs cooperative processing, so that the balance and high efficiency of data processing and transmission are particularly important in the heterogeneous processing platform.
Most of the existing strategies for traffic buffer management are to adjust and control the transmission rate by changing the transmission rate, and the rate of sending data is changed at different times, for example, when the sending end receives a reset signal, a packet reception confirmation character, a packet reception rejection character, or a time-out time changes the transmission rate, and when the link works normally and receives control characters normally received by a plurality of receiving ends, high-rate transmission is performed. However, when the traffic stream is transmitted too fast and the receiving device is not in time to process, the other party is required to reduce the transmission rate, and as soon as the device is jammed and the transmitting end continuously sends request inquiries, both ends are increasingly congested. Some strategies (for example, a flow control method and a switching device disclosed in chinese patent document CN 108243116A) are to transmit a pause frame to inform a transmitting end to stop transmitting data, and a duration of the pause transmission is determined according to a duration of a congestion state, so that efficiency of data transmission is greatly impaired.
In the above method, the pressure of the receiving device for processing the data packet is relieved by reducing the sending rate or stopping sending the data packet, so that the transmission efficiency of the whole system is reduced, and the space utilization rate of the buffer area is greatly reduced. Because the receiving device only transmits the confirmation or rejection characters to the opposite side to respond to the data stream transmission condition of the sender, no buffer information favorable for packet reception is provided for the sender, and the sender cannot judge whether the data sent by the sender is received correctly or incorrectly in advance, the data transmission capability of the whole system has great dependence on the data processing capability of the receiving device.
Disclosure of Invention
Aiming at the problems of low transmission efficiency and low space utilization rate of a buffer area in the conventional flow buffer area management method, the invention provides a heterogeneous processing platform flow control management method and device based on fpga.
In one aspect, the present invention provides a heterogeneous processing platform flow control management method based on fpga, including: the receiving device sends a buffer control character to the sending device, wherein the buffer control character is used for indicating the size of the residual buffer space of the receiving device at the current moment;
and after receiving the buffer control characters, the sending device sets the priority of each transaction flow packet to be transmitted and sends the transaction flow packet with high priority preferentially.
Further, when the size of the remaining buffer space of the receiving device is changed, the receiving device transmits the buffer control character to the transmitting device.
Further, the setting the priority of each transaction stream packet to be transmitted includes:
and if the transaction flow packet sent by the sending device is a request response signal, setting the priority of the request response signal as the priority of the highest level.
Further, still include: setting 4 priority thresholds for the size of the remaining buffer space of the receiving device in advance: p0, P1, P2, P3, P0> P1> P2> P3> 0;
the size of the remaining buffer space of the receiving device is represented as free _ buf _ cnt, and the transmission rule between the sending device and the receiving device is as follows:
if free _ buf _ cnt > is P0, transaction stream packets of all priorities can be transmitted;
if P0> free _ buf _ cnt > -P1, transaction stream packets with priorities of 1, 2 and 3 can be transmitted;
if P1> free _ buf _ cnt > -P2, transaction stream packets with priorities of 2 and 3 can be transmitted;
if P2> free _ buf _ cnt > -P3, the transaction stream packet with priority 3 can be transmitted;
if P3> free _ buf _ cnt >0, a response transaction stream packet can be transmitted.
Further, still include: presetting an indication signal output _ no _ received indicating that the transaction stream packet is sent but not received and an indication signal that the transaction stream packet is sent and received;
adding 1 to the value of output _ no _ received when the sending device sends a data packet, and subtracting 1 from the value of output _ no _ received when the sending device receives a receiving control character;
the size of the remaining buffer space of the receiving device at the current moment is equal to the total buffer space of the receiving device minus the value of output _ no _ received, and then minus the value of the indication signal that the transaction flow packet has been sent and has confirmed to receive.
Further, the transaction flow packet comprises an identifier ID and a PRIO priority character; the identifier ID is used to indicate the transfer order of each transaction stream packet, and the PRIO priority character is used to indicate the priority of the transaction stream packet.
On the other hand, the invention provides a heterogeneous processing platform flow control management device based on fpga, comprising:
the receiving end flow control management unit is arranged at the receiving device end and used for sending a buffer control character to the sending device, wherein the buffer control character is used for indicating the size of the residual buffer space of the receiving device at the current moment;
and the sending end flow control management unit is arranged at the sending device end and used for setting the priority of each transaction flow packet to be transmitted after receiving the buffer control characters and preferentially sending the transaction flow packet with high priority.
Further, the sending-end flow control management unit is specifically configured to: and if the transaction flow packet sent by the sending device is a request response signal, setting the priority of the request response signal as the priority of the highest level.
Further, still include: a transmission rule setting unit, configured to set 4 priority thresholds for the size of the remaining buffer space of the receiving device in advance: p0, P1, P2, P3, P0> P1> P2> P3> 0;
the size of the remaining buffer space of the receiving device is represented as free _ buf _ cnt, and the transmission rule between the sending device and the receiving device is as follows:
if free _ buf _ cnt > is P0, transaction stream packets of all priorities can be transmitted;
if P0> free _ buf _ cnt > -P1, transaction stream packets with priorities of 1, 2 and 3 can be transmitted;
if P1> free _ buf _ cnt > -P2, transaction stream packets with priorities of 2 and 3 can be transmitted;
if P2> free _ buf _ cnt > -P3, the transaction stream packet with priority 3 can be transmitted;
if P3> free _ buf _ cnt >0, a response transaction stream packet can be transmitted.
Further, still include: the residual cache space size calculating unit is used for presetting an indication signal output _ no _ received sent by the transaction flow packet but not received by the transaction flow packet and an indication signal sent by the transaction flow packet and received by the transaction flow packet; and when the sending device receives one receiving control character, the value of output _ no _ received is subtracted by 1.
The invention has the beneficial effects that:
(1) in the heterogeneous processing platform, the dependency of the whole system performance on a receiving device is reduced, and part of arbitration pressure of transaction flow transmission of a rear receiving end is borne on a sending end, so that the complex control of the sending device and the receiving device is relatively balanced;
(2) different from the traditional strategy of taking speed adjustment as the direction, the invention utilizes a feedback adjustment control mechanism to feed back the idle buffer quantity of the receiving device to the sending device, and the sending device readjusts the priority attribute of the transaction flow packet according to the feedback information of the receiving device and distributes the priority attribute to the next module unit, thereby greatly increasing the utilization rate of the buffer area;
(3) the sending device can autonomously allocate the buffer units of the receiving device according to the priority and the number of the transaction flow packets, and forced retransmission caused by insufficient space is not needed to be worried about, so that the probability of data receiving failure is reduced, and the transmission efficiency of the heterogeneous processing platform is improved.
Drawings
Fig. 1 is a schematic flow chart of a heterogeneous processing platform flow control management method based on fpga according to an embodiment of the present invention;
fig. 2 is a schematic format diagram of a transaction stream packet according to an embodiment of the present invention;
fig. 3 is a second flowchart of a heterogeneous processing platform flow control management method based on fpga according to the embodiment of the present invention;
fig. 4 is a block diagram of a flow control management device of an fpga-based heterogeneous processing platform according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is becoming a trend to combine fpga with general processor cpu to form a heterogeneous processing platform in heterogeneous processing systems. The parallel coprocessing of the fpga unit and the calculation and scheduling control of the cpu unit are combined to exert the advantages of different calculation units, thereby meeting the requirements of high-performance real-time systems such as high-speed data transmission and processing. The invention constructs a special link between the fpga and an external processing module according to different task requirements, and perfects the functions of command interaction, system state detection, dynamic reconfiguration and the like between the fpga and the external processing module.
The invention provides an improved flow buffering method in a multi-fpga board card heterogeneous processing platform, which can greatly reduce the dependence of the whole system on the performance of a receiving end. One part of the pressure of the transaction flow transmission of the rear receiving end is borne by the transmitting end, so that the complex control of the receiving and transmitting of the two ends is balanced, the management and the utilization rate of the buffer area are greatly improved, and the transmission efficiency of the whole system is improved.
Example 1
As shown in fig. 1, an embodiment of the present invention provides a heterogeneous processing platform flow control management method based on fpga, including:
s101: the receiving device sends a buffer control character to the sending device, wherein the buffer control character is used for indicating the size of the residual buffer space of the receiving device at the current moment;
specifically, when the size of the remaining buffer space of the receiving device changes, the receiving device transmits a buffer control character to the transmitting device.
S102: and after receiving the buffer control characters, the sending device sets the priority of each transaction flow packet to be transmitted and sends the transaction flow packet with high priority preferentially.
Specifically, if the transaction stream packet sent by the sending device is a request response signal, the priority of the request response signal is set to the priority of the highest level.
As an implementation manner, the format of the transaction stream packet shown in fig. 2 includes an identifier ID of the transaction stream packet, followed by a PRIO priority character for flow control management, and then the target addr and source addr fields are all routing information about transmission, and then the next fields are all information fields added by the logical layer. The identifier ID is used to indicate the transfer order of each transaction stream packet, and the PRIO priority character is used to indicate the priority of the transaction stream packet.
In the flow control management method provided in the embodiment of the present invention, after the sending device sends out data, the receiving device feeds back a buffer control character to the sending device in a control character manner, and because the buffer control character indicates information about the size of the remaining buffer space of the receiving device at the current time, the sending device may perform pre-judgment according to the buffer control character, and thus allocate and send a decision about a sending policy according to the number and priority of transmitted transaction stream packets, for example, how many transaction stream packets can be sent, which transaction stream packets should be sent first, and the like. Thus, the transmitting device does not need to worry about transmission failure of data transmitted by the transmitting device due to various reasons such as insufficient buffer area, and the like, so that the data transmission efficiency between two communication parties can be improved.
Example 2
As shown in fig. 3, an embodiment of the present invention provides another method for flow control management of an fpga-based heterogeneous processing platform, including:
s201: setting a counter at the end of the sending device;
specifically, the counting rule of the counter is as follows: (1) when the transaction flow packet starts to be sent, the counter starts to count; (2) when the sending device receives the receiving control character, the counter is reset; the counter is always circularly carried out according to the rule (1) and the rule (2);
s202: the sending device judges whether the counter value exceeds a set threshold value or not, or whether a packet transmission error character is received or not;
specifically, when the value of the counter exceeds a certain threshold or when the transmitting device receives a packet transmission error character, the packet reception is considered to be failed, and the receiving device needs to wait for responding to a retransmission indication signal;
s203: the receiving device sends a retransmission response signal (error reception or retransmission recovery character) and/or a buffering control character to the sending device;
s204: when the transmitting device receives the retransmission response signal of the receiving device, retransmitting according to the retransmission recovery character;
s205: when the sending device receives the buffer control character of the receiving device, the buffer control character is distributed and sent according to the priority of the transaction flow packet;
specifically, 4 priority thresholds are set in advance for the size of the remaining buffer space of the receiving device: p0, P1, P2, P3, P0> P1> P2> P3> 0; comparing the size of the residual buffer space indicated by the buffer control character with 4 priority thresholds, and then transmitting according to an agreed transmission rule;
as an implementation manner, the size of the remaining buffer space of the receiving device is represented as free _ buf _ cnt, and the transmission rule between the sending device and the receiving device is as follows:
if free _ buf _ cnt > is P0, transaction stream packets of all priorities can be transmitted;
if P0> free _ buf _ cnt > -P1, transaction stream packets with priorities of 1, 2 and 3 can be transmitted;
if P1> free _ buf _ cnt > -P2, transaction stream packets with priorities of 2 and 3 can be transmitted;
if P2> free _ buf _ cnt > -P3, the transaction stream packet with priority 3 can be transmitted;
if P3> free _ buf _ cnt >0, a response transaction stream packet can be transmitted.
As an implementation manner, the size of the remaining buffer space of the receiving device at the current time is calculated as follows:
presetting an indication signal output _ no _ received indicating that the transaction stream packet is sent but not received and an indication signal that the transaction stream packet is sent and received;
adding 1 to the value of output _ no _ received when the sending device sends a data packet, and subtracting 1 from the value of output _ no _ received when the sending device receives a receiving control character;
the size of the remaining buffer space of the receiving device at the current moment is equal to the total buffer space of the receiving device minus the value of output _ no _ received, and then minus the value of the indication signal that the transaction flow packet has been sent and has confirmed to receive.
It should be noted that the free _ buf _ cnt also represents the free size of the received transaction stream packet available to a port, and represents the maximum length of the transaction stream packet currently available for receiving, and if the size of the available buffer of a port exceeds the maximum value of the free _ buf _ cnt, the free _ buf _ cnt is set to the maximum value, and the number of reported buffers may be smaller than the number that can be actually used, but cannot report a value larger than the actual number of buffers, so as to avoid data overflow or data reception errors.
Example 3
As shown in fig. 4, an embodiment of the present invention provides a heterogeneous processing platform flow control management device based on fpga, including: the system comprises a receiving end flow control management unit, a sending end flow control management unit, a transmission rule setting unit and a residual cache space size calculating unit; wherein:
the receiving end flow control management unit is arranged at the receiving device end and used for sending a buffer control character to the sending device, wherein the buffer control character is used for indicating the size of the residual buffer space of the receiving device at the current moment;
and the sending end flow control management unit is arranged at the sending device end and used for setting the priority of each transaction flow packet to be transmitted after receiving the buffer control characters and preferentially sending the transaction flow packet with high priority.
Specifically, the sending-end flow control management unit is specifically configured to: and if the transaction flow packet sent by the sending device is a request response signal, setting the priority of the request response signal as the priority of the highest level.
A transmission rule setting unit, configured to set 4 priority thresholds for the size of the remaining buffer space of the receiving device in advance: p0, P1, P2, P3, P0> P1> P2> P3> 0; the size of the remaining buffer space of the receiving device is represented as free _ buf _ cnt, and the transmission rule between the sending device and the receiving device is as follows: if free _ buf _ cnt > is P0, transaction stream packets of all priorities can be transmitted; if P0> free _ buf _ cnt > -P1, transaction stream packets with priorities of 1, 2 and 3 can be transmitted; if P1> free _ buf _ cnt > -P2, transaction stream packets with priorities of 2 and 3 can be transmitted; if P2> free _ buf _ cnt > -P3, the transaction stream packet with priority 3 can be transmitted; if P3> free _ buf _ cnt >0, a response transaction stream packet can be transmitted.
The residual cache space size calculating unit is used for presetting an indication signal output _ no _ received sent by the transaction flow packet but not received by the transaction flow packet and an indication signal sent by the transaction flow packet and received by the transaction flow packet; and when the sending device receives one receiving control character, the value of output _ no _ received is subtracted by 1.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A heterogeneous processing platform flow control management method based on fpga is characterized by comprising the following steps:
the receiving device sends a buffer control character to the sending device, wherein the buffer control character is used for indicating the size of the residual buffer space of the receiving device at the current moment;
and after receiving the buffer control characters, the sending device sets the priority of each transaction flow packet to be transmitted and sends the transaction flow packet with high priority preferentially.
2. The method of claim 1, wherein the receiving device sends the buffer control character to the sending device when the size of the remaining buffer space of the receiving device changes.
3. The method of claim 1, wherein the setting the priority of each transaction stream packet to be transmitted comprises:
and if the transaction flow packet sent by the sending device is a request response signal, setting the priority of the request response signal as the priority of the highest level.
4. The method of claim 1, further comprising: setting 4 priority thresholds for the size of the remaining buffer space of the receiving device in advance: p0, P1, P2, P3, P0> P1> P2> P3> 0;
the size of the remaining buffer space of the receiving device is represented as free _ buf _ cnt, and the transmission rule between the sending device and the receiving device is as follows:
if free _ buf _ cnt > is P0, transaction stream packets of all priorities can be transmitted;
if P0> free _ buf _ cnt > -P1, transaction stream packets with priorities of 1, 2 and 3 can be transmitted;
if P1> free _ buf _ cnt > -P2, transaction stream packets with priorities of 2 and 3 can be transmitted;
if P2> free _ buf _ cnt > -P3, the transaction stream packet with priority 3 can be transmitted;
if P3> free _ buf _ cnt >0, a response transaction stream packet can be transmitted.
5. The method of claim 1, further comprising: presetting an indication signal output _ no _ received indicating that the transaction stream packet is sent but not received and an indication signal that the transaction stream packet is sent and received;
adding 1 to the value of output _ no _ received when the sending device sends a data packet, and subtracting 1 from the value of output _ no _ received when the sending device receives a receiving control character;
the size of the remaining buffer space of the receiving device at the current moment is equal to the total buffer space of the receiving device minus the value of output _ no _ received, and then minus the value of the indication signal that the transaction flow packet has been sent and has confirmed to receive.
6. The method of claim 1, wherein the transaction flow packet comprises an identifier ID and a PRIO priority character; the identifier ID is used to indicate the transfer order of each transaction stream packet, and the PRIO priority character is used to indicate the priority of the transaction stream packet.
7. An fpga-based heterogeneous processing platform flow control management device, comprising:
the receiving end flow control management unit is arranged at the receiving device end and used for sending a buffer control character to the sending device, wherein the buffer control character is used for indicating the size of the residual buffer space of the receiving device at the current moment;
and the sending end flow control management unit is arranged at the sending device end and used for setting the priority of each transaction flow packet to be transmitted after receiving the buffer control characters and preferentially sending the transaction flow packet with high priority.
8. The apparatus according to claim 7, wherein the sending-end flow control management unit is specifically configured to: and if the transaction flow packet sent by the sending device is a request response signal, setting the priority of the request response signal as the priority of the highest level.
9. The apparatus of claim 7, further comprising:
a transmission rule setting unit, configured to set 4 priority thresholds for the size of the remaining buffer space of the receiving device in advance: p0, P1, P2, P3, P0> P1> P2> P3> 0;
the size of the remaining buffer space of the receiving device is represented as free _ buf _ cnt, and the transmission rule between the sending device and the receiving device is as follows:
if free _ buf _ cnt > is P0, transaction stream packets of all priorities can be transmitted;
if P0> free _ buf _ cnt > -P1, transaction stream packets with priorities of 1, 2 and 3 can be transmitted;
if P1> free _ buf _ cnt > -P2, transaction stream packets with priorities of 2 and 3 can be transmitted;
if P2> free _ buf _ cnt > -P3, the transaction stream packet with priority 3 can be transmitted;
if P3> free _ buf _ cnt >0, a response transaction stream packet can be transmitted.
10. The apparatus of claim 7, further comprising:
the residual cache space size calculating unit is used for presetting an indication signal output _ no _ received sent by the transaction flow packet but not received by the transaction flow packet and an indication signal sent by the transaction flow packet and received by the transaction flow packet; and when the sending device receives one receiving control character, the value of output _ no _ received is subtracted by 1.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6347361B1 (en) * | 1998-02-17 | 2002-02-12 | International Business Machines Corporation | Cache coherency protocols with posted operations |
| JP2004165776A (en) * | 2002-11-11 | 2004-06-10 | Nippon Telegr & Teleph Corp <Ntt> | Code transmission method, code reception method, these devices and their respective programs |
| CN101800699A (en) * | 2010-02-09 | 2010-08-11 | 上海华为技术有限公司 | Method and device for dropping packets |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6347361B1 (en) * | 1998-02-17 | 2002-02-12 | International Business Machines Corporation | Cache coherency protocols with posted operations |
| JP2004165776A (en) * | 2002-11-11 | 2004-06-10 | Nippon Telegr & Teleph Corp <Ntt> | Code transmission method, code reception method, these devices and their respective programs |
| CN101800699A (en) * | 2010-02-09 | 2010-08-11 | 上海华为技术有限公司 | Method and device for dropping packets |
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Application publication date: 20210226 |