CN112416250B

CN112416250B - Command processing method for NVMe-based solid state disk and related equipment

Info

Publication number: CN112416250B
Application number: CN202011318258.8A
Authority: CN
Inventors: 黎杨; 赵朔天; 于大治; 段廷勇
Original assignee: Shenzhen Electric Appliance Co ltd
Current assignee: Shenzhen Electric Appliance Co ltd
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2024-09-20
Anticipated expiration: 2040-11-19
Also published as: CN112416250A

Abstract

The application provides a command processing method and related equipment of a solid state disk based on NVMe. Wherein the method comprises the following steps: updating the command queue entry and the command queue write pointer; reading a command from a static random access memory SRAM to obtain a command table entry, the command table entry comprising a command buffer address; according to the command table entry, acquiring a command from the SRAM and storing the command into a command static random access memory CSRAM arbiter; processing the command and updating a command completion queue in the SRAM. The method can improve the performance and efficiency of the SSD main control chip, and can realize high-efficiency processing of commands by utilizing the NVMe protocol.

Description

Command processing method for NVMe-based solid state disk and related equipment

Technical Field

The invention relates to the technical field of computers, in particular to a command processing method and related equipment of a solid state disk based on NVMe.

Background

Solid State Disk (SSD) is a hard disk made from an array of solid state electronic memory chips, and the interface specification of the SSD may be a serial advanced technology attachment (SERIAL ADVANCED technology attachment, SATA) interface or a high speed serial computer expansion bus standard (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIe) interface.

At present, the design of a storage chip of an SSD adopting a SATA interface or a PCIe interface is based on an advanced host controller interface (advanced host controller interface, AHCI) protocol, and some SSDs are even realized by adopting a field programmable gate array (field programmable GATE ARRAY, FPGA), so that the SSDs are poor in performance and low in efficiency.

Therefore, how to improve the performance and efficiency of the main control chip of the SSD is a problem to be solved.

Disclosure of Invention

The embodiment of the invention discloses a command processing implementation method, a command processing implementation system and related equipment for an NVMe-based solid state disk, which can improve the performance and efficiency of an SSD main control chip and can realize efficient command processing by utilizing an NVMe protocol.

In a first aspect, the present application provides a command processing implementation method for an NVMe-based solid state disk, including: updating the command queue entry and the command queue write pointer; reading a command table entry from a Static Random Access Memory (SRAM), wherein the command table entry comprises a command buffer address; according to the command table entry, acquiring a command from the SRAM and storing the command into a command static random access memory CSRAM arbiter; processing the command and updating a command completion queue in the SRAM.

In the scheme provided by the application, the NVMe command is firstly read from the SRAM to the CSRAM, then the CSRAM arbiter arbitrates the access of the relevant CSRAM, finally, the NVMe command is processed, and then the command completion queue in the SRAM is updated, so that the high-efficiency processing of the NVMe command can be improved, and the performance and efficiency of the SSD main control chip can be improved.

With reference to the first aspect, in a possible implementation manner of the first aspect, the NVMe command processing system searches a slot from the CSRAM and stores the command into the slot; the command tag table and the write command link list are updated.

With reference to the first aspect, in a possible implementation manner of the first aspect, the NVMe command processing system updates the command queue read pointer after obtaining the command from the SRAM and saving it in the command static random access memory CSRAM.

With reference to the first aspect, in one possible implementation manner of the first aspect, if the command is a write command and the write command link list is not empty, the CSRAM is read to obtain a new write command; determining the last data unit DU transmission and releasing the slot.

With reference to the first aspect, in one possible implementation manner of the first aspect, if the command is a read command, the slot is released after the last DU is sent to the host.

With reference to the first aspect, in a possible implementation manner of the first aspect, the NVMe command processing system receives a command tag, where the command tag is used to suspend a command corresponding to the command tag; and according to the command label, setting the corresponding flag bit in the completion queue entry to be 1 so as to suspend the command.

In a second aspect, the present application provides an NVMe command processing system, including: an updating unit for updating the command queue entry and the command queue write pointer; a reading unit for reading a command table entry from a static random access memory SRAM, the command table entry comprising a command buffer address; and the processing unit is used for acquiring the command from the SRAM according to the command table entry, storing the command into a command static random access memory CSRAM, processing the command and updating a command completion queue in the SRAM.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing unit is specifically configured to: searching a slot from the CSRAM, and storing the command into the slot; the command tag table and the write command link list are updated.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing unit is further configured to update a command queue read pointer.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing unit is specifically configured to: if the command is a writing command and the writing command link list is not empty, reading the CSRAM to acquire a new writing command; determining the last data unit DU transmission and releasing the slot.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing unit is specifically configured to: and if the command is a read command, the slot is released after the last DU is sent to the host.

With reference to the second aspect, in a possible implementation manner of the second aspect, the system further includes a receiving unit, configured to receive a command tag, where the command tag is configured to suspend a command corresponding to the command tag; and the processing unit is further used for setting the corresponding flag bit in the completion queue entry to be 1 according to the command tag so as to suspend the command.

In a third aspect, the present application provides a computing device comprising a processor and a memory, the processor and the memory being connected by an internal bus, the memory having instructions stored therein, the processor invoking the instructions in the memory to perform the method of data access as provided in connection with any of the implementations of the first aspect above.

In a fourth aspect, the present application provides a computer storage medium storing a computer program, which when executed by a processor, implements the first aspect described above and the flow of the data access method provided in connection with any one of the implementations of the first aspect described above.

In a fifth aspect, the present application provides a computer program product comprising instructions which, when executed by a computer, cause the computer to perform the above-described first aspect and the flow of a data access method provided in connection with any one of the implementations of the above-described first aspect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an NVMe multi-queue according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a system architecture according to an embodiment of the present application;

Fig. 3 is a flow chart of a command processing method of a solid state disk based on NVMe according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a command table entry format provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a command location in an SRAM according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a command tag table according to an embodiment of the present application;

FIG. 7 is a diagram of a completion queue entry format provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of an NVMe command processing system according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made more fully hereinafter with reference to the accompanying drawings, in which it is shown, however, only some, but not all embodiments of the application are shown.

First, some of the expressions and related techniques involved in the present application are explained in conjunction with the drawings so as to be understood by those skilled in the art.

Nonvolatile memory system (Non-Volatile memory express, NVMe) is an extensible host controller interface designed specifically for enterprise-level and client systems that employs PCIe solid state disks, including optimized register interfaces and command sets. Basically, NVMe is an optimized queue interface, and the host submits commands to the queue, and the queue completes reading or writing data, not according to the time sequence of the host command submission. And, it has a special component to manage the queues to accomplish the creation, deletion, command suspension, security, etc. of the queues. The NVMe protocol supports a plurality of parallel command queues, a maximum of 64k command queues, each having 64k commands, and for each command queue, queue information needs to be saved, so that when implementing the NVMe protocol, a piece of space needs to be opened up for each queue. As shown in fig. 1, an NVMe multi-queue schematic diagram is shown, interaction between a host and an NVMe device (which may be referred to as a controller) is realized through a shared memory queue, an MSI-X interrupt mechanism is supported, two queues exist in the host memory, namely a management queue (leftmost queue) and a normal queue (command queue), there is only one management queue, the number and mode of the command queues can be set through the management queue, each command queue is actually a queue pair, including two queues, namely a command submitting queue and a command completing queue, the command submitting queue is used for the host to send an NVMe command to the NVMe device, the command completing queue is used for the NVMe device to feed back a command executing condition to the host, and each command queue corresponds to one CPU core and can perform a read-write operation and a refresh operation of the command. In order to adapt to a high-bandwidth and low-delay interface of a PCIe SSD, the interface form is designed into a multi-path or multi-IO channel mode, one path or IO channel is composed of one or more command submitting queues and a command completing queue corresponding to the command submitting queues, and the command submitting queues and the command completing queues can be dynamically created in pairs. If multiple command queues share one IO channel, their priority may be determined by an arbitration mechanism, thereby determining the IO channel usage order.

The host memory buffer (host memory buffer, HMB) enables the host side to provide memory resources which are not needed at present for SSD for use through NVMe protocol, is applicable to solid state disk without external buffer, can realize memory conversion layer (flash translation layer, FTL) mapping table access by using host memory, and can accelerate improvement of performance.

At present, when a storage chip is designed, SSD based on an SATA interface or a PCIe interface is realized by adopting an AHCI protocol or an FPGA, so that the SSD main control chip has poor performance and low efficiency. The application provides a design scheme and a command processing method of an SSD storage control chip based on an NVMe protocol and an HMB technology, which are used for independently designing NVMe command processing, further optimizing the design on the basis of realizing the NVMe protocol and improving the performance and efficiency of an SSD main control chip.

Based on the above, the application provides a command processing method for a solid state disk based on NVMe, which processes NVMe commands through an independently designed NVMe command processing architecture, thereby improving the performance and efficiency of an SSD main control chip.

The technical scheme of the embodiment of the application can be applied to any system related to command processing of an SSD control chip, and particularly can be applied to the SSD scene using an NVMe protocol.

Fig. 2 shows a schematic diagram of a system architecture according to an embodiment of the application. As shown in fig. 2, the system 200 includes: microprocessor 210, registers 220, fetch command state machine 230, advanced extensible interface (advanced extensible interface, AXI) master 240, command static random access memory arbiter 250, command completion state machine 260, static random access memory 270. The microprocessor 210 sends the received IO command to the register 220, the register 220 includes a command queue base address and pointer register 221, a command abort register 222, a completion queue base address and pointer register 223, an interrupt status and mask register 224, a data format register 225, the microprocessor 210 issues a read/write command using a command queue in the sram 270 or BTCM and informs the fetch state machine 230, the fetch state machine 230 reads the command from the sram 270 through the AXI master 240 according to the address and pointer stored in the register 220 (e.g., command queue base address and pointer register 221) and then requests the command sram arbiter 250 to obtain a command slot, the command sram arbiter 250 includes a command sram 251, a command tag array 252 and a write command linked list, the command sram arbiter 250 saves the command in the command sram 251 and updates the command tag list in the command tag array 252 and the write command linked list in the write command linked list, it is required that the initial command context is also stored in the command sram 251, the command sram 260 is completed after the command is processed by the AXI master 240, and the command sram arbiter 250 releases the command ram arbiter 250 from the command sram 270.

In the embodiment of the application, all parts related to the NVMe command processing system are independently designed for better processing of the NVMe command, and can be deployed in a server or a chip.

Compared with the prior art, the system shown in fig. 2 is used for processing the NVMe command, so that the command processing efficiency and the performance of the SSD main control chip can be effectively improved.

With reference to the schematic diagram of the system architecture shown in fig. 2, the command processing method based on the NVMe solid state disk provided by the embodiment of the application will be described below. As shown in fig. 3, the method flow includes:

s301: the command queue entry and command queue write pointer are updated.

Specifically, the firmware uses the command queue to issue a read command or a write command to the command processing system, for each command, the firmware needs to write a new command queue entry, and then the firmware updates the command queue write pointer to push the command into the hardware. Each 32-bit command queue entry points to a 64-byte NVMe command buffer, the base address of the command queue is controlled by the lower 21 bits (e.g., RC0033018h [20:0 ]), the size of the command queue is controlled by the upper 8 bits (e.g., RC0033018h [31:24 ]), and the positions of the command queue and command buffer are controlled by the middle two bits (e.g., RC0033018h [23:22 ]).

It should be noted that for an unmapped read command, the read data is not from NAND, the buffer manager will provide dummy data for the unmapped read command, firmware needs to issue the read command to CMD_ PORC and program a register (e.g., register RC0033048 h) to implement the unmapped read command control. Illustratively, RC0033048h [16] is set to 1 to enable the unmapped read command data tag, RC0033048h [9:0] is used for the special data tag of the unmapped read command (which tag must match the special data tag in the buffer manager), when RC0033048h [16] is 1 and the incoming data tag matches RC0033048h [9:0], it can be determined that this data tag is used for the unmapped read command, if PI is enabled, the PI result will be ignored, and PI inserted for each sector.

After updating the command queue entry and command queue write pointer, the system 200 may begin processing new commands.

S302: a command table entry is read from the static random access memory SRAM, the command table entry including a command buffer address.

Specifically, in the case where the command queue is not empty and the command slot is not full, the cmd_fetch_sm reads the SRAM to acquire a command table entry including sq_id, hw_auo_cmpl, cmd_type, cmd_buf_addr information, so that the command buffer address can be determined.

Illustratively, as shown in FIG. 4, there is a schematic diagram of a command table entry format having 32 bits, divided into 6 parts, each representing a different meaning, e.g., 8 bits low for describing an internal command TAG, 16 bits high for describing CMD_BUF_ADDR, and 16 bits 16 for describing CMD_TYPE_1 for describing a command TYPE.

S303: and acquiring a command from the SRAM according to the command table entry and storing the command into a command static random access memory CSRAM arbiter.

Specifically, after reading the command table entry, cmd_fetch_sm reads the SRAM to acquire the command, then calculates the command context and saves it to CMD DW1-DW3, then requests the CSRAM acquire command slot, writes the command into the corresponding CSRAM entry, and then updates the command tag table and write command link list. When the command slot is full, reading of the new command will cease and each time after reading the command, the command queue read pointer (e.g., RC003301Ch [15:8 ]) needs to be updated.

Illustratively, as shown in FIG. 5, FIG. 5 is a schematic diagram of the location of commands in an SRAM, with both the base address and the data read pointer in the command table pointing to scattered 64 byte NVMe commands.

It should be noted that, when the fetch command state machine requests to store a new command, a command tag is required to be used as an input, then the CSRAM arbiter allocates a command queue location and stores the command, and then updates a command tag table, which is used to store a command slot and a command tag mapping table, as shown in fig. 6.

In addition, the CSRAM arbiter will also handle other arbitration regarding CSRAM access, such as data_xfer write DMA request to get new write command, CSRAM arbiter returns new write command and its location queue number, and updates the write command link list; when the DATA_XFER reads the DMA request to acquire command information, taking a command tag as input, the CSRAM arbiter finds a queue number, returns command information, and updates the remaining DATA length of the command; when DATA_XFER reads_PRP_CTRL requests to acquire command information, the command slot is taken as input, and the CSRAM arbiter returns the command information; when the DATA_XFER requests to store error information, the command slot is taken as input, and the CSRAM arbiter stores the error information into a corresponding command static random access memory; when a DATA_XFER NCB_INDI_CTRL requests to acquire command information, taking a command tag as input, the CSRAM arbiter finds a slot and returns the command information; a command ABORT request, taking the command tag as input, the CSRAM arbiter finding a slot and immediately aborting the read command, or commanding WCMD _abort position 1 in static random access memory for the write command; the command completes the request, takes the command tag as input, and the CSRAM arbiter releases the command slot and clears the valid bit. It should be appreciated that for a READ command, the CSRAM arbiter also requests read_prp_ctrl to clear all READ PRP entries associated with this command.

It is readily appreciated that commands stored in CSRAM CRSAM may store 64 commands, each of 64 bytes, for the write command case, DATA_XFER determines the last DU transfer and requests the CMPL FSM to release the command slot; for read command requests, the CSRAM returns last_du with command information to the DATA_XFER of the last DU, which requests the CMPL FSM to release the command slot after the DATA is sent to the host.

S304: processing the command and updating a command completion queue in the SRAM.

Specifically, after the CSRAM arbiter completes the relevant processing of the command, the command completion queue in the SRAM is updated by the command completion state machine. The command completion state machine processes the DATA_XFER completion request and FW command ABORT request and requests the CSRAM to release the command slot or save the WCMD _ABORT status bit as a write command, updates the command completion queue in the SRAM, if the hardware autocomplete function is enabled and the command has completed correctly, NVMe_CTRL updates the host CQ, and if the command is aborted, requests NVMe_CTRL are disabled.

For example, as shown in fig. 7, fig. 7 is a schematic diagram of a completion queue entry format, where the completion queue entry format has 64 bits, each of which indicates a different field, e.g., the FIRST bit indicates cmd_good for describing command completion and no error, the 7 th bit indicates pcie_read_ TMOUT for describing PCIe READ timeout, the 17 th to 25 th bits indicate cmd_tag for describing command TAG, and the 33 th to 64 th bits indicate first_err_lba for describing FIRST LBA error.

The extraction process is described in detail above, and the write command flow and the read command flow are described in detail below.

The specific process of writing commands is as follows:

If the write command linked list is not empty, then DATA_XFER reads CSRAM to get the new write command, if the required PRP/SGL is greater than PRP1/PRP2/SGL1, DATA_XFER reads the PRP/SGL list from the host, when PRP/SGL is available, DATA_XFER reads the DATA from the host and then writes it to SRAM, the read is split into DUs (e.g., 4KB, 4KB+8B, or 4KB+64B for the 4KB DU case), the first and last DUs may be partial DUs. Since the write commands are executed sequentially, the CSRAM does not need to update the remaining DATA length, after writing all the DATA of the command to SRAM, the data_xfer requests cmd_proc to update the command completion status, cmd_proc releases the command slot and writes the completion queue to SRAM, if this command enables the hardware autocompletion function, cmd_proc will send { sq_id, CID } information to nvme_ctrl if this command does not enable the hardware autocompletion function, if the command is aborted or completed erroneously, it will later prepare the completion status and inform nvme_ctrl to send, nvme_ctrl updates the host CQ.

The specific process of the read command is as follows:

When DATA_XFER obtains an early indication from the NAND control block, a CMD_PROC with CMD_TAG and DU_OFFSET is requested, the CMD_PROC returns command slots, PSDT, DATA Pointer (DPTR), metadata Pointer (MPTR), SLBA, PRINFO and NLB, and DATA_XFER then reads the host memory to prepare PRP/SGL. After the DATA_XFER obtains the DATA TAG from the BM, a CMD_PROC with CMD_TAG and DU_OFFSET is requested, which returns to the command slots, PSDT, DPTR, MPTR, SLBA, PRINFO, NLB, EILBRT, ELBATM and ELBAT, which also reduces the remaining DATA length saved in the command SRAM, and if this is the last DU, the CMD_PROC sends a last_du signal with acknowledgement to the DATA_XFER. If DATA_XFER READ_PRP_CTRL cannot find the relevant PRP/SGL of the DATA tag, CMD_PROC with CMD_SLOT and DU_OFFSET will be requested, CMD_PROC returns command SLOTs, PSDT, DPTR, MPTR, SLBA, PRINFO and NLB, and DATA_XFER READ_PRP_CTRL then READs the host memory to obtain PRP/SGL. After the DATA_XFER sends the last DU to the host, the CMD_PROC update command completion status is requested, the command slot is released by CMD_PROC, the DATA_XFER READ_PRP_CTRL is requested to release the PRP/SGL cache entry associated with this command, and the completion queue is written to SRAM. If this command enables the hardware auto-complete function, then CMD_PROC sends SQ_ID, CID } information to NVMe_CTRL in the event that the command completes without error, and if this command does not enable the hardware self-complete function, the command is aborted or completed in error, then the completion status will be prepared later and the NVMe_CTRL is notified to send, and NVMe_CTRL updates the host CQ.

In addition, there may be a case of suspension during the execution of the command, for example, the command cmd_tag may be written into the command suspension register to suspend the command, and if the command issue queue is not empty, the suspended command may remain in the queue and cannot reach the CSRAM, at which point the suspension operation will be retried until the command issue queue is empty. If the read command is to be aborted, it is necessary to ensure that there is no pending data TAG associated with this command in the BM and nvme_ctrl, if cmd_tag is not found, this ABORT operation will be ignored and will not write to the completion queue, if cmd_tag is found, HW ABORTs the read command immediately and updates the completion queue with cmd_abort position 1. If the write command is to be aborted, if CMD_TAG is not found, then this ABORT operation will be ignored and the completion queue will not be written, if CMD_TAG is found, then the write command will not be aborted immediately, WCMD _ABORT location 1, DATA_XFER will be treated in the command SRAM in the same way as the fatal error WCMD _ABORT, and the command will be aborted after WCMD _ABORT bit is found to be set to 1.

The foregoing details of the method according to the embodiments of the present application are provided for the purpose of better implementing the foregoing aspects of the embodiments of the present application, and accordingly, related devices for implementing the foregoing aspects in conjunction therewith are also provided below.

Referring to fig. 8, fig. 8 is a schematic structural diagram of an NVMe command processing system according to an embodiment of the present application. As shown in fig. 8, the system 800 includes an updating unit 810, a reading unit 820, and a processing unit 830. Wherein,

An updating unit 810 for updating the command queue entry and the command queue write pointer;

a reading unit 820 for reading a command table entry from the SRAM, the command table entry including a command buffer address;

and a processing unit 830, configured to obtain a command from the SRAM according to the command table entry, store the command in a command static random access memory CSRAM, process the command, and update a command completion queue in the SRAM.

As an embodiment, the processing unit 830 is specifically configured to: searching a slot from the CSRAM, and storing the command into the slot; the command tag table and the write command link list are updated.

The processing unit 830 is further configured to update a command queue read pointer, as an embodiment.

As an embodiment, the processing unit 830 is specifically configured to: if the command is a writing command and the writing command link list is not empty, reading the CSRAM to acquire a new writing command; determining the last data unit DU transmission and releasing the slot.

As an embodiment, the processing unit 830 is specifically configured to: and if the command is a read command, the slot is released after the last DU is sent to the host.

As an embodiment, the system further comprises a receiving unit 840, the receiving unit 840 is configured to receive a command tag, and the command tag is configured to suspend a command corresponding to the command tag; the processing unit 830 is further configured to set a corresponding flag bit in a completion queue entry to 1 according to the command tag to suspend the command.

It should be understood that the above-described structure of the NVMe command processing system is only an example, and should not be construed as a specific limitation, and various units of the system may be added, reduced or combined as needed. In addition, the operations and/or functions of the respective units in the system are not described herein for brevity in order to implement the corresponding flow of the method described in fig. 3.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a computing device according to an embodiment of the present application. As shown in fig. 9, the computing device 900 includes: a processor 910, a communication interface 920, and a memory 930, the processor 910, the communication interface 920, and the memory 930 being interconnected by an internal bus 940.

The computing device 900 may be the NVMe command processing system of fig. 2. The functions performed by the NVMe command processing system in fig. 2 are actually performed by the processor 910 of the computing device.

The processor 910 may be comprised of one or more general purpose processors, such as a central processing unit (central processing unit, CPU), or a combination of CPU and hardware chips. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, general-purpose array logic (GENERIC ARRAY logic, GAL), or any combination thereof.

Bus 940 may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The bus 940 may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, only one thick line is shown in fig. 9, but not only one bus or one type of bus.

Memory 930 may include volatile memory (RAM), such as random access memory (random access memory); the memory 730 may also include a non-volatile memory (non-volatile memory), such as read-only memory (ROM), flash memory (flash memory), hard disk (HARD DISK DRIVE, HDD) or solid state disk (solid-state disk) (STATE DRIVE, SSD); memory 930 may also include combinations of the above. The program code may be functional units for implementing the NVMe command processing system 800 or method steps for implementing the NVMe command processing system as an execution body in the method embodiment shown in fig. 3.

The embodiment of the present application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, can implement part or all of the steps of any one of the above-described method embodiments, and implement the functions of any one of the functional units described in fig. 8.

Embodiments of the present application also provide a computer program product which, when run on a computer or processor, causes the computer or processor to perform one or more steps of any of the methods described above. The respective constituent elements of the above-mentioned apparatus may be stored in the computer-readable storage medium if implemented in the form of software functional units and sold or used as independent products.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.

It should also be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. The command processing method of the NVMe-based solid state disk is characterized by comprising the following steps of:

updating the command queue entry and the command queue write pointer;

reading a command table entry from a Static Random Access Memory (SRAM), wherein the command table entry comprises a command buffer address;

According to the command table entry, acquiring a command from the SRAM and storing the command into a command static random access memory CSRAM arbiter;

processing the command and updating a command completion queue in the SRAM;

wherein, according to the command table entry, the command is obtained from the SRAM and stored into a command static random access memory CSRAM, comprising:

searching a slot from the CSRAM, and storing the command into the slot;

the command tag table and the write command link list are updated.

2. The method of claim 1, wherein after retrieving a command from the SRAM and saving it to a command static random access memory CSRAM, the method further comprises:

The command queue read pointer is updated.

3. The method of claim 1, wherein processing the command comprises:

If the command is a writing command and the writing command link list is not empty, reading the CSRAM to acquire a new writing command;

Determining the last data unit DU transmission and releasing the slot.

4. The method of claim 2, wherein processing the command comprises:

Determining the last data unit DU transmission and releasing the slot.

5. The method of any of claims 1-4, wherein processing the command comprises:

and if the command is a read command, the slot is released after the last DU is sent to the host.

6. The method of any one of claims 1-4, wherein the method further comprises:

receiving a command tag, wherein the command tag is used for suspending a command corresponding to the command tag;

and according to the command label, setting the corresponding flag bit in the completion queue entry to be 1 so as to suspend the command.

7. An NVMe command processing system, comprising:

an updating unit for updating the command queue entry and the command queue write pointer;

a reading unit for reading a command table entry from a static random access memory SRAM, the command table entry comprising a command buffer address;

The processing unit is used for acquiring the command from the SRAM according to the command table entry, storing the command into a command static random access memory CSRAM, processing the command and updating a command completion queue in the SRAM;

wherein, the processing unit is specifically configured to:

searching a slot from the CSRAM, and storing the command into the slot;

the command tag table and the write command link list are updated.

8. The system of claim 7, wherein the system comprises a plurality of sensors,

The processing unit is further configured to update the command queue read pointer.

9. The system according to claim 7, wherein the processing unit is specifically configured to:

Determining the last data unit DU transmission and releasing the slot.

10. The system according to claim 8, wherein the processing unit is specifically configured to:

Determining the last data unit DU transmission and releasing the slot.

11. The system according to any of the claims 7-10, wherein the processing unit is specifically configured to:

12. The system of any one of claims 7-10, further comprising a receiving unit,

The receiving unit is used for receiving a command tag, and the command tag is used for stopping a command corresponding to the command tag;

And the processing unit is further used for setting the corresponding flag bit in the completion queue entry to be 1 according to the command tag so as to suspend the command.

13. A computing device comprising a memory and a processor executing computer instructions stored in the memory, the computing device being caused to perform the method of any of claims 1-6.

14. A computer readable storage medium storing a computer program which, when executed by a processor, performs the functions of the method of any one of claims 1-6.