CN112332852A - Platform and method for improving DAC sampling rate - Google Patents
Platform and method for improving DAC sampling rate Download PDFInfo
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- CN112332852A CN112332852A CN202011374157.2A CN202011374157A CN112332852A CN 112332852 A CN112332852 A CN 112332852A CN 202011374157 A CN202011374157 A CN 202011374157A CN 112332852 A CN112332852 A CN 112332852A
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Abstract
The invention discloses a platform and a method for improving DAC sampling rate, wherein the platform comprises: the method comprises the steps of firstly, decomposing an input signal into two independent signal sequences by using a data decomposition unit, then respectively inputting the two signal sequences into two DAC chips working in a conventional mode and a mixing mode, respectively performing different compensation on the signal sequences input into the two DAC chips according to the amplitude inconsistency output by the two DAC chips, finally, synthesizing and outputting the output signals of the two DAC chips by using a power synthesizer, and providing a sampling clock and a reference clock for the two DAC chips by using the clock management module. The platform and the method for improving the DAC sampling rate improve the real-time sampling rate of the DAC chip by 1 time, provide a new technical route for improving the DAC sampling rate, have obvious effect, and have simple and easily realized platform architecture.
Description
Technical Field
The invention belongs to the technical field of DAC synthesis conversion, and particularly relates to a platform and a method for improving the DAC sampling rate.
Background
The high-speed DAC is a key to realize high-speed data playing, and at present, the number of DACs capable of operating at a higher sampling frequency is small and expensive, and further increasing the sampling rate of the DAC also faces a great challenge. In recent years, due to factors such as technical blockade, high-end DAC devices are difficult to obtain in China, and in the face of such dilemma, breaking through the technical bottleneck that the DAC sampling rate is difficult to improve is of great importance to improving the application level of DAC chips in China.
At present, two methods for improving the sampling rate of the DAC mainly include a DAC synthesis method based on high-speed switching and a DAC synthesis method of alternative time, and specifically, the output of two or even a plurality of DAC chips are spliced together. The two DAC chips are taken as an example for explanation, when the two DAC chips are synthesized, the DAC synthesis method based on the high-speed switch needs to ensure that the switching frequency of the electronic switch is twice of the sampling clock of the DAC chip, and the method has the defects that when the switching frequency of the electronic switch is continuously improved, clock jitter has great influence on the duty ratio of the electronic switch, and the electronic switch with high switching frequency is difficult to obtain; the alternative time based DAC synthesis method requires that the clocks of the two DAC chips have a fixed phase difference, so as to avoid the problem of inaccurate output synthesis signals, but in practice, the fixed phase difference is hard to guarantee.
Therefore, a new platform and method for increasing the sampling rate of the DAC are needed to effectively increase the sampling rate of the DAC.
Disclosure of Invention
In view of this, the present invention provides a platform for improving a DAC sampling rate based on power synthesis and a method thereof, in which the method synthesizes outputs of two DAC chips operating in different modes, thereby effectively improving a real-time sampling rate of the DAC chip.
In order to achieve the purpose, the invention adopts the following technical scheme: a platform to increase a sampling rate of a DAC, the platform comprising: the device comprises a data decomposition unit, a DAC I, DAC chip II, a clock management module and a power synthesizer; the signal flow is firstly input into a data decomposition unit, is output from the data decomposition unit and then is input into a DAC chip I and a DAC chip II, and the signals output from the DAC chip I and the DAC chip II are input into a power synthesizer; and the clock management module controls the DAC chip I and the DAC chip II.
A method for increasing the sampling rate of a DAC, the method comprising the steps of:
a. the data decomposition unit decomposes a signal to be input into two independent signal sequences;
b. the adjusting clock management module generates a sampling clock and a reference clock which meet the requirements of the DAC chip I and the DAC chip II;
c. configuring the working modes of a DAC chip I and a DAC chip II, and enabling the two DAC chips to work in different modes;
d. b, respectively inputting the two independent signal sequences obtained by decomposition in the step a into a DAC chip I and a DAC chip II, respectively compensating the input signal sequences, and then respectively outputting the signal sequences;
e. and inputting the output signal sequence into a power synthesizer for power synthesis and outputting.
Preferably, the operating mode of the DAC chip in step c includes: a normal mode and a mixing mode.
Preferably, when the input signal sequence is compensated in step d, compensation adjustment coefficients of different DAC chips are different.
The invention has the beneficial effects that: the platform and the method for improving the DAC sampling rate can effectively improve the real-time sampling rate of the DAC by synthesizing two DAC chip signals working under different modes, are simple and easy to operate, have obvious effect, and avoid the problems that an electronic switch which meets performance indexes is difficult to find along with the improvement of the switching frequency of the electronic switch in the DAC synthesis technology based on a high-speed switch and the clock phase difference between different DACs is difficult to keep absolutely fixed in the alternative time DAC synthesis technology; the platform is simple in structure and easy to implement.
The platform and the method for improving the DAC sampling rate widen the application scene of the DAC.
Drawings
FIG. 1 is a schematic diagram of the structure and flow of the platform for increasing the DAC sampling rate and the method thereof according to the present invention;
FIG. 2 is a schematic diagram of the input-output relationship between the clock pulses and the DAC chip in the conventional mode of the present invention;
FIG. 3 is a schematic diagram of the input-output relationship between the clock pulses and the DAC chip in the mixing mode according to the present invention.
Detailed Description
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
The invention is described in detail below with reference to the figures and specific embodiments.
A platform for increasing the sampling rate of a DAC as shown in fig. 1, the platform comprising: the device comprises a data decomposition unit, a DAC chip I, a DAC chip II, a clock management module and a power synthesizer; the signal flow is firstly input into a data decomposition unit, is output from the data decomposition unit and then is input into a DAC chip I and a DAC chip II, and the signals output from the DAC chip I and the DAC chip II are input into a power synthesizer; and the clock management module controls the DAC chip I and the DAC chip II.
The data decomposition unit decomposes the data input into the system into two independent signal sequences according to the high sampling rate output required by the system; the DAC chip I and the DAC chip II both need to have two working modes, namely a conventional mode and a mixing mode, and the working modes can be configured; the clock management module is used for generating a DAC sampling clock and a reference clock meeting the requirements and ensuring the synchronism of the hardware platform; the power synthesizer is used for realizing the synthesis and output of two groups of analog signals after single-path digital-to-analog conversion of the two DAC chips.
The method for improving the DAC sampling rate by using the platform comprises the following steps:
a. the data decomposition unit decomposes a signal to be input into two independent signal sequences;
b. the adjusting clock management module generates a sampling clock and a reference clock which meet the requirements of the DAC chip I and the DAC chip II;
c. configuring the working modes of a DAC chip I and a DAC chip II, and enabling the two DAC chips to work in different modes;
d. b, respectively inputting the two independent signal sequences obtained by decomposition in the step a into two DAC chips, respectively compensating the input signal sequences, and then respectively outputting the signal sequences;
e. and inputting the output signal sequence into a power synthesizer for addition and outputting.
Wherein, the working mode of the DAC chip in the step c comprises: a normal mode and a mixing mode.
In the normal mode, the sampling principle of the DAC chip is based on the zero-order hold sampling, each time the rising edge of the sampling clock comes, the chip performs a digital-to-analog conversion on the sampling data, and then keeps the data unchanged in this period until the next rising edge of the sampling clock signal comes, and the above process is repeated, and the input-output relationship between the sampling clock pulse and the DAC chip operating in the normal mode is shown in fig. 2.
In the mixing mode, the DAC chip also performs digital-to-analog conversion on data to be converted on the rising edge of the sampling clock signal, and keeps the data unchanged for the next half clock cycle. Unlike the conventional mode, the DAC chip in the mixing mode will perform an inversion process on the data in the second half clock cycle, and hold the data in the second half clock cycle until the next rising edge of the sampling clock arrives, and the above process is repeated, and the relationship between the sampling clock pulses and the input and output of the DAC chip in the mixing mode is as shown in fig. 3.
During operation, two DAC chips work in different modes, as shown in FIG. 1, two DAC chips respectively order: DAC0 and DAC1, DAC0 operating in normal mode and DAC1 operating in mixed mode, both using the same sampling clock.
Taking the input signal sequence of a DAC0 chip as a0，a1，a2，…，aN-1As can be seen from FIG. 2, the output signal sequence of the DAC0 chip is a0，a0，a1，a1，a2，a2，…，aN-1，aN-1Taking the input signal sequence of the DAC1 chip as b0，b1，b2，…，bN-1As can be seen from FIG. 3, the output sequence of the DAC1 chip is b0，-b0，b1，-b1，b2，-b2，…，bN-1，-bN-1。
Let c be the final high-sampling-rate output signal sequence to be obtained0，c1，c2，…c2N-2，c2N-1In the ideal case, one can obtain:
and the analogy is that:
however, in practical situations, two identical DAC chips are not possible, and there is always a problem of amplitude inconsistency between the DAC chips, so that the signal sequences input to the DAC0 chip and the DAC1 chip need to be compensated separately, that is, different DAC chip input signals are multiplied by different compensation coefficients, that is:
in the above formula, a and β are compensation coefficients of the DAC0 chip and the DAC1 chip, respectively, and values of a and β can be obtained through multiple experimental verifications.
The DAC sampling rate can be increased to twice of the original DAC sampling rate by performing signal sampling through the DAC sampling rate increasing platform and the method thereof, the platform and the method disclosed by the invention can overcome the problems in the existing DAC sampling rate increasing method, the DAC chip sampling rate is effectively increased, and the application of the DAC chip is further expanded.
Claims (4)
1. A platform for increasing a sampling rate of a DAC, the platform comprising: the device comprises a data decomposition unit, a DAC I, DAC chip II, a clock management module and a power synthesizer; the signal flow is firstly input into the data decomposition unit, is input into the DAC chip I and the DAC chip II after being output from the data decomposition unit, and is input into the power synthesizer after being output from the DAC chip I and the DAC chip II; and the clock management module controls the DAC chip I and the DAC chip II.
2. A method for increasing the sampling rate of a DAC, the method comprising the steps of:
a. the data decomposition unit decomposes a signal to be input into two independent signal sequences;
b. the adjusting clock management module generates a sampling clock and a reference clock which meet the requirements of the DAC chip I and the DAC chip II;
c. configuring the working modes of a DAC chip I and a DAC chip II, and enabling the two DAC chips to work in different modes;
d. b, respectively inputting the two independent signal sequences obtained by decomposition in the step a into a DAC chip I and a DAC chip II, respectively compensating the input signal sequences, and then respectively outputting the signal sequences;
e. and inputting the output signal sequences into a power synthesizer for power synthesis and outputting.
3. The method of claim 2, wherein the operating mode of the DAC chip in step c comprises: a normal mode and a mixing mode.
4. The method for increasing the sampling rate of the DAC of claim 2, wherein when the compensation is performed on the input signal sequence in step d, the compensation adjustment coefficients of different DAC chips are different.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119171915A (en) * | 2024-09-25 | 2024-12-20 | 上海奥令科电子科技有限公司 | A digital-to-analog converter circuit supporting mixing mode |
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| US20080224908A1 (en) * | 2007-03-15 | 2008-09-18 | Analog Devices, Inc. | Mixer/DAC Chip and Method |
| US7479912B1 (en) * | 2007-09-13 | 2009-01-20 | Texas Instruments Incorporated | Low-power high-performance audio DAC system including internal oscillator, FIFO memory, and ASRC |
| CN105207671A (en) * | 2015-09-08 | 2015-12-30 | 四川鸿创电子科技有限公司 | High-speed digital signal parallel DDS synthesis method |
| JP2020025315A (en) * | 2015-11-18 | 2020-02-13 | フラウンホファー‐ゲゼルシャフト・ツア・フェルデルング・デア・アンゲヴァンテン・フォルシュング・エー・ファウ | Signal processing system and signal processing method |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208671B1 (en) * | 1998-01-20 | 2001-03-27 | Cirrus Logic, Inc. | Asynchronous sample rate converter |
| US20080224908A1 (en) * | 2007-03-15 | 2008-09-18 | Analog Devices, Inc. | Mixer/DAC Chip and Method |
| CN101627542A (en) * | 2007-03-15 | 2010-01-13 | 模拟设备公司 | Mixer/DAC chip and method |
| US7479912B1 (en) * | 2007-09-13 | 2009-01-20 | Texas Instruments Incorporated | Low-power high-performance audio DAC system including internal oscillator, FIFO memory, and ASRC |
| CN105207671A (en) * | 2015-09-08 | 2015-12-30 | 四川鸿创电子科技有限公司 | High-speed digital signal parallel DDS synthesis method |
| JP2020025315A (en) * | 2015-11-18 | 2020-02-13 | フラウンホファー‐ゲゼルシャフト・ツア・フェルデルング・デア・アンゲヴァンテン・フォルシュング・エー・ファウ | Signal processing system and signal processing method |
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| CN119171915A (en) * | 2024-09-25 | 2024-12-20 | 上海奥令科电子科技有限公司 | A digital-to-analog converter circuit supporting mixing mode |
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