CN112307627A

CN112307627A - An intelligent design method for on-chip all-optical devices with complex functions

Info

Publication number: CN112307627A
Application number: CN202011203168.4A
Authority: CN
Inventors: 芦启超; 陶理; 谭辉
Original assignee: 701 Research Institute of CSSC
Current assignee: 701 Research Institute of CSSC
Priority date: 2020-11-02
Filing date: 2020-11-02
Publication date: 2021-02-02

Abstract

The invention discloses an intelligent design method of a complex function on-chip all-optical device, and belongs to the technical field of on-chip all-optical device design. The invention adopts a method of combining intelligent design and modular design. First deconstruct it into a combination of several simple functional sub-devices, arrange the functions, locations, couplings and connection methods of these sub-devices through global design, and then use the intelligent design method to design these simple functional sub-devices. These sub-devices should be designed to maintain the consistency of dimensions, input and output waveguides, etc., which will facilitate the final combination of complex functional devices. At the same time, the basic device structures that have been designed are stored in the design database and can be used in future designs. Because the size of the sub-module device obtained by intelligent design is extremely small, and its layout is designed globally, an ultra-small-sized on-chip all-optical device with complex functions can be obtained.

Description

Intelligent design method of all-optical device on complex function chip

Technical Field

The invention belongs to the technical field of on-chip all-optical device design, and particularly relates to an intelligent design method of an on-chip all-optical device with complex functions.

Background

The on-chip optical device is considered as one of the most ideal technologies for breaking through the bottlenecks of ultra-large capacity, ultra-high speed data transmission and processing due to its outstanding advantages of high speed, low power consumption, small volume, easy integration and the like, and has recently received extensive attention from the academic and industrial fields. However, the conventional design concept is to obtain an initial structure according to an electromagnetic analysis theory and then perform complex optimization work, so that the device has a large size and a single function, and it is difficult to realize a high-integration-level and complex-function all-optical device.

Intelligent design is an effective combination of algorithmic optimization and electromagnetic computation, and the method will find the optimal device structure in an infinite structure parameter space according to the target performance given by the designer. In theory, any size and shape of device can be realized by intelligent design, so that the function of the device can be realized in smaller size. However, when a complex function device is faced, the calculation resource is greatly consumed when the corresponding function is directly obtained by using the algorithm through optimization, and the convergence of the algorithm cannot be guaranteed to obtain the optimal solution. The modular design is one of the most common methods for various designs at present, and a complex system can be effectively obtained by separately designing and recombining modules.

Therefore, how to perform intelligent design on the all-optical device with complex functions on a chip by combining an intelligent design method and a modular design method is a technical problem which needs to be solved urgently at present.

Disclosure of Invention

Aiming at the defects or improvement requirements in the prior art, the invention provides an intelligent design method of an all-optical device on a complex function chip, which comprises the steps of deconstructing the complex function device, obtaining sub-devices of the complex function device by intelligent design, and obtaining a final function by global design. Therefore, the function complexity of the on-chip all-optical device is realized, and the ultra-small size is realized.

In order to achieve the purpose, the invention provides an intelligent design method of an all-optical device on a complex function chip, which comprises the following steps:

(1) deconstructing a device that implements a target function into a combination of a plurality of sub-function devices;

(2) arranging the functions, positions, coupling and connection modes of all sub-functional devices through global design;

(3) and designing each sub-function device by using an intelligent design method to obtain a device structure with the minimum size.

In some alternative embodiments, step (1) comprises:

and constructing a function expression of a target function of the device, dividing the function expression of the target function into a combination of a plurality of simple functions, wherein each simple function represents a sub-function device so as to deconstruct the device for realizing the target function into a combination of a plurality of sub-function devices.

In some alternative embodiments, step (2) comprises:

in the design area, the coordinates of each sub-function device in the design area are obtained according to the input and output conditions of each sub-function device, and then the coupling connection mode between each sub-function device is further arranged.

In some alternative embodiments, step (3) comprises:

determining the function index of each sub-function device, and converting the function index into a fixed function form to optimize the function of each sub-function device;

performing electromagnetic field numerical simulation on each sub-function device to obtain the distribution and transmission characteristics of the electromagnetic field of the sub-function device, and then obtaining data capable of measuring the performance of the sub-function device according to the target function of the sub-function device;

and continuously and iteratively generating new device structures by using an intelligent algorithm according to the data capable of measuring the performance of each sub-function device, wherein when the optimal device structure is obtained, the algorithm is converged, and the optimal device structure is obtained at the moment.

In some alternative embodiments, the sub-devices should be designed to maintain consistency in dimensions and input-output waveguide conditions.

In some optional embodiments, the method further comprises:

and storing the designed sub-device structure.

In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:

the invention adopts a method of combining intelligent design and modular design, when a device with more complex functions needs to be designed, the device is deconstructed into a combination of a plurality of simple functional sub-devices, the functions, positions, coupling and connecting modes and the like of the sub-devices are arranged through global design, and the simple functional sub-devices are designed by using the intelligent design method. These sub-devices should be designed to maintain the consistency of the dimensions, input and output waveguides, etc., which is beneficial for the combination of the final complex functional device. Meanwhile, the designed basic device structure is stored in a design database and can be used in future design. Because the sub-module device obtained by intelligent design has extremely small size, and the layout of the sub-module device is designed globally, the on-chip all-optical device with ultra-small size and complex functions can be obtained.

Drawings

Fig. 1 is a schematic flowchart of an intelligent design method for an on-chip all-optical device with complex functions according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a design concept of an ultra-small on-chip all-optical half-adder according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the structure and function of an all-optical half adder according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a time response of a half adder according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

The invention mainly aims at the design of on-chip all-optical complex function devices, realizes the miniaturization of the devices and is beneficial to integration. Since the on-chip device size is small, it is difficult to realize complex functions by a single device, or the device size is drastically increased when the functions are complex, which is disadvantageous for the integration of the device. The invention therefore relates to a method for designing on-chip all-optical devices with complex functions at very small dimensions. The method can be better applied to the design of on-chip all-optical devices with complex functions under the condition of extremely small size.

The method mainly comprises the following steps:

(1) and (5) developing an intelligent design method. An intelligent design method effectively combining an algorithm and electromagnetic calculation is designed, and an optimal device structure and a minimum realization size can be searched in an infinite structure parameter space according to target performance given by a designer. The method comprises the following steps:

firstly, defining the target function of the device: in the step, the function index of the device to be designed is determined and converted into a fixed function form, and then the function is optimized; then, performing electromagnetic field numerical simulation on the device: performing electromagnetic field numerical simulation on the device structure by using an FDTD method to obtain a series of data of the distribution, transmission characteristics and the like of the electromagnetic field, and then obtaining data capable of measuring the performance of the device according to the target function of the device; and finally, optimizing the structure of the device: and continuously iterating an intelligent algorithm such as a genetic algorithm, a simulated annealing algorithm and the like to generate a new device structure, wherein when the optimal device structure is obtained, the algorithm is converged, and the optimal device structure is obtained at the moment.

(2) Deconstruction method of complex function device. The complex function is deconstructed into a combination of a plurality of simple functions, and a more general mode is to write a function expression of the complex function first and divide the function expression into a combination of a plurality of simple functions by using a mathematical decomposition and reconstruction method, so that the function deconstruction is realized. The simple functional devices are designed by an intelligent design method, the coordinates of the modules are obtained by global calculation, namely, in a design area according to the input and output conditions of the devices and the like by the intelligent design method, and a proper coupling connection mode is further arranged. The positions, the coupling and the connection modes of the simple functional devices are arranged, and complex functions are realized.

(3) Intelligent design of a plurality of different functional devices. Reasonably arranging the deconstructed device functions, and designing by using an intelligent method to obtain a device structure with a minimum size.

The key technology and the proposed solution will be described below with reference to the accompanying drawings and specific embodiments.

Example 1:

as shown in fig. 1, the embodiment of the present invention describes a specific design method flow by specifically designing an on-chip all-optical half adder.

The specific working mode is as follows:

(1) deconstruction of the function of the half adder and reintegration of the module;

as shown in fig. 2, the SUM of the outputs (SUM) of the half-adders is implemented by an exclusive or (XOR) operation AND the CARRY bit (CARRY) of the output is implemented by an AND (AND) operation. The XOR AND AND logic gate is the main functional block, AND the two logic gates are both in 2-input-1-output structures, so the Beam splitter is required to separate the initial signals AND input the signals into the two logic gates respectively, AND before the signals are input into the two logic gates, the signals are inevitably crossed, AND a Hub is required to avoid the crossing of the signals.

(2) Carrying out intelligent design on each functional module by utilizing an optimization algorithm;

as shown in fig. 3, each module is formed by a square lattice of the same size, and by using intelligent optimization, these square points are called pixels and are formed by two different materials, so that there are only two states of the pixels, and then only the pixels in the state of "1" can be considered in the algorithm optimization, and what is required is the optimal position of the pixels in the state of "1", which is called the optimal distribution of the pixels. Because the search space is only a two-dimensional space of 20 × 20 and the values can only be integers, the algorithm can converge very fast, and the calculation efficiency can be greatly improved. Certainly, the number of the pixels in the state of "1" needs to be considered in the optimization process, and this factor can gradually reduce the search range by using the approximation criterion, so as to further improve the calculation efficiency. The improved intelligent design process flow can be summarized as:

if the design area is composed of N × M pixel points with the state of 0 or 1, the number of the pixel points with the state of 1 is 0.25N × M, 0.5N × M, 0.75N × M and the like respectively as initial optimization conditions;

next, the achievable optimal distribution of these 0.25N × M, 0.5N × M, and 0.75N × M pixels is solved using PSO or MOPSO, since the search range is only N × M within the two-dimensional range, which greatly reduces the amount of computation compared to the 2N × M solution space;

and then, the number of the pixel points with the optimal state of 1 and the corresponding distribution thereof are obtained by utilizing the approximation criterion.

Thus, different functions can be realized by different arrangements of the lattices. In the step, several modules with the same size of 2 microns multiplied by 2 microns and different functions are designed, and the functional requirements of each module after the structure of the first step are met.

(3) Module combination waveguide connection design and performance verification.

After the design of each module is completed, the modules need to be connected by a waveguide, and in order to meet the requirements of input and output intensity, phase and the like of each module, the length, width and other properties of the waveguide need to be designed to optimize the function of the whole device. After the design is complete, the performance of the device should be further verified, as shown in fig. 3 and 4.

The invention can respectively design different modules for different complex function devices according to the requirements of each user, and the devices can be finely adjusted according to the functional requirements after being designed according to the sequence.

Furthermore, the specific steps of designing the on-chip all-optical half adder by the method are as follows:

s1: deconstructing the function of a half adder, wherein in the digital electronic technology, the half adder is realized by combining an exclusive-OR gate AND an AND gate, wherein the SUM (SUM) output of the half adder is realized by exclusive-OR (XOR) operation, AND the CARRY bit (CARRY) output is realized by AND (AND) operation;

s2: XOR AND AND logic gates are main functional blocks, AND the two logic gates are both in a 2-input-1-output structure, so that a Beam splitter is adopted to split an initial signal AND input the initial signal into the two logic gates respectively, the signals are inevitably crossed before being input into the two logic gates, AND a Hub is adopted to avoid the crossing of the signals;

s3, calculating and analyzing the phases of the output signals of the 5 modules, designing the size, the position and the length of the connecting waveguide of each module, and finally determining that the side length and the length of the connecting waveguide of each module are both 2 mu m after global optimization;

s3: an XOR gate is optimally designed by using an intelligent algorithm, and a device structure which can enable the device to output the maximum output when only one input exists and output the minimum output when two inputs exist is obtained, wherein the final size is 2 Mum multiplied by 2 Mum;

s4: an AND gate is optimally designed by using an intelligent algorithm, AND a device structure which can enable the device to output the maximum output when two inputs exist AND output the minimum output when only one input exists is obtained, wherein the final size is 2 Mum multiplied by 2 Mum;

s5: the Beam Splitter is optimally designed by using an intelligent algorithm, and a device structure which can separate signals according to a fixed proportion and ensure certain transmission efficiency is obtained, wherein the final size is 2 micrometers multiplied by 2 micrometers;

s6: optimally designing Hub by using an intelligent algorithm to obtain a device structure which can cross-transmit signals and ensure no crosstalk basically and has a final size of 2μm multiplied by 2μm;

s7: calculating and analyzing the phase of the output signal of each module, and keeping the phase of the light output by each module consistent before entering the next module, so that the positions of the modules and the lengths of the connecting waveguides can be reasonably arranged to keep the phase of the light entering each module consistent, and finally assembling the modules to obtain the half adder, as shown in fig. 3, wherein (a) in fig. 3 shows a structural diagram of the designed half adder, (b) in fig. 3 shows a result diagram of the half adder with the value of 1+0 being 01, and (c) in fig. 3 shows a result diagram of the half adder with the value of 0+1 being 01, and (d) in fig. 3 shows a result diagram of the half adder with the value of 1+1 being 10;

s8: calculating performance parameters of each module, wherein the extinction ratio of the AND logic gate is 12dB, AND the extinction ratio of the XOR logic gate is 8.45 dB;

s9: the overall performance of the half-adder was calculated to be less than 10 μm x 5 μm in overall size and less than 0.7ps in response time, as shown in fig. 4, with an overall extinction ratio greater than 10 dB.

The invention provides a new idea for the miniaturization design of the on-chip all-optical complex function device by fusing the advantages and the characteristics of intelligent design and modular design for the first time; the invention designs and obtains devices with various functions, the size of the device is only 2 Mum multiplied by 2 Mum, and a new module is provided for a design database of an on-chip all-optical device; the invention obtains the full-optical on-chip half adder with the integral extinction ratio larger than 10dB and the response time smaller than 0.7ps through design, the integral size of the full-optical on-chip half adder is smaller than 10 mu m multiplied by 5 mu m, and the on-chip integration is easy to realize.

It should be noted that, according to the implementation requirement, each step/component described in the present application can be divided into more steps/components, and two or more steps/components or partial operations of the steps/components can be combined into new steps/components to achieve the purpose of the present invention.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An intelligent design method of an all-optical device on a complex function chip is characterized by comprising the following steps:

2. The method of claim 1, wherein step (1) comprises:

3. The method of claim 1 or 2, wherein step (2) comprises:

4. The method of claim 3, wherein step (3) comprises:

5. The method of claim 4, wherein the sub-devices are designed to maintain dimensional and input-output waveguide condition consistency.

6. The method of claim 5, further comprising:

and storing the designed sub-device structure.